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x86: clean up aperture_64.c 

1. use symbolic register names where appropriate.
2. num to bus or slot changing
3. handle for new opteron for bus other than 0

Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Yinghai Lu 2008-04-19 01:31:11 -07:00 committed by Ingo Molnar
parent 7677b2ef6c
commit 55c0d721df
1 changed files with 132 additions and 84 deletions
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216
arch/x86/kernel/aperture_64.c
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@ -35,6 +35,18 @@ int fallback_aper_force __initdata;
int fix_aperture __initdata = 1; int fix_aperture __initdata = 1;
struct bus_dev_range {
int bus;
int dev_base;
int dev_limit;
};
static struct bus_dev_range bus_dev_ranges[] __initdata = {
{ 0x00, 0x18, 0x20},
{ 0xff, 0x00, 0x20},
{ 0xfe, 0x00, 0x20}
};
static struct resource gart_resource = { static struct resource gart_resource = {
.name = "GART", .name = "GART",
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
@ -120,33 +132,33 @@ static int __init aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
} }
/* Find a PCI capability */ /* Find a PCI capability */
static __u32 __init find_cap(int num, int slot, int func, int cap) static __u32 __init find_cap(int bus, int slot, int func, int cap)
{ {
int bytes; int bytes;
u8 pos; u8 pos;
if (!(read_pci_config_16(num, slot, func, PCI_STATUS) & if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
PCI_STATUS_CAP_LIST)) PCI_STATUS_CAP_LIST))
return 0; return 0;
pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST); pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
u8 id; u8 id;
pos &= ~3; pos &= ~3;
id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID); id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
if (id == 0xff) if (id == 0xff)
break; break;
if (id == cap) if (id == cap)
return pos; return pos;
pos = read_pci_config_byte(num, slot, func, pos = read_pci_config_byte(bus, slot, func,
pos+PCI_CAP_LIST_NEXT); pos+PCI_CAP_LIST_NEXT);
} }
return 0; return 0;
} }
/* Read a standard AGPv3 bridge header */ /* Read a standard AGPv3 bridge header */
static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order) static __u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
{ {
u32 apsize; u32 apsize;
u32 apsizereg; u32 apsizereg;
@ -155,8 +167,8 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
u64 aper; u64 aper;
u32 old_order; u32 old_order;
printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func); printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", bus, slot, func);
apsizereg = read_pci_config_16(num, slot, func, cap + 0x14); apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
if (apsizereg == 0xffffffff) { if (apsizereg == 0xffffffff) {
printk(KERN_ERR "APSIZE in AGP bridge unreadable\n"); printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
return 0; return 0;
@ -174,8 +186,8 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
if ((int)*order < 0) /* < 32MB */ if ((int)*order < 0) /* < 32MB */
*order = 0; *order = 0;
aper_low = read_pci_config(num, slot, func, 0x10); aper_low = read_pci_config(bus, slot, func, 0x10);
aper_hi = read_pci_config(num, slot, func, 0x14); aper_hi = read_pci_config(bus, slot, func, 0x14);
aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
/* /*
@ -213,15 +225,15 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
*/ */
static __u32 __init search_agp_bridge(u32 *order, int *valid_agp) static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
{ {
int num, slot, func; int bus, slot, func;
/* Poor man's PCI discovery */ /* Poor man's PCI discovery */
for (num = 0; num < 256; num++) { for (bus = 0; bus < 256; bus++) {
for (slot = 0; slot < 32; slot++) { for (slot = 0; slot < 32; slot++) {
for (func = 0; func < 8; func++) { for (func = 0; func < 8; func++) {
u32 class, cap; u32 class, cap;
u8 type; u8 type;
class = read_pci_config(num, slot, func, class = read_pci_config(bus, slot, func,
PCI_CLASS_REVISION); PCI_CLASS_REVISION);
if (class == 0xffffffff) if (class == 0xffffffff)
break; break;
@ -230,17 +242,17 @@ static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
case PCI_CLASS_BRIDGE_HOST: case PCI_CLASS_BRIDGE_HOST:
case PCI_CLASS_BRIDGE_OTHER: /* needed? */ case PCI_CLASS_BRIDGE_OTHER: /* needed? */
/* AGP bridge? */ /* AGP bridge? */
cap = find_cap(num, slot, func, cap = find_cap(bus, slot, func,
PCI_CAP_ID_AGP); PCI_CAP_ID_AGP);
if (!cap) if (!cap)
break; break;
*valid_agp = 1; *valid_agp = 1;
return read_agp(num, slot, func, cap, return read_agp(bus, slot, func, cap,
order); order);
} }
/* No multi-function device? */ /* No multi-function device? */
type = read_pci_config_byte(num, slot, func, type = read_pci_config_byte(bus, slot, func,
PCI_HEADER_TYPE); PCI_HEADER_TYPE);
if (!(type & 0x80)) if (!(type & 0x80))
break; break;
@ -280,38 +292,49 @@ void __init early_gart_iommu_check(void)
* or BIOS forget to put that in reserved. * or BIOS forget to put that in reserved.
* try to update e820 to make that region as reserved. * try to update e820 to make that region as reserved.
*/ */
int fix, num; int fix, slot;
u32 ctl; u32 ctl;
u32 aper_size = 0, aper_order = 0, last_aper_order = 0; u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
u64 aper_base = 0, last_aper_base = 0; u64 aper_base = 0, last_aper_base = 0;
int aper_enabled = 0, last_aper_enabled = 0; int aper_enabled = 0, last_aper_enabled = 0;
int i;
if (!early_pci_allowed()) if (!early_pci_allowed())
return; return;
fix = 0; fix = 0;
for (num = 24; num < 32; num++) { for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) int bus;
continue; int dev_base, dev_limit;
ctl = read_pci_config(0, num, 3, 0x90); bus = bus_dev_ranges[i].bus;
aper_enabled = ctl & 1; dev_base = bus_dev_ranges[i].dev_base;
aper_order = (ctl >> 1) & 7; dev_limit = bus_dev_ranges[i].dev_limit;
aper_size = (32 * 1024 * 1024) << aper_order;
aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
aper_base <<= 25;
if ((last_aper_order && aper_order != last_aper_order) || for (slot = dev_base; slot < dev_limit; slot++) {
(last_aper_base && aper_base != last_aper_base) || if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
(last_aper_enabled && aper_enabled != last_aper_enabled)) { continue;
fix = 1;
break; ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
aper_enabled = ctl & AMD64_GARTEN;
aper_order = (ctl >> 1) & 7;
aper_size = (32 * 1024 * 1024) << aper_order;
aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
aper_base <<= 25;
if ((last_aper_order && aper_order != last_aper_order) ||
(last_aper_base && aper_base != last_aper_base) ||
(last_aper_enabled && aper_enabled != last_aper_enabled)) {
fix = 1;
goto out;
}
last_aper_order = aper_order;
last_aper_base = aper_base;
last_aper_enabled = aper_enabled;
} }
last_aper_order = aper_order;
last_aper_base = aper_base;
last_aper_enabled = aper_enabled;
} }
out:
if (!fix && !aper_enabled) if (!fix && !aper_enabled)
return; return;
@ -330,13 +353,22 @@ void __init early_gart_iommu_check(void)
} }
/* different nodes have different setting, disable them all at first*/ /* different nodes have different setting, disable them all at first*/
for (num = 24; num < 32; num++) { for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) int bus;
continue; int dev_base, dev_limit;
ctl = read_pci_config(0, num, 3, 0x90); bus = bus_dev_ranges[i].bus;
ctl &= ~1; dev_base = bus_dev_ranges[i].dev_base;
write_pci_config(0, num, 3, 0x90, ctl); dev_limit = bus_dev_ranges[i].dev_limit;
for (slot = dev_base; slot < dev_limit; slot++) {
if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
continue;
ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
ctl &= ~AMD64_GARTEN;
write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
}
} }
} }
@ -348,8 +380,8 @@ void __init gart_iommu_hole_init(void)
u32 agp_aper_base = 0, agp_aper_order = 0; u32 agp_aper_base = 0, agp_aper_order = 0;
u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0; u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
u64 aper_base, last_aper_base = 0; u64 aper_base, last_aper_base = 0;
int fix, num, valid_agp = 0; int fix, slot, valid_agp = 0;
int node; int i, node;
if (gart_iommu_aperture_disabled || !fix_aperture || if (gart_iommu_aperture_disabled || !fix_aperture ||
!early_pci_allowed()) !early_pci_allowed())
@ -362,48 +394,58 @@ void __init gart_iommu_hole_init(void)
fix = 0; fix = 0;
node = 0; node = 0;
for (num = 24; num < 32; num++) { for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) int bus;
continue; int dev_base, dev_limit;
iommu_detected = 1; bus = bus_dev_ranges[i].bus;
gart_iommu_aperture = 1; dev_base = bus_dev_ranges[i].dev_base;
dev_limit = bus_dev_ranges[i].dev_limit;
aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7; for (slot = dev_base; slot < dev_limit; slot++) {
aper_size = (32 * 1024 * 1024) << aper_order; if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff; continue;
aper_base <<= 25;
printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n", iommu_detected = 1;
node, aper_base, aper_size >> 20); gart_iommu_aperture = 1;
node++;
if (!aperture_valid(aper_base, aper_size, 64<<20)) { aper_order = (read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL) >> 1) & 7;
if (valid_agp && agp_aper_base && aper_size = (32 * 1024 * 1024) << aper_order;
agp_aper_base == aper_base && aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
agp_aper_order == aper_order) { aper_base <<= 25;
/* the same between two setting from NB and agp */
if (!no_iommu && end_pfn > MAX_DMA32_PFN && !printed_gart_size_msg) { printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n"); node, aper_base, aper_size >> 20);
printk(KERN_ERR "please increase GART size in your BIOS setup\n"); node++;
printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
printed_gart_size_msg = 1; if (!aperture_valid(aper_base, aper_size, 64<<20)) {
if (valid_agp && agp_aper_base &&
agp_aper_base == aper_base &&
agp_aper_order == aper_order) {
/* the same between two setting from NB and agp */
if (!no_iommu && end_pfn > MAX_DMA32_PFN && !printed_gart_size_msg) {
printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n");
printk(KERN_ERR "please increase GART size in your BIOS setup\n");
printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
printed_gart_size_msg = 1;
}
} else {
fix = 1;
goto out;
} }
} else {
fix = 1;
break;
} }
}
if ((last_aper_order && aper_order != last_aper_order) || if ((last_aper_order && aper_order != last_aper_order) ||
(last_aper_base && aper_base != last_aper_base)) { (last_aper_base && aper_base != last_aper_base)) {
fix = 1; fix = 1;
break; goto out;
}
last_aper_order = aper_order;
last_aper_base = aper_base;
} }
last_aper_order = aper_order;
last_aper_base = aper_base;
} }
out:
if (!fix && !fallback_aper_force) { if (!fix && !fallback_aper_force) {
if (last_aper_base) { if (last_aper_base) {
unsigned long n = (32 * 1024 * 1024) << last_aper_order; unsigned long n = (32 * 1024 * 1024) << last_aper_order;
@ -452,16 +494,22 @@ void __init gart_iommu_hole_init(void)
} }
/* Fix up the north bridges */ /* Fix up the north bridges */
for (num = 24; num < 32; num++) { for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) int bus;
continue; int dev_base, dev_limit;
/* bus = bus_dev_ranges[i].bus;
* Don't enable translation yet. That is done later. dev_base = bus_dev_ranges[i].dev_base;
* Assume this BIOS didn't initialise the GART so dev_limit = bus_dev_ranges[i].dev_limit;
* just overwrite all previous bits for (slot = dev_base; slot < dev_limit; slot++) {
*/ if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
write_pci_config(0, num, 3, 0x90, aper_order<<1); continue;
write_pci_config(0, num, 3, 0x94, aper_alloc>>25);
/* Don't enable translation yet. That is done later.
Assume this BIOS didn't initialise the GART so
just overwrite all previous bits */
write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, aper_order << 1);
write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
}
} }
} }