mirror of https://gitee.com/openkylin/linux.git
drm/tilcdc: Enable palette loading for revision 2 LCDC too
The LCDC revision 2 documentation also mentions the mandatory palette for true color modes. Even if the rev 2 LCDC appears to work just fine without the palette being loaded loading it helps in testing the feature. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This commit is contained in:
Jyri Sarha
parent
f13e088ca8
commit
55e165c4d9
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@ -28,8 +28,8 @@
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#include "tilcdc_regs.h"
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#define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
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#define TILCDC_REV1_PALETTE_SIZE 32
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#define TILCDC_REV1_PALETTE_FIRST_ENTRY 0x4000
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#define TILCDC_PALETTE_SIZE 32
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#define TILCDC_PALETTE_FIRST_ENTRY 0x4000
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struct tilcdc_crtc {
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struct drm_crtc base;
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@ -62,7 +62,7 @@ struct tilcdc_crtc {
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struct work_struct recover_work;
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dma_addr_t palette_dma_handle;
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void *palette_base;
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u16 *palette_base;
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struct completion palette_loaded;
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};
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#define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
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@ -114,23 +114,17 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
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}
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/*
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* The driver currently only supports the RGB565 format for revision 1. For
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* 16 bits-per-pixel the palette block is bypassed, but the first 32 bytes of
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* the framebuffer are still considered palette. The first 16-bit entry must
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* be 0x4000 while all other entries must be zeroed.
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* The driver currently only supports only true color formats. For
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* true color the palette block is bypassed, but a 32 byte palette
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* should still be loaded. The first 16-bit entry must be 0x4000 while
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* all other entries must be zeroed.
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*/
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static void tilcdc_crtc_load_palette(struct drm_crtc *crtc)
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{
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u32 dma_fb_base, dma_fb_ceiling, raster_ctl;
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struct tilcdc_crtc *tilcdc_crtc;
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struct drm_device *dev;
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u16 *first_entry;
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dev = crtc->dev;
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tilcdc_crtc = to_tilcdc_crtc(crtc);
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first_entry = tilcdc_crtc->palette_base;
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*first_entry = TILCDC_REV1_PALETTE_FIRST_ENTRY;
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struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct tilcdc_drm_private *priv = dev->dev_private;
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dma_fb_base = tilcdc_read(dev, LCDC_DMA_FB_BASE_ADDR_0_REG);
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dma_fb_ceiling = tilcdc_read(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG);
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@ -140,23 +134,34 @@ static void tilcdc_crtc_load_palette(struct drm_crtc *crtc)
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tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG,
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tilcdc_crtc->palette_dma_handle);
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tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG,
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(u32)tilcdc_crtc->palette_dma_handle
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+ TILCDC_REV1_PALETTE_SIZE - 1);
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(u32) tilcdc_crtc->palette_dma_handle +
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TILCDC_PALETTE_SIZE - 1);
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/* Load it. */
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tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
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LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
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tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
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LCDC_PALETTE_LOAD_MODE(PALETTE_ONLY));
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/* Set dma load mode for palette loading only. */
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tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
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LCDC_PALETTE_LOAD_MODE(PALETTE_ONLY),
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LCDC_PALETTE_LOAD_MODE_MASK);
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/* Enable the LCDC and wait for palette to be loaded. */
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tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
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/* Enable DMA Palette Loaded Interrupt */
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if (priv->rev == 1)
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tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
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else
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tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_PL_INT_ENA);
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/* Enable LCDC DMA and wait for palette to be loaded. */
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tilcdc_clear_irqstatus(dev, 0xffffffff);
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tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
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wait_for_completion(&tilcdc_crtc->palette_loaded);
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/* Restore the registers. */
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/* Disable LCDC DMA and DMA Palette Loaded Interrupt. */
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tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
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if (priv->rev == 1)
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tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
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else
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tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA);
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/* Restore the registers. */
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tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_fb_base);
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tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, dma_fb_ceiling);
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tilcdc_write(dev, LCDC_RASTER_CTRL_REG, raster_ctl);
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@ -218,7 +223,6 @@ static void tilcdc_crtc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
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struct tilcdc_drm_private *priv = dev->dev_private;
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WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
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mutex_lock(&tilcdc_crtc->enable_lock);
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@ -231,7 +235,7 @@ static void tilcdc_crtc_enable(struct drm_crtc *crtc)
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reset(crtc);
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if (priv->rev == 1 && !completion_done(&tilcdc_crtc->palette_loaded))
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if (!completion_done(&tilcdc_crtc->palette_loaded))
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tilcdc_crtc_load_palette(crtc);
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tilcdc_crtc_enable_irqs(dev);
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@ -281,8 +285,7 @@ static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown)
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* LCDC will not retain the palette when reset. Make sure it gets
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* reloaded on tilcdc_crtc_enable().
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*/
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if (priv->rev == 1)
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reinit_completion(&tilcdc_crtc->palette_loaded);
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reinit_completion(&tilcdc_crtc->palette_loaded);
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drm_crtc_vblank_off(crtc);
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@ -917,12 +920,14 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
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dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow",
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__func__, stat);
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if (priv->rev == 1) {
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if (stat & LCDC_PL_LOAD_DONE) {
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complete(&tilcdc_crtc->palette_loaded);
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tilcdc_clear(dev,
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LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
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}
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if (stat & LCDC_PL_LOAD_DONE) {
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complete(&tilcdc_crtc->palette_loaded);
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if (priv->rev == 1)
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tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
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LCDC_V1_PL_INT_ENA);
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else
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tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
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LCDC_V2_PL_INT_ENA);
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}
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if (stat & LCDC_SYNC_LOST) {
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@ -972,15 +977,14 @@ int tilcdc_crtc_create(struct drm_device *dev)
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return -ENOMEM;
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}
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if (priv->rev == 1) {
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init_completion(&tilcdc_crtc->palette_loaded);
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tilcdc_crtc->palette_base = dmam_alloc_coherent(dev->dev,
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TILCDC_REV1_PALETTE_SIZE,
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init_completion(&tilcdc_crtc->palette_loaded);
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tilcdc_crtc->palette_base = dmam_alloc_coherent(dev->dev,
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TILCDC_PALETTE_SIZE,
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&tilcdc_crtc->palette_dma_handle,
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GFP_KERNEL | __GFP_ZERO);
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if (!tilcdc_crtc->palette_base)
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return -ENOMEM;
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}
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if (!tilcdc_crtc->palette_base)
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return -ENOMEM;
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*tilcdc_crtc->palette_base = TILCDC_PALETTE_FIRST_ENTRY;
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crtc = &tilcdc_crtc->base;
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