mirror of https://gitee.com/openkylin/linux.git
Merge remote-tracking branches 'asoc/topic/arizona', 'asoc/topic/atmel', 'asoc/topic/bt-sco', 'asoc/topic/compress' and 'asoc/topic/cs35l33' into asoc-next
This commit is contained in:
Mark Brown
commit
5600eab2df
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|
@ -4,7 +4,7 @@ This device support generic Bluetooth SCO link.
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|||
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||||
Required properties:
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- compatible : "delta,dfbmcs320"
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- compatible : "delta,dfbmcs320" or "linux,bt-sco"
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Example:
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|
|
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|
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@ -0,0 +1,126 @@
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CS35L33 Speaker Amplifier
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Required properties:
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- compatible : "cirrus,cs35l33"
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- reg : the I2C address of the device for I2C
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- VA-supply, VP-supply : power supplies for the device,
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as covered in
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Documentation/devicetree/bindings/regulator/regulator.txt.
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Optional properties:
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- reset-gpios : gpio used to reset the amplifier
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- interrupt-parent : Specifies the phandle of the interrupt controller to
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which the IRQs from CS35L33 are delivered to.
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- interrupts : IRQ line info CS35L33.
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(See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
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for further information relating to interrupt properties)
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- cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is
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0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
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a value of 1 and will increase at a step size of 100mV until a maximum of
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8000mV.
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- cirrus,ramp-rate : On power up, it affects the time from when the power
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up sequence begins to the time the audio reaches a full-scale output.
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On power down, it affects the time from when the power-down sequence
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begins to when the amplifier disables the PWM outputs. If this property
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is not set then soft ramping will be disabled and ramp time would be
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20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms,
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60ms,100ms,175ms respectively for 48KHz sample rate.
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- cirrus,boost-ipk : The maximum current allowed for the boost converter.
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The range starts at 1850000uA and goes to a maximum of 3600000uA
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with a step size of 15625uA. The default is 2500000uA.
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- cirrus,imon-adc-scale : Configures the scaling of data bits from the IMON
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ADC data word. This property can be set as a value of 0 for bits 15 down
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to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8.
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Optional H/G Algorithm sub-node:
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The cs35l33 node can have a single "cirrus,hg-algo" sub-node that will enable
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the internal H/G Algorithm.
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- cirrus,hg-algo : Sub-node for internal Class H/G algorithm that
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controls the amplifier supplies.
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Optional properties for the "cirrus,hg-algo" sub-node:
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- cirrus,mem-depth : Memory depth for the Class H/G algorithm measured in
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LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
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depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles.
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cirrus,release-rate : The number of consecutive LRCLK periods before
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allowing release condition tracking updates. The number of LRCLK periods
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start at 3 to a maximum of 255.
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- cirrus,ldo-thld : Configures the signal threshold at which the PWM output
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stage enters LDO operation. Starts as a default value of 50mV for a value
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of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
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0xF).
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- cirrus,ldo-path-disable : This is a boolean property. If present, the H/G
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algorithm uses the max detection path. If not present, the LDO
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detection path is used.
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- cirrus,ldo-entry-delay : The LDO entry delay in milliseconds before the H/G
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algorithm switches to the LDO voltage. This property can be set to values
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from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms.
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The default is 100ms.
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- cirrus,vp-hg-auto : This is a boolean property. When set, class H/G VPhg
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automatic updating is enabled.
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- cirrus,vp-hg : Class H/G algorithm VPhg. Controls the H/G algorithm's
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reference to the VP voltage for when to start generating a boosted VBST.
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The reference voltage starts at 3000mV with a value of 0x3 and is increased
|
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by 100mV per step to a maximum of 5500mV.
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- cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is
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allowed to increase to a higher voltage when using VPhg automatic
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tracking. This property can be set to values from 0 to 3 with rates of 128
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periods, 2048 periods, 32768 periods, and 524288 periods.
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The default is 32768 periods.
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|
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- cirrus,vp-hg-va : VA calculation reference for automatic VPhg tracking
|
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using VPMON. This property can be set to values from 0 to 6 starting at
|
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1800mV with a step size of 50mV up to a maximum value of 1750mV.
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Default is 1800mV.
|
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|
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Example:
|
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|
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cs35l33: cs35l33@40 {
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compatible = "cirrus,cs35l33";
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reg = <0x40>;
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|
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VA-supply = <&ldo5_reg>;
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VP-supply = <&ldo5_reg>;
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interrupt-parent = <&gpio8>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&cs47l91 34 0>;
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cirrus,ramp-rate = <0x0>;
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cirrus,boost-ctl = <0x30>; /* VBST = 8000mV */
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cirrus,boost-ipk = <0xE0>; /* 3600mA */
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cirrus,imon-adc-scale = <0> /* Bits 15 down to 0 */
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cirrus,hg-algo {
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cirrus,mem-depth = <0x3>;
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cirrus,release-rate = <0x3>;
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cirrus,ldo-thld = <0x1>;
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cirrus,ldo-path-disable = <0x0>;
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cirrus,ldo-entry-delay=<0x4>;
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cirrus,vp-hg-auto;
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cirrus,vp-hg=<0xF>;
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cirrus,vp-hg-rate=<0x2>;
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cirrus,vp-hg-va=<0x0>;
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};
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};
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@ -0,0 +1,48 @@
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/*
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* linux/sound/cs35l33.h -- Platform data for CS35l33
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*
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* Copyright (c) 2016 Cirrus Logic Inc.
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*
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||||
* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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||||
*/
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||||
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#ifndef __CS35L33_H
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#define __CS35L33_H
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struct cs35l33_hg {
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bool enable_hg_algo;
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unsigned int mem_depth;
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unsigned int release_rate;
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unsigned int hd_rm;
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unsigned int ldo_thld;
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unsigned int ldo_path_disable;
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unsigned int ldo_entry_delay;
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bool vp_hg_auto;
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unsigned int vp_hg;
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unsigned int vp_hg_rate;
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unsigned int vp_hg_va;
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};
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struct cs35l33_pdata {
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/* Boost Controller Voltage Setting */
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unsigned int boost_ctl;
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/* Boost Controller Peak Current */
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unsigned int boost_ipk;
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||||
/* Amplifier Drive Select */
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unsigned int amp_drv_sel;
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/* soft volume ramp */
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unsigned int ramp_rate;
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/* IMON adc scale */
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unsigned int imon_adc_scale;
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/* H/G algo configuration */
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struct cs35l33_hg hg_config;
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};
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||||
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#endif /* __CS35L33_H */
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@ -10,6 +10,7 @@ if SND_ATMEL_SOC
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|||
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||||
config SND_ATMEL_SOC_PDC
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tristate
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||||
depends on HAS_DMA
|
||||
default m if SND_ATMEL_SOC_SSC_PDC=m && SND_ATMEL_SOC_SSC=m
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default y if SND_ATMEL_SOC_SSC_PDC=y || (SND_ATMEL_SOC_SSC_PDC=m && SND_ATMEL_SOC_SSC=y)
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||||
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||||
|
|
|
|||
|
|
@ -593,11 +593,6 @@ static int atmel_classd_probe(struct platform_device *pdev)
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}
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||||
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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||||
if (!res) {
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dev_err(dev, "no memory resource\n");
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return -ENXIO;
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}
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io_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(io_base)) {
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ret = PTR_ERR(io_base);
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|
|
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|||
|
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@ -624,11 +624,6 @@ static int atmel_pdmic_probe(struct platform_device *pdev)
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(dev, "no memory resource\n");
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return -ENXIO;
|
||||
}
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||||
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io_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(io_base)) {
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ret = PTR_ERR(io_base);
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|
|
|
|||
|
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@ -321,7 +321,7 @@ static int atmel_ssc_startup(struct snd_pcm_substream *substream,
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return ret;
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}
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dma_params = &ssc_dma_params[dai->id][dir];
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dma_params = &ssc_dma_params[pdev->id][dir];
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dma_params->ssc = ssc_p->ssc;
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dma_params->substream = substream;
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||||
|
|
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|||
|
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@ -47,6 +47,7 @@ config SND_SOC_ALL_CODECS
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select SND_SOC_BT_SCO
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select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC
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select SND_SOC_CS35L32 if I2C
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select SND_SOC_CS35L33 if I2C
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select SND_SOC_CS42L51_I2C if I2C
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select SND_SOC_CS42L52 if I2C && INPUT
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select SND_SOC_CS42L56 if I2C && INPUT
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@ -380,7 +381,7 @@ config SND_SOC_ALC5632
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tristate
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config SND_SOC_BT_SCO
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tristate
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tristate "Dummy BT SCO codec driver"
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config SND_SOC_CQ0093VC
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tristate
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@ -389,6 +390,10 @@ config SND_SOC_CS35L32
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tristate "Cirrus Logic CS35L32 CODEC"
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depends on I2C
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config SND_SOC_CS35L33
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tristate "Cirrus Logic CS35L33 CODEC"
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depends on I2C
|
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|
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config SND_SOC_CS42L51
|
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tristate
|
||||
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@ snd-soc-arizona-objs := arizona.o
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snd-soc-bt-sco-objs := bt-sco.o
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snd-soc-cq93vc-objs := cq93vc.o
|
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snd-soc-cs35l32-objs := cs35l32.o
|
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snd-soc-cs35l33-objs := cs35l33.o
|
||||
snd-soc-cs42l51-objs := cs42l51.o
|
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snd-soc-cs42l51-i2c-objs := cs42l51-i2c.o
|
||||
snd-soc-cs42l52-objs := cs42l52.o
|
||||
|
|
@ -254,6 +255,7 @@ obj-$(CONFIG_SND_SOC_ARIZONA) += snd-soc-arizona.o
|
|||
obj-$(CONFIG_SND_SOC_BT_SCO) += snd-soc-bt-sco.o
|
||||
obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o
|
||||
obj-$(CONFIG_SND_SOC_CS35L32) += snd-soc-cs35l32.o
|
||||
obj-$(CONFIG_SND_SOC_CS35L33) += snd-soc-cs35l33.o
|
||||
obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o
|
||||
obj-$(CONFIG_SND_SOC_CS42L51_I2C) += snd-soc-cs42l51-i2c.o
|
||||
obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o
|
||||
|
|
|
|||
|
|
@ -85,30 +85,9 @@ static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
|
|||
{
|
||||
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
|
||||
struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
|
||||
struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
|
||||
bool manual_ena = false;
|
||||
int val;
|
||||
|
||||
switch (arizona->type) {
|
||||
case WM5102:
|
||||
switch (arizona->rev) {
|
||||
case 0:
|
||||
break;
|
||||
default:
|
||||
manual_ena = true;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (event) {
|
||||
case SND_SOC_DAPM_PRE_PMU:
|
||||
if (!priv->spk_ena && manual_ena) {
|
||||
regmap_write_async(arizona->regmap, 0x4f5, 0x25a);
|
||||
priv->spk_ena_pending = true;
|
||||
}
|
||||
break;
|
||||
case SND_SOC_DAPM_POST_PMU:
|
||||
val = snd_soc_read(codec, ARIZONA_INTERRUPT_RAW_STATUS_3);
|
||||
if (val & ARIZONA_SPK_OVERHEAT_STS) {
|
||||
|
|
@ -120,33 +99,12 @@ static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
|
|||
regmap_update_bits_async(arizona->regmap,
|
||||
ARIZONA_OUTPUT_ENABLES_1,
|
||||
1 << w->shift, 1 << w->shift);
|
||||
|
||||
if (priv->spk_ena_pending) {
|
||||
msleep(75);
|
||||
regmap_write_async(arizona->regmap, 0x4f5, 0xda);
|
||||
priv->spk_ena_pending = false;
|
||||
priv->spk_ena++;
|
||||
}
|
||||
break;
|
||||
case SND_SOC_DAPM_PRE_PMD:
|
||||
if (manual_ena) {
|
||||
priv->spk_ena--;
|
||||
if (!priv->spk_ena)
|
||||
regmap_write_async(arizona->regmap,
|
||||
0x4f5, 0x25a);
|
||||
}
|
||||
|
||||
regmap_update_bits_async(arizona->regmap,
|
||||
ARIZONA_OUTPUT_ENABLES_1,
|
||||
1 << w->shift, 0);
|
||||
break;
|
||||
case SND_SOC_DAPM_POST_PMD:
|
||||
if (manual_ena) {
|
||||
if (!priv->spk_ena)
|
||||
regmap_write_async(arizona->regmap,
|
||||
0x4f5, 0x0da);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -630,7 +588,7 @@ const struct soc_enum arizona_asrc_rate1 =
|
|||
arizona_rate_text, arizona_rate_val);
|
||||
EXPORT_SYMBOL_GPL(arizona_asrc_rate1);
|
||||
|
||||
static const char *arizona_vol_ramp_text[] = {
|
||||
static const char * const arizona_vol_ramp_text[] = {
|
||||
"0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
|
||||
"15ms/6dB", "30ms/6dB",
|
||||
};
|
||||
|
|
@ -659,7 +617,7 @@ SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp,
|
|||
arizona_vol_ramp_text);
|
||||
EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
|
||||
|
||||
static const char *arizona_lhpf_mode_text[] = {
|
||||
static const char * const arizona_lhpf_mode_text[] = {
|
||||
"Low-pass", "High-pass"
|
||||
};
|
||||
|
||||
|
|
@ -687,7 +645,7 @@ SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode,
|
|||
arizona_lhpf_mode_text);
|
||||
EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
|
||||
|
||||
static const char *arizona_ng_hold_text[] = {
|
||||
static const char * const arizona_ng_hold_text[] = {
|
||||
"30ms", "120ms", "250ms", "500ms",
|
||||
};
|
||||
|
||||
|
|
@ -821,6 +779,14 @@ const struct soc_enum arizona_output_anc_src[] = {
|
|||
};
|
||||
EXPORT_SYMBOL_GPL(arizona_output_anc_src);
|
||||
|
||||
const struct snd_kcontrol_new arizona_voice_trigger_switch[] = {
|
||||
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0),
|
||||
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 1, 1, 0),
|
||||
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 2, 1, 0),
|
||||
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 3, 1, 0),
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(arizona_voice_trigger_switch);
|
||||
|
||||
static void arizona_in_set_vu(struct snd_soc_codec *codec, int ena)
|
||||
{
|
||||
struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
|
||||
|
|
|
|||
|
|
@ -90,9 +90,6 @@ struct arizona_priv {
|
|||
unsigned int out_down_pending;
|
||||
unsigned int out_down_delay;
|
||||
|
||||
unsigned int spk_ena:2;
|
||||
unsigned int spk_ena_pending:1;
|
||||
|
||||
unsigned int dvfs_reqs;
|
||||
struct mutex dvfs_lock;
|
||||
bool dvfs_cached;
|
||||
|
|
@ -255,6 +252,8 @@ extern const struct soc_enum arizona_anc_input_src[];
|
|||
extern const struct soc_enum arizona_anc_ng_enum;
|
||||
extern const struct soc_enum arizona_output_anc_src[];
|
||||
|
||||
extern const struct snd_kcontrol_new arizona_voice_trigger_switch[];
|
||||
|
||||
extern int arizona_in_ev(struct snd_soc_dapm_widget *w,
|
||||
struct snd_kcontrol *kcontrol,
|
||||
int event);
|
||||
|
|
|
|||
|
|
@ -25,22 +25,41 @@ static const struct snd_soc_dapm_route bt_sco_routes[] = {
|
|||
{ "TX", NULL, "Playback" },
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_driver bt_sco_dai = {
|
||||
.name = "bt-sco-pcm",
|
||||
.playback = {
|
||||
.stream_name = "Playback",
|
||||
.channels_min = 1,
|
||||
.channels_max = 1,
|
||||
.rates = SNDRV_PCM_RATE_8000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
.capture = {
|
||||
.stream_name = "Capture",
|
||||
.channels_min = 1,
|
||||
.channels_max = 1,
|
||||
.rates = SNDRV_PCM_RATE_8000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
static struct snd_soc_dai_driver bt_sco_dai[] = {
|
||||
{
|
||||
.name = "bt-sco-pcm",
|
||||
.playback = {
|
||||
.stream_name = "Playback",
|
||||
.channels_min = 1,
|
||||
.channels_max = 1,
|
||||
.rates = SNDRV_PCM_RATE_8000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
.capture = {
|
||||
.stream_name = "Capture",
|
||||
.channels_min = 1,
|
||||
.channels_max = 1,
|
||||
.rates = SNDRV_PCM_RATE_8000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "bt-sco-pcm-wb",
|
||||
.playback = {
|
||||
.stream_name = "Playback",
|
||||
.channels_min = 1,
|
||||
.channels_max = 1,
|
||||
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
.capture = {
|
||||
.stream_name = "Capture",
|
||||
.channels_min = 1,
|
||||
.channels_max = 1,
|
||||
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
static struct snd_soc_codec_driver soc_codec_dev_bt_sco = {
|
||||
|
|
@ -53,7 +72,7 @@ static struct snd_soc_codec_driver soc_codec_dev_bt_sco = {
|
|||
static int bt_sco_probe(struct platform_device *pdev)
|
||||
{
|
||||
return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_bt_sco,
|
||||
&bt_sco_dai, 1);
|
||||
bt_sco_dai, ARRAY_SIZE(bt_sco_dai));
|
||||
}
|
||||
|
||||
static int bt_sco_remove(struct platform_device *pdev)
|
||||
|
|
@ -77,6 +96,7 @@ MODULE_DEVICE_TABLE(platform, bt_sco_driver_ids);
|
|||
#if defined(CONFIG_OF)
|
||||
static const struct of_device_id bt_sco_codec_of_match[] = {
|
||||
{ .compatible = "delta,dfbmcs320", },
|
||||
{ .compatible = "linux,bt-sco", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, bt_sco_codec_of_match);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,221 @@
|
|||
/*
|
||||
* cs35l33.h -- CS35L33 ALSA SoC audio driver
|
||||
*
|
||||
* Copyright 2016 Cirrus Logic, Inc.
|
||||
*
|
||||
* Author: Paul Handrigan <paul.handrigan@cirrus.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CS35L33_H__
|
||||
#define __CS35L33_H__
|
||||
|
||||
#define CS35L33_CHIP_ID 0x00035A33
|
||||
#define CS35L33_DEVID_AB 0x01 /* Device ID A & B [RO] */
|
||||
#define CS35L33_DEVID_CD 0x02 /* Device ID C & D [RO] */
|
||||
#define CS35L33_DEVID_E 0x03 /* Device ID E [RO] */
|
||||
#define CS35L33_FAB_ID 0x04 /* Fab ID [RO] */
|
||||
#define CS35L33_REV_ID 0x05 /* Revision ID [RO] */
|
||||
#define CS35L33_PWRCTL1 0x06 /* Power Ctl 1 */
|
||||
#define CS35L33_PWRCTL2 0x07 /* Power Ctl 2 */
|
||||
#define CS35L33_CLK_CTL 0x08 /* Clock Ctl */
|
||||
#define CS35L33_BST_PEAK_CTL 0x09 /* Max Current for Boost */
|
||||
#define CS35L33_PROTECT_CTL 0x0A /* Amp Protection Parameters */
|
||||
#define CS35L33_BST_CTL1 0x0B /* Boost Converter CTL1 */
|
||||
#define CS35L33_BST_CTL2 0x0C /* Boost Converter CTL2 */
|
||||
#define CS35L33_ADSP_CTL 0x0D /* Serial Port Control */
|
||||
#define CS35L33_ADC_CTL 0x0E /* ADC Control */
|
||||
#define CS35L33_DAC_CTL 0x0F /* DAC Control */
|
||||
#define CS35L33_DIG_VOL_CTL 0x10 /* Digital Volume CTL */
|
||||
#define CS35L33_CLASSD_CTL 0x11 /* Class D Amp CTL */
|
||||
#define CS35L33_AMP_CTL 0x12 /* Amp Gain/Protecton Release CTL */
|
||||
#define CS35L33_INT_MASK_1 0x13 /* Interrupt Mask 1 */
|
||||
#define CS35L33_INT_MASK_2 0x14 /* Interrupt Mask 2 */
|
||||
#define CS35L33_INT_STATUS_1 0x15 /* Interrupt Status 1 [RO] */
|
||||
#define CS35L33_INT_STATUS_2 0x16 /* Interrupt Status 2 [RO] */
|
||||
#define CS35L33_DIAG_LOCK 0x17 /* Diagnostic Mode Register Lock */
|
||||
#define CS35L33_DIAG_CTRL_1 0x18 /* Diagnostic Mode Register Control */
|
||||
#define CS35L33_DIAG_CTRL_2 0x19 /* Diagnostic Mode Register Control 2 */
|
||||
#define CS35L33_HG_MEMLDO_CTL 0x23 /* H/G Memory/LDO CTL */
|
||||
#define CS35L33_HG_REL_RATE 0x24 /* H/G Release Rate */
|
||||
#define CS35L33_LDO_DEL 0x25 /* LDO Entry Delay/VPhg Control 1 */
|
||||
#define CS35L33_HG_HEAD 0x29 /* H/G Headroom */
|
||||
#define CS35L33_HG_EN 0x2A /* H/G Enable/VPhg CNT2 */
|
||||
#define CS35L33_TX_VMON 0x2D /* TDM TX Control 1 (VMON) */
|
||||
#define CS35L33_TX_IMON 0x2E /* TDM TX Control 2 (IMON) */
|
||||
#define CS35L33_TX_VPMON 0x2F /* TDM TX Control 3 (VPMON) */
|
||||
#define CS35L33_TX_VBSTMON 0x30 /* TDM TX Control 4 (VBSTMON) */
|
||||
#define CS35L33_TX_FLAG 0x31 /* TDM TX Control 5 (FLAG) */
|
||||
#define CS35L33_TX_EN1 0x32 /* TDM TX Enable 1 */
|
||||
#define CS35L33_TX_EN2 0x33 /* TDM TX Enable 2 */
|
||||
#define CS35L33_TX_EN3 0x34 /* TDM TX Enable 3 */
|
||||
#define CS35L33_TX_EN4 0x35 /* TDM TX Enable 4 */
|
||||
#define CS35L33_RX_AUD 0x36 /* TDM RX Control 1 */
|
||||
#define CS35L33_RX_SPLY 0x37 /* TDM RX Control 2 */
|
||||
#define CS35L33_RX_ALIVE 0x38 /* TDM RX Control 3 */
|
||||
#define CS35L33_BST_CTL4 0x39 /* Boost Converter Control 4 */
|
||||
#define CS35L33_HG_STATUS 0x3F /* H/G Status */
|
||||
#define CS35L33_MAX_REGISTER 0x59
|
||||
|
||||
#define CS35L33_MCLK_5644 5644800
|
||||
#define CS35L33_MCLK_6144 6144000
|
||||
#define CS35L33_MCLK_6 6000000
|
||||
#define CS35L33_MCLK_11289 11289600
|
||||
#define CS35L33_MCLK_12 12000000
|
||||
#define CS35L33_MCLK_12288 12288000
|
||||
|
||||
/* CS35L33_PWRCTL1 */
|
||||
#define CS35L33_PDN_AMP (1 << 7)
|
||||
#define CS35L33_PDN_BST (1 << 2)
|
||||
#define CS35L33_PDN_ALL 1
|
||||
|
||||
/* CS35L33_PWRCTL2 */
|
||||
#define CS35L33_PDN_VMON_SHIFT 7
|
||||
#define CS35L33_PDN_VMON (1 << CS35L33_PDN_VMON_SHIFT)
|
||||
#define CS35L33_PDN_IMON_SHIFT 6
|
||||
#define CS35L33_PDN_IMON (1 << CS35L33_PDN_IMON_SHIFT)
|
||||
#define CS35L33_PDN_VPMON_SHIFT 5
|
||||
#define CS35L33_PDN_VPMON (1 << CS35L33_PDN_VPMON_SHIFT)
|
||||
#define CS35L33_PDN_VBSTMON_SHIFT 4
|
||||
#define CS35L33_PDN_VBSTMON (1 << CS35L33_PDN_VBSTMON_SHIFT)
|
||||
#define CS35L33_SDOUT_3ST_I2S_SHIFT 3
|
||||
#define CS35L33_SDOUT_3ST_I2S (1 << CS35L33_SDOUT_3ST_I2S_SHIFT)
|
||||
#define CS35L33_PDN_SDIN_SHIFT 2
|
||||
#define CS35L33_PDN_SDIN (1 << CS35L33_PDN_SDIN_SHIFT)
|
||||
#define CS35L33_PDN_TDM_SHIFT 1
|
||||
#define CS35L33_PDN_TDM (1 << CS35L33_PDN_TDM_SHIFT)
|
||||
|
||||
/* CS35L33_CLK_CTL */
|
||||
#define CS35L33_MCLKDIS (1 << 7)
|
||||
#define CS35L33_MCLKDIV2 (1 << 6)
|
||||
#define CS35L33_SDOUT_3ST_TDM (1 << 5)
|
||||
#define CS35L33_INT_FS_RATE (1 << 4)
|
||||
#define CS35L33_ADSP_FS 0xF
|
||||
|
||||
/* CS35L33_PROTECT_CTL */
|
||||
#define CS35L33_ALIVE_WD_DIS (3 << 2)
|
||||
|
||||
/* CS35L33_BST_CTL1 */
|
||||
#define CS35L33_BST_CTL_SRC (1 << 6)
|
||||
#define CS35L33_BST_CTL_SHIFT (1 << 5)
|
||||
#define CS35L33_BST_CTL_MASK 0x3F
|
||||
|
||||
/* CS35L33_BST_CTL2 */
|
||||
#define CS35L33_TDM_WD_SEL (1 << 4)
|
||||
#define CS35L33_ALIVE_WD_DIS2 (1 << 3)
|
||||
#define CS35L33_VBST_SR_STEP 0x3
|
||||
|
||||
/* CS35L33_ADSP_CTL */
|
||||
#define CS35L33_ADSP_DRIVE (1 << 7)
|
||||
#define CS35L33_MS_MASK (1 << 6)
|
||||
#define CS35L33_SDIN_LOC (3 << 4)
|
||||
#define CS35L33_ALIVE_RATE 0x3
|
||||
|
||||
/* CS35L33_ADC_CTL */
|
||||
#define CS35L33_INV_VMON (1 << 7)
|
||||
#define CS35L33_INV_IMON (1 << 6)
|
||||
#define CS35L33_ADC_NOTCH_DIS (1 << 5)
|
||||
#define CS35L33_IMON_SCALE 0xF
|
||||
|
||||
/* CS35L33_DAC_CTL */
|
||||
#define CS35L33_INV_DAC (1 << 7)
|
||||
#define CS35L33_DAC_NOTCH_DIS (1 << 5)
|
||||
#define CS35L33_DIGSFT (1 << 4)
|
||||
#define CS35L33_DSR_RATE 0xF
|
||||
|
||||
/* CS35L33_CLASSD_CTL */
|
||||
#define CS35L33_AMP_SD (1 << 6)
|
||||
#define CS35L33_AMP_DRV_SEL_SRC (1 << 5)
|
||||
#define CS35L33_AMP_DRV_SEL_MASK 0x10
|
||||
#define CS35L33_AMP_DRV_SEL_SHIFT 4
|
||||
#define CS35L33_AMP_CAL (1 << 3)
|
||||
#define CS35L33_GAIN_CHG_ZC_MASK 0x04
|
||||
#define CS35L33_GAIN_CHG_ZC_SHIFT 2
|
||||
#define CS35L33_CLASS_D_CTL_MASK 0x3F
|
||||
|
||||
/* CS35L33_AMP_CTL */
|
||||
#define CS35L33_AMP_GAIN 0xF0
|
||||
#define CS35L33_CAL_ERR_RLS (1 << 3)
|
||||
#define CS35L33_AMP_SHORT_RLS (1 << 2)
|
||||
#define CS35L33_OTW_RLS (1 << 1)
|
||||
#define CS35L33_OTE_RLS 1
|
||||
|
||||
/* CS35L33_INT_MASK_1 */
|
||||
#define CS35L33_M_CAL_ERR_SHIFT 6
|
||||
#define CS35L33_M_CAL_ERR (1 << CS35L33_M_CAL_ERR_SHIFT)
|
||||
#define CS35L33_M_ALIVE_ERR_SHIFT 5
|
||||
#define CS35L33_M_ALIVE_ERR (1 << CS35L33_M_ALIVE_ERR_SHIFT)
|
||||
#define CS35L33_M_AMP_SHORT_SHIFT 2
|
||||
#define CS35L33_M_AMP_SHORT (1 << CS35L33_M_AMP_SHORT_SHIFT)
|
||||
#define CS35L33_M_OTW_SHIFT 1
|
||||
#define CS35L33_M_OTW (1 << CS35L33_M_OTW_SHIFT)
|
||||
#define CS35L33_M_OTE_SHIFT 0
|
||||
#define CS35L33_M_OTE (1 << CS35L33_M_OTE_SHIFT)
|
||||
|
||||
/* CS35L33_INT_STATUS_1 */
|
||||
#define CS35L33_CAL_ERR (1 << 6)
|
||||
#define CS35L33_ALIVE_ERR (1 << 5)
|
||||
#define CS35L33_ADSPCLK_ERR (1 << 4)
|
||||
#define CS35L33_MCLK_ERR (1 << 3)
|
||||
#define CS35L33_AMP_SHORT (1 << 2)
|
||||
#define CS35L33_OTW (1 << 1)
|
||||
#define CS35L33_OTE (1 << 0)
|
||||
|
||||
/* CS35L33_INT_STATUS_2 */
|
||||
#define CS35L33_VMON_OVFL (1 << 7)
|
||||
#define CS35L33_IMON_OVFL (1 << 6)
|
||||
#define CS35L33_VPMON_OVFL (1 << 5)
|
||||
#define CS35L33_VBSTMON_OVFL (1 << 4)
|
||||
#define CS35L33_PDN_DONE 1
|
||||
|
||||
/* CS35L33_BST_CTL4 */
|
||||
#define CS35L33_BST_RGS 0x70
|
||||
#define CS35L33_BST_COEFF3 0xF
|
||||
|
||||
/* CS35L33_HG_MEMLDO_CTL */
|
||||
#define CS35L33_MEM_DEPTH_SHIFT 5
|
||||
#define CS35L33_MEM_DEPTH_MASK (0x3 << CS35L33_MEM_DEPTH_SHIFT)
|
||||
#define CS35L33_LDO_THLD_SHIFT 1
|
||||
#define CS35L33_LDO_THLD_MASK (0xF << CS35L33_LDO_THLD_SHIFT)
|
||||
#define CS35L33_LDO_DISABLE_SHIFT 0
|
||||
#define CS35L33_LDO_DISABLE_MASK (0x1 << CS35L33_LDO_DISABLE_SHIFT)
|
||||
|
||||
/* CS35L33_LDO_DEL */
|
||||
#define CS35L33_VP_HG_VA_SHIFT 5
|
||||
#define CS35L33_VP_HG_VA_MASK (0x7 << CS35L33_VP_HG_VA_SHIFT)
|
||||
#define CS35L33_LDO_ENTRY_DELAY_SHIFT 2
|
||||
#define CS35L33_LDO_ENTRY_DELAY_MASK (0x7 << CS35L33_LDO_ENTRY_DELAY_SHIFT)
|
||||
#define CS35L33_VP_HG_RATE_SHIFT 0
|
||||
#define CS35L33_VP_HG_RATE_MASK (0x3 << CS35L33_VP_HG_RATE_SHIFT)
|
||||
|
||||
/* CS35L33_HG_HEAD */
|
||||
#define CS35L33_HD_RM_SHIFT 0
|
||||
#define CS35L33_HD_RM_MASK (0x7F << CS35L33_HD_RM_SHIFT)
|
||||
|
||||
/* CS35L33_HG_EN */
|
||||
#define CS35L33_CLASS_HG_ENA_SHIFT 7
|
||||
#define CS35L33_CLASS_HG_EN_MASK (0x1 << CS35L33_CLASS_HG_ENA_SHIFT)
|
||||
#define CS35L33_VP_HG_AUTO_SHIFT 6
|
||||
#define CS35L33_VP_HG_AUTO_MASK (0x1 << 6)
|
||||
#define CS35L33_VP_HG_SHIFT 0
|
||||
#define CS35L33_VP_HG_MASK (0x1F << CS35L33_VP_HG_SHIFT)
|
||||
|
||||
#define CS35L33_RATES (SNDRV_PCM_RATE_8000_48000)
|
||||
#define CS35L33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
|
||||
SNDRV_PCM_FMTBIT_S24_LE)
|
||||
|
||||
/* CS35L33_{RX,TX}_X */
|
||||
#define CS35L33_X_STATE_SHIFT 7
|
||||
#define CS35L33_X_STATE (1 << CS35L33_X_STATE_SHIFT)
|
||||
#define CS35L33_X_LOC_SHIFT 0
|
||||
#define CS35L33_X_LOC (0x1F << CS35L33_X_LOC_SHIFT)
|
||||
|
||||
/* CS35L33_RX_AUD */
|
||||
#define CS35L33_AUDIN_RX_DEPTH_SHIFT 5
|
||||
#define CS35L33_AUDIN_RX_DEPTH (0x7 << CS35L33_AUDIN_RX_DEPTH_SHIFT)
|
||||
|
||||
#endif
|
||||
|
|
@ -359,6 +359,11 @@ SND_SOC_DAPM_INPUT("IN2R"),
|
|||
SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
|
||||
SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
|
||||
|
||||
SND_SOC_DAPM_OUTPUT("DSP Voice Trigger"),
|
||||
|
||||
SND_SOC_DAPM_SWITCH("DSP3 Voice Trigger", SND_SOC_NOPM, 2, 0,
|
||||
&arizona_voice_trigger_switch[2]),
|
||||
|
||||
SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT,
|
||||
0, NULL, 0, arizona_in_ev,
|
||||
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
|
||||
|
|
@ -899,10 +904,16 @@ static const struct snd_soc_dapm_route cs47l24_dapm_routes[] = {
|
|||
|
||||
{ "MICSUPP", NULL, "SYSCLK" },
|
||||
|
||||
{ "DRC1 Signal Activity", NULL, "SYSCLK" },
|
||||
{ "DRC2 Signal Activity", NULL, "SYSCLK" },
|
||||
{ "DRC1 Signal Activity", NULL, "DRC1L" },
|
||||
{ "DRC1 Signal Activity", NULL, "DRC1R" },
|
||||
{ "DRC2 Signal Activity", NULL, "DRC2L" },
|
||||
{ "DRC2 Signal Activity", NULL, "DRC2R" },
|
||||
|
||||
{ "DSP Voice Trigger", NULL, "SYSCLK" },
|
||||
{ "DSP Voice Trigger", NULL, "DSP3 Voice Trigger" },
|
||||
{ "DSP3 Voice Trigger", "Switch", "DSP3" },
|
||||
};
|
||||
|
||||
static int cs47l24_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
|
||||
|
|
|
|||
|
|
@ -1713,6 +1713,7 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = {
|
|||
|
||||
{ "MICSUPP", NULL, "SYSCLK" },
|
||||
|
||||
{ "DRC1 Signal Activity", NULL, "SYSCLK" },
|
||||
{ "DRC1 Signal Activity", NULL, "DRC1L" },
|
||||
{ "DRC1 Signal Activity", NULL, "DRC1R" },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1104,6 +1104,11 @@ SND_SOC_DAPM_INPUT("IN4R"),
|
|||
SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"),
|
||||
SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"),
|
||||
|
||||
SND_SOC_DAPM_OUTPUT("DSP Voice Trigger"),
|
||||
|
||||
SND_SOC_DAPM_SWITCH("DSP3 Voice Trigger", SND_SOC_NOPM, 2, 0,
|
||||
&arizona_voice_trigger_switch[2]),
|
||||
|
||||
SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT,
|
||||
0, NULL, 0, wm5110_in_ev,
|
||||
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
|
||||
|
|
@ -1998,10 +2003,16 @@ static const struct snd_soc_dapm_route wm5110_dapm_routes[] = {
|
|||
|
||||
{ "MICSUPP", NULL, "SYSCLK" },
|
||||
|
||||
{ "DRC1 Signal Activity", NULL, "SYSCLK" },
|
||||
{ "DRC2 Signal Activity", NULL, "SYSCLK" },
|
||||
{ "DRC1 Signal Activity", NULL, "DRC1L" },
|
||||
{ "DRC1 Signal Activity", NULL, "DRC1R" },
|
||||
{ "DRC2 Signal Activity", NULL, "DRC2L" },
|
||||
{ "DRC2 Signal Activity", NULL, "DRC2R" },
|
||||
|
||||
{ "DSP Voice Trigger", NULL, "SYSCLK" },
|
||||
{ "DSP Voice Trigger", NULL, "DSP3 Voice Trigger" },
|
||||
{ "DSP3 Voice Trigger", "Switch", "DSP3" },
|
||||
};
|
||||
|
||||
static int wm5110_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
|
||||
|
|
|
|||
|
|
@ -1166,6 +1166,7 @@ static const struct snd_soc_dapm_route wm8998_dapm_routes[] = {
|
|||
|
||||
{ "MICSUPP", NULL, "SYSCLK" },
|
||||
|
||||
{ "DRC1 Signal Activity", NULL, "SYSCLK" },
|
||||
{ "DRC1 Signal Activity", NULL, "DRC1L" },
|
||||
{ "DRC1 Signal Activity", NULL, "DRC1R" },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -394,6 +394,7 @@ static const struct {
|
|||
int compr_direction;
|
||||
int num_caps;
|
||||
const struct wm_adsp_fw_caps *caps;
|
||||
bool voice_trigger;
|
||||
} wm_adsp_fw[WM_ADSP_NUM_FW] = {
|
||||
[WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
|
||||
[WM_ADSP_FW_HIFI] = { .file = "hifi" },
|
||||
|
|
@ -406,6 +407,7 @@ static const struct {
|
|||
.compr_direction = SND_COMPRESS_CAPTURE,
|
||||
.num_caps = ARRAY_SIZE(ctrl_caps),
|
||||
.caps = ctrl_caps,
|
||||
.voice_trigger = true,
|
||||
},
|
||||
[WM_ADSP_FW_ASR] = { .file = "asr" },
|
||||
[WM_ADSP_FW_TRACE] = {
|
||||
|
|
@ -3000,6 +3002,9 @@ int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
|
|||
goto out;
|
||||
}
|
||||
|
||||
if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
|
||||
ret = WM_ADSP_COMPR_VOICE_TRIGGER;
|
||||
|
||||
out_notify:
|
||||
if (compr && compr->stream)
|
||||
snd_compr_fragment_elapsed(compr->stream);
|
||||
|
|
|
|||
|
|
@ -19,6 +19,10 @@
|
|||
|
||||
#include "wmfw.h"
|
||||
|
||||
/* Return values for wm_adsp_compr_handle_irq */
|
||||
#define WM_ADSP_COMPR_OK 0
|
||||
#define WM_ADSP_COMPR_VOICE_TRIGGER 1
|
||||
|
||||
struct wm_adsp_region {
|
||||
int type;
|
||||
unsigned int base;
|
||||
|
|
|
|||
|
|
@ -530,14 +530,15 @@ static int soc_compr_pointer(struct snd_compr_stream *cstream,
|
|||
{
|
||||
struct snd_soc_pcm_runtime *rtd = cstream->private_data;
|
||||
struct snd_soc_platform *platform = rtd->platform;
|
||||
int ret = 0;
|
||||
|
||||
mutex_lock_nested(&rtd->pcm_mutex, rtd->pcm_subclass);
|
||||
|
||||
if (platform->driver->compr_ops && platform->driver->compr_ops->pointer)
|
||||
platform->driver->compr_ops->pointer(cstream, tstamp);
|
||||
ret = platform->driver->compr_ops->pointer(cstream, tstamp);
|
||||
|
||||
mutex_unlock(&rtd->pcm_mutex);
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int soc_compr_copy(struct snd_compr_stream *cstream,
|
||||
|
|
|
|||
Loading…
Reference in New Issue