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drm/sun4i: tcon: Introduce LVDS setup routine setting 

Different sunxi flavors require slightly different sequence for enabling
LVDS output. This allows to differentiate between them.

Signed-off-by: Andrey Lebedev <andrey@lebedev.lt>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20200219180858.4806-2-andrey.lebedev@gmail.com
This commit is contained in:
Andrey Lebedev 2020-02-19 20:08:54 +02:00 committed by Maxime Ripard
parent 80579bf36c
commit 5627c9d8dd
No known key found for this signature in database
GPG Key ID: E3EF0D6F671851C5
2 changed files with 38 additions and 32 deletions
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67
drivers/gpu/drm/sun4i/sun4i_tcon.c
View File

@ -114,46 +114,47 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
}
}
static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
const struct drm_encoder *encoder)
{
u8 val;
regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
SUN6I_TCON0_LVDS_ANA0_C(2) |
SUN6I_TCON0_LVDS_ANA0_V(3) |
SUN6I_TCON0_LVDS_ANA0_PD(2) |
SUN6I_TCON0_LVDS_ANA0_EN_LDO);
udelay(2);
regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
SUN6I_TCON0_LVDS_ANA0_EN_MB,
SUN6I_TCON0_LVDS_ANA0_EN_MB);
udelay(2);
regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
if (sun4i_tcon_get_pixel_depth(encoder) == 18)
val = 7;
else
val = 0xf;
regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
}
static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
const struct drm_encoder *encoder,
bool enabled)
{
if (enabled) {
u8 val;
regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
SUN4I_TCON0_LVDS_IF_EN,
SUN4I_TCON0_LVDS_IF_EN);
/*
* As their name suggest, these values only apply to the A31
* and later SoCs. We'll have to rework this when merging
* support for the older SoCs.
*/
regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
SUN6I_TCON0_LVDS_ANA0_C(2) |
SUN6I_TCON0_LVDS_ANA0_V(3) |
SUN6I_TCON0_LVDS_ANA0_PD(2) |
SUN6I_TCON0_LVDS_ANA0_EN_LDO);
udelay(2);
regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
SUN6I_TCON0_LVDS_ANA0_EN_MB,
SUN6I_TCON0_LVDS_ANA0_EN_MB);
udelay(2);
regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
if (sun4i_tcon_get_pixel_depth(encoder) == 18)
val = 7;
else
val = 0xf;
regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
if (tcon->quirks->setup_lvds_phy)
tcon->quirks->setup_lvds_phy(tcon, encoder);
} else {
regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
SUN4I_TCON0_LVDS_IF_EN, 0);
@ -1465,12 +1466,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
.has_channel_0 = true,
.has_lvds_alt = true,
.dclk_min_div = 1,
.setup_lvds_phy = sun6i_tcon_setup_lvds_phy,
};
static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
.supports_lvds = true,
.has_channel_0 = true,
.dclk_min_div = 1,
.setup_lvds_phy = sun6i_tcon_setup_lvds_phy,
};
static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {

3
drivers/gpu/drm/sun4i/sun4i_tcon.h
View File

@ -228,6 +228,9 @@ struct sun4i_tcon_quirks {
/* callback to handle tcon muxing options */
int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
/* handler for LVDS setup routine */
void (*setup_lvds_phy)(struct sun4i_tcon *tcon,
const struct drm_encoder *encoder);
};
struct sun4i_tcon {