mirror of https://gitee.com/openkylin/linux.git
mt76x0: unify rssi_offset parsing
Unify rssi_offset parsing with mt76x2 driver using eeprom utility routines available in mt76x02-lib module Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
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@ -103,11 +103,8 @@ mt76x0_eeprom_param_read(struct seq_file *file, void *data)
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int i;
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seq_printf(file, "RF freq offset: %hhx\n", dev->ee->rf_freq_off);
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seq_printf(file, "RSSI offset 2GHz: %hhx %hhx\n",
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dev->ee->rssi_offset_2ghz[0], dev->ee->rssi_offset_2ghz[1]);
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seq_printf(file, "RSSI offset 5GHz: %hhx %hhx %hhx\n",
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dev->ee->rssi_offset_5ghz[0], dev->ee->rssi_offset_5ghz[1],
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dev->ee->rssi_offset_5ghz[2]);
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seq_printf(file, "RSSI offset: %hhx %hhx\n",
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dev->caldata.rssi_offset[0], dev->caldata.rssi_offset[1]);
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seq_printf(file, "Temperature offset: %hhx\n", dev->ee->temp_off);
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seq_printf(file, "LNA gain: %x\n", dev->caldata.lna_gain);
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@ -126,44 +126,21 @@ void mt76x0_read_rx_gain(struct mt76x0_dev *dev)
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{
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struct ieee80211_channel *chan = dev->mt76.chandef.chan;
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struct mt76x0_caldata *caldata = &dev->caldata;
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s8 lna_5g[3], lna_2g;
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s8 val, lna_5g[3], lna_2g;
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u16 rssi_offset;
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int i;
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mt76x02_get_rx_gain(&dev->mt76, chan->band, &rssi_offset,
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&lna_2g, lna_5g);
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caldata->lna_gain = mt76x02_get_lna_gain(&dev->mt76, &lna_2g,
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lna_5g, chan);
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}
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for (i = 0; i < ARRAY_SIZE(caldata->rssi_offset); i++) {
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val = rssi_offset >> (8 * i);
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if (val < -10 || val > 10)
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val = 0;
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static void
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mt76x0_set_rssi_offset(struct mt76x0_dev *dev, u8 *eeprom)
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{
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int i;
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s8 *rssi_offset = dev->ee->rssi_offset_2ghz;
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for (i = 0; i < 2; i++) {
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rssi_offset[i] = eeprom[MT_EE_RSSI_OFFSET_2G_0 + i];
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if (rssi_offset[i] < -10 || rssi_offset[i] > 10) {
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dev_warn(dev->mt76.dev,
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"Warning: EEPROM RSSI is invalid %02hhx\n",
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rssi_offset[i]);
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rssi_offset[i] = 0;
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}
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}
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rssi_offset = dev->ee->rssi_offset_5ghz;
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for (i = 0; i < 3; i++) {
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rssi_offset[i] = eeprom[MT_EE_RSSI_OFFSET_5G_0 + i];
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if (rssi_offset[i] < -10 || rssi_offset[i] > 10) {
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dev_warn(dev->mt76.dev,
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"Warning: EEPROM RSSI is invalid %02hhx\n",
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rssi_offset[i]);
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rssi_offset[i] = 0;
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}
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caldata->rssi_offset[i] = val;
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}
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}
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@ -311,7 +288,6 @@ mt76x0_eeprom_init(struct mt76x0_dev *dev)
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mt76x0_set_chip_cap(dev, eeprom);
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mt76x0_set_rf_freq_off(dev, eeprom);
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mt76x0_set_temp_offset(dev, eeprom);
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mt76x0_set_rssi_offset(dev, eeprom);
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dev->chainmask = 0x0101;
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mt76x0_set_tx_power_per_rate(dev, eeprom);
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@ -29,14 +29,13 @@ struct reg_channel_bounds {
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};
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struct mt76x0_caldata {
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s8 rssi_offset[2];
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s8 lna_gain;
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};
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struct mt76x0_eeprom_params {
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u8 rf_freq_off;
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s16 temp_off;
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s8 rssi_offset_2ghz[2];
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s8 rssi_offset_5ghz[3];
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/* TX_PWR_CFG_* values from EEPROM for 20 and 40 Mhz bandwidths. */
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u32 tx_pwr_cfg_2g[5][2];
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@ -229,18 +229,8 @@ mt76x0_bbp_set_ctrlch(struct mt76x0_dev *dev, enum nl80211_chan_width width,
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int mt76x0_phy_get_rssi(struct mt76x0_dev *dev, struct mt76x02_rxwi *rxwi)
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{
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struct mt76x0_caldata *caldata = &dev->caldata;
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s8 rssi_offset;
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int val;
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if (dev->mt76.chandef.chan->band == NL80211_BAND_2GHZ) {
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rssi_offset = dev->ee->rssi_offset_2ghz[0];
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} else {
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rssi_offset = dev->ee->rssi_offset_5ghz[0];
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}
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val = rxwi->rssi[0] + rssi_offset - caldata->lna_gain;
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return val;
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return rxwi->rssi[0] + caldata->rssi_offset[0] - caldata->lna_gain;
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}
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static void mt76x0_vco_cal(struct mt76x0_dev *dev, u8 channel)
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