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phy: stm32: ensure pll is disabled before phys creation
To ensure a good balancing of regulators, force PLL disable either by reset or by clearing the PLLEN bit. If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER instead of polling the PLLEN bit, which will be low at the next probe. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210105090525.23164-5-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -8,7 +8,7 @@
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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@ -334,7 +334,7 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct device_node *child, *np = dev->of_node;
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struct phy_provider *phy_provider;
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u32 version;
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u32 pllen, version;
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int ret, port = 0;
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usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
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@ -366,6 +366,19 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
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ret = PTR_ERR(usbphyc->rst);
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if (ret == -EPROBE_DEFER)
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goto clk_disable;
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stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
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}
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/*
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* Wait for minimum width of powerdown pulse (ENABLE = Low):
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* we have to ensure the PLL is disabled before phys initialization.
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*/
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if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
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pllen, !(pllen & PLLEN), 5, 50)) {
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dev_warn(usbphyc->dev, "PLL not reset\n");
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ret = -EPROBE_DEFER;
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goto clk_disable;
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}
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usbphyc->switch_setup = -EINVAL;
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