mirror of https://gitee.com/openkylin/linux.git
drm/i915: Clear TX FIFO reset master override bits on chv
Clear the override bits to make sure the hardware manages the TX FIFO reset master on its own. v2: Squash with the earlier attempt at forcing the override bits Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -796,6 +796,8 @@ enum punit_power_well {
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#define _VLV_PCS_DW0_CH1 0x8400
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#define _VLV_PCS_DW0_CH1 0x8400
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#define DPIO_PCS_TX_LANE2_RESET (1<<16)
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#define DPIO_PCS_TX_LANE2_RESET (1<<16)
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#define DPIO_PCS_TX_LANE1_RESET (1<<7)
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#define DPIO_PCS_TX_LANE1_RESET (1<<7)
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#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
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#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
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#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
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#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
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#define _VLV_PCS01_DW0_CH0 0x200
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#define _VLV_PCS01_DW0_CH0 0x200
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@ -872,8 +874,18 @@ enum punit_power_well {
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#define _VLV_PCS_DW11_CH0 0x822c
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#define _VLV_PCS_DW11_CH0 0x822c
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#define _VLV_PCS_DW11_CH1 0x842c
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#define _VLV_PCS_DW11_CH1 0x842c
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#define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
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#define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
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#define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
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#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
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#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
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#define _VLV_PCS01_DW11_CH0 0x022c
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#define _VLV_PCS23_DW11_CH0 0x042c
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#define _VLV_PCS01_DW11_CH1 0x262c
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#define _VLV_PCS23_DW11_CH1 0x282c
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#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
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#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
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#define _VLV_PCS_DW12_CH0 0x8230
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#define _VLV_PCS_DW12_CH0 0x8230
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#define _VLV_PCS_DW12_CH1 0x8430
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#define _VLV_PCS_DW12_CH1 0x8430
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#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
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#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
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@ -2731,6 +2731,15 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->dpio_lock);
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/* allow hardware to manage TX FIFO reset source */
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
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val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
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vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
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val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
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vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
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/* Deassert soft data lane reset*/
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/* Deassert soft data lane reset*/
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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@ -1400,6 +1400,15 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
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mutex_lock(&dev_priv->dpio_lock);
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mutex_lock(&dev_priv->dpio_lock);
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/* allow hardware to manage TX FIFO reset source */
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
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val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
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vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
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val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
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vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
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/* Deassert soft data lane reset*/
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/* Deassert soft data lane reset*/
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
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val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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val |= CHV_PCS_REQ_SOFTRESET_EN;
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