mirror of https://gitee.com/openkylin/linux.git
drm/i915: Rename plane_config to initial_plane_config
This vfunc and related structure are only used for fast boot, so let's rename them to not take them as general purpose ones. v2: Fix conflicts caused by the introduction of struct intel_crtc_state Reviewed-By: Tvrtko Ursulin <tvrtko.ursulin@intel.com> (v1) Suggested-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -504,7 +504,7 @@ struct drm_i915_error_state {
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struct intel_connector;
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struct intel_connector;
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struct intel_encoder;
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struct intel_encoder;
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struct intel_crtc_state;
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struct intel_crtc_state;
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struct intel_plane_config;
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struct intel_initial_plane_config;
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struct intel_crtc;
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struct intel_crtc;
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struct intel_limit;
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struct intel_limit;
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struct dpll;
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struct dpll;
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@ -543,8 +543,8 @@ struct drm_i915_display_funcs {
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* fills out the pipe-config with the hw state. */
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* fills out the pipe-config with the hw state. */
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bool (*get_pipe_config)(struct intel_crtc *,
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bool (*get_pipe_config)(struct intel_crtc *,
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struct intel_crtc_state *);
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struct intel_crtc_state *);
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void (*get_plane_config)(struct intel_crtc *,
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void (*get_initial_plane_config)(struct intel_crtc *,
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struct intel_plane_config *);
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struct intel_initial_plane_config *);
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int (*crtc_compute_clock)(struct intel_crtc *crtc,
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int (*crtc_compute_clock)(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state);
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struct intel_crtc_state *crtc_state);
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void (*crtc_enable)(struct drm_crtc *crtc);
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void (*crtc_enable)(struct drm_crtc *crtc);
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@ -2363,8 +2363,9 @@ static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
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}
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}
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}
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}
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static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
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static bool
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struct intel_plane_config *plane_config)
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intel_alloc_plane_obj(struct intel_crtc *crtc,
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struct intel_initial_plane_config *plane_config)
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{
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_gem_object *obj = NULL;
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struct drm_i915_gem_object *obj = NULL;
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@ -2408,8 +2409,9 @@ static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
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return false;
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return false;
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}
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}
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static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
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static void
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struct intel_plane_config *plane_config)
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intel_find_plane_obj(struct intel_crtc *intel_crtc,
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struct intel_initial_plane_config *plane_config)
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{
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -6571,8 +6573,9 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
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pipe_config->port_clock = clock.dot / 5;
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pipe_config->port_clock = clock.dot / 5;
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}
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}
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static void i9xx_get_plane_config(struct intel_crtc *crtc,
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static void
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struct intel_plane_config *plane_config)
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i9xx_get_initial_plane_config(struct intel_crtc *crtc,
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struct intel_initial_plane_config *plane_config)
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{
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -7599,8 +7602,9 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc,
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}
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}
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}
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}
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static void skylake_get_plane_config(struct intel_crtc *crtc,
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static void
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struct intel_plane_config *plane_config)
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skylake_get_initial_plane_config(struct intel_crtc *crtc,
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struct intel_initial_plane_config *plane_config)
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{
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -7691,8 +7695,9 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
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}
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}
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}
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}
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static void ironlake_get_plane_config(struct intel_crtc *crtc,
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static void
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struct intel_plane_config *plane_config)
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ironlake_get_initial_plane_config(struct intel_crtc *crtc,
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struct intel_initial_plane_config *plane_config)
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{
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -12764,7 +12769,8 @@ static void intel_init_display(struct drm_device *dev)
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if (INTEL_INFO(dev)->gen >= 9) {
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if (INTEL_INFO(dev)->gen >= 9) {
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dev_priv->display.get_pipe_config = haswell_get_pipe_config;
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dev_priv->display.get_pipe_config = haswell_get_pipe_config;
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dev_priv->display.get_plane_config = skylake_get_plane_config;
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dev_priv->display.get_initial_plane_config =
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skylake_get_initial_plane_config;
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dev_priv->display.crtc_compute_clock =
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dev_priv->display.crtc_compute_clock =
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haswell_crtc_compute_clock;
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haswell_crtc_compute_clock;
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dev_priv->display.crtc_enable = haswell_crtc_enable;
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dev_priv->display.crtc_enable = haswell_crtc_enable;
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@ -12774,7 +12780,8 @@ static void intel_init_display(struct drm_device *dev)
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skylake_update_primary_plane;
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skylake_update_primary_plane;
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} else if (HAS_DDI(dev)) {
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} else if (HAS_DDI(dev)) {
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dev_priv->display.get_pipe_config = haswell_get_pipe_config;
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dev_priv->display.get_pipe_config = haswell_get_pipe_config;
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dev_priv->display.get_plane_config = ironlake_get_plane_config;
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dev_priv->display.get_initial_plane_config =
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ironlake_get_initial_plane_config;
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dev_priv->display.crtc_compute_clock =
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dev_priv->display.crtc_compute_clock =
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haswell_crtc_compute_clock;
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haswell_crtc_compute_clock;
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dev_priv->display.crtc_enable = haswell_crtc_enable;
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dev_priv->display.crtc_enable = haswell_crtc_enable;
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@ -12784,7 +12791,8 @@ static void intel_init_display(struct drm_device *dev)
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ironlake_update_primary_plane;
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ironlake_update_primary_plane;
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} else if (HAS_PCH_SPLIT(dev)) {
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} else if (HAS_PCH_SPLIT(dev)) {
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dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
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dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
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dev_priv->display.get_plane_config = ironlake_get_plane_config;
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dev_priv->display.get_initial_plane_config =
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ironlake_get_initial_plane_config;
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dev_priv->display.crtc_compute_clock =
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dev_priv->display.crtc_compute_clock =
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ironlake_crtc_compute_clock;
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ironlake_crtc_compute_clock;
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dev_priv->display.crtc_enable = ironlake_crtc_enable;
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dev_priv->display.crtc_enable = ironlake_crtc_enable;
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@ -12794,7 +12802,8 @@ static void intel_init_display(struct drm_device *dev)
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ironlake_update_primary_plane;
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ironlake_update_primary_plane;
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} else if (IS_VALLEYVIEW(dev)) {
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} else if (IS_VALLEYVIEW(dev)) {
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_plane_config = i9xx_get_plane_config;
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dev_priv->display.get_initial_plane_config =
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i9xx_get_initial_plane_config;
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dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
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dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
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dev_priv->display.crtc_enable = valleyview_crtc_enable;
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dev_priv->display.crtc_enable = valleyview_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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@ -12803,7 +12812,8 @@ static void intel_init_display(struct drm_device *dev)
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i9xx_update_primary_plane;
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i9xx_update_primary_plane;
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} else {
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} else {
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_plane_config = i9xx_get_plane_config;
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dev_priv->display.get_initial_plane_config =
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i9xx_get_initial_plane_config;
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dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
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dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
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dev_priv->display.crtc_enable = i9xx_crtc_enable;
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dev_priv->display.crtc_enable = i9xx_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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@ -13175,8 +13185,8 @@ void intel_modeset_init(struct drm_device *dev)
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* can even allow for smooth boot transitions if the BIOS
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* can even allow for smooth boot transitions if the BIOS
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* fb is large enough for the active pipe configuration.
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* fb is large enough for the active pipe configuration.
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*/
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*/
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if (dev_priv->display.get_plane_config) {
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if (dev_priv->display.get_initial_plane_config) {
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dev_priv->display.get_plane_config(crtc,
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dev_priv->display.get_initial_plane_config(crtc,
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&crtc->plane_config);
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&crtc->plane_config);
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/*
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/*
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* If the fb is shared between multiple heads, we'll
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* If the fb is shared between multiple heads, we'll
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@ -257,7 +257,7 @@ struct intel_plane_state {
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bool hides_primary;
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bool hides_primary;
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};
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};
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struct intel_plane_config {
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struct intel_initial_plane_config {
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unsigned int tiling;
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unsigned int tiling;
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int size;
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int size;
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u32 base;
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u32 base;
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@ -468,7 +468,7 @@ struct intel_crtc {
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uint32_t cursor_size;
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uint32_t cursor_size;
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uint32_t cursor_base;
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uint32_t cursor_base;
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struct intel_plane_config plane_config;
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struct intel_initial_plane_config plane_config;
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struct intel_crtc_state *config;
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struct intel_crtc_state *config;
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struct intel_crtc_state *new_config;
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struct intel_crtc_state *new_config;
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bool new_enabled;
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bool new_enabled;
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@ -531,7 +531,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
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struct intel_framebuffer *fb = NULL;
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struct intel_framebuffer *fb = NULL;
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struct drm_crtc *crtc;
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struct drm_crtc *crtc;
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struct intel_crtc *intel_crtc;
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struct intel_crtc *intel_crtc;
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struct intel_plane_config *plane_config = NULL;
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struct intel_initial_plane_config *plane_config = NULL;
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unsigned int max_size = 0;
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unsigned int max_size = 0;
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if (!i915.fastboot)
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if (!i915.fastboot)
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