mirror of https://gitee.com/openkylin/linux.git
r8169: add a new chip for RTL8111G
Add a new chip for RTL8111G series. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
hayeswang
David S. Miller
parent
beb330a441
commit
57538c4a89
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@ -48,6 +48,7 @@
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#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
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#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
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#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
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#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
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#ifdef RTL8169_DEBUG
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#define assert(expr) \
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@ -140,6 +141,7 @@ enum mac_version {
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RTL_GIGA_MAC_VER_39,
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RTL_GIGA_MAC_VER_40,
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RTL_GIGA_MAC_VER_41,
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RTL_GIGA_MAC_VER_42,
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RTL_GIGA_MAC_NONE = 0xff,
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};
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@ -266,6 +268,9 @@ static const struct {
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JUMBO_9K, false),
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[RTL_GIGA_MAC_VER_41] =
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_R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
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[RTL_GIGA_MAC_VER_42] =
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_R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
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JUMBO_9K, false),
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};
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#undef _R
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@ -514,6 +519,7 @@ enum rtl_register_content {
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PMEnable = (1 << 0), /* Power Management Enable */
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/* Config2 register p. 25 */
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ClkReqEn = (1 << 7), /* Clock Request Enable */
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MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
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PCI_Clock_66MHz = 0x01,
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PCI_Clock_33MHz = 0x00,
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@ -534,6 +540,7 @@ enum rtl_register_content {
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Spi_en = (1 << 3),
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LanWake = (1 << 1), /* LanWake enable/disable */
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PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
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ASPM_en = (1 << 0), /* ASPM enable */
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/* TBICSR p.28 */
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TBIReset = 0x80000000,
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@ -816,6 +823,7 @@ MODULE_FIRMWARE(FIRMWARE_8402_1);
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MODULE_FIRMWARE(FIRMWARE_8411_1);
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MODULE_FIRMWARE(FIRMWARE_8106E_1);
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MODULE_FIRMWARE(FIRMWARE_8168G_2);
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MODULE_FIRMWARE(FIRMWARE_8168G_3);
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static void rtl_lock_work(struct rtl8169_private *tp)
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{
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@ -2036,6 +2044,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
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int mac_version;
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} mac_info[] = {
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/* 8168G family. */
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{ 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
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{ 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
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{ 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
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@ -3439,6 +3448,11 @@ static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
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rtl_writephy(tp, 0x1f, 0x0000);
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}
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static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
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{
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rtl_apply_firmware(tp);
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}
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static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
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{
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static const struct phy_reg phy_reg_init[] = {
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@ -3624,6 +3638,9 @@ static void rtl_hw_phy_config(struct net_device *dev)
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case RTL_GIGA_MAC_VER_40:
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rtl8168g_1_hw_phy_config(tp);
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break;
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case RTL_GIGA_MAC_VER_42:
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rtl8168g_2_hw_phy_config(tp);
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break;
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case RTL_GIGA_MAC_VER_41:
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default:
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@ -3832,6 +3849,7 @@ static void rtl_init_mdio_ops(struct rtl8169_private *tp)
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break;
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case RTL_GIGA_MAC_VER_40:
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_42:
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ops->write = r8168g_mdio_write;
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ops->read = r8168g_mdio_read;
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break;
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@ -3859,6 +3877,7 @@ static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_39:
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case RTL_GIGA_MAC_VER_40:
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_42:
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RTL_W32(RxConfig, RTL_R32(RxConfig) |
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AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
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break;
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@ -4121,6 +4140,7 @@ static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_38:
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case RTL_GIGA_MAC_VER_40:
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_42:
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ops->down = r8168_pll_power_down;
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ops->up = r8168_pll_power_up;
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break;
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@ -4165,6 +4185,7 @@ static void rtl_init_rxcfg(struct rtl8169_private *tp)
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break;
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case RTL_GIGA_MAC_VER_40:
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_42:
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RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
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break;
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default:
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@ -4323,6 +4344,7 @@ static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
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*/
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case RTL_GIGA_MAC_VER_40:
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_42:
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default:
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ops->disable = NULL;
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ops->enable = NULL;
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@ -4430,6 +4452,7 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
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tp->mac_version == RTL_GIGA_MAC_VER_37 ||
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tp->mac_version == RTL_GIGA_MAC_VER_40 ||
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tp->mac_version == RTL_GIGA_MAC_VER_41 ||
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tp->mac_version == RTL_GIGA_MAC_VER_42 ||
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tp->mac_version == RTL_GIGA_MAC_VER_38) {
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RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
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rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
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@ -5174,6 +5197,24 @@ static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
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rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
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}
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static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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static const struct ephy_info e_info_8168g_2[] = {
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{ 0x00, 0x0000, 0x0008 },
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{ 0x0c, 0x3df0, 0x0200 },
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{ 0x19, 0xffff, 0xfc00 },
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{ 0x1e, 0xffff, 0x20eb }
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};
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rtl_hw_start_8168g_1(tp);
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/* disable aspm and clock request before access ephy */
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RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
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RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
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rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
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}
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static void rtl_hw_start_8168(struct net_device *dev)
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{
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struct rtl8169_private *tp = netdev_priv(dev);
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@ -5279,6 +5320,9 @@ static void rtl_hw_start_8168(struct net_device *dev)
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case RTL_GIGA_MAC_VER_41:
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rtl_hw_start_8168g_1(tp);
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break;
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case RTL_GIGA_MAC_VER_42:
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rtl_hw_start_8168g_2(tp);
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break;
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default:
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printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
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@ -6766,6 +6810,7 @@ static void rtl_hw_initialize(struct rtl8169_private *tp)
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_40:
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_42:
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rtl_hw_init_8168g(tp);
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break;
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