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clk: qcom: clk-alpha-pll: Use common names for defines
The PLL run and standby modes are similar across the PLLs, thus rename them to common names and update the use of these. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200224045003.3783838-2-vkoul@kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -134,15 +134,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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#define PLL_HUAYRA_N_MASK 0xff
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#define PLL_HUAYRA_ALPHA_WIDTH 16
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#define FABIA_OPMODE_STANDBY 0x0
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#define FABIA_OPMODE_RUN 0x1
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#define FABIA_PLL_OUT_MASK 0x7
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#define FABIA_PLL_RATE_MARGIN 500
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#define TRION_PLL_STANDBY 0x0
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#define TRION_PLL_RUN 0x1
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#define TRION_PLL_OUT_MASK 0x7
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#define PLL_STANDBY 0x0
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#define PLL_RUN 0x1
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#define PLL_OUT_MASK 0x7
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#define PLL_RATE_MARGIN 500
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#define pll_alpha_width(p) \
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((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
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@ -766,7 +761,7 @@ static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
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if (ret)
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return 0;
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return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
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return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL));
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}
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static int clk_trion_pll_is_enabled(struct clk_hw *hw)
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@ -796,7 +791,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
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}
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/* Set operation mode to RUN */
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regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
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regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
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ret = wait_for_pll_enable_lock(pll);
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if (ret)
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@ -804,7 +799,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
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/* Enable the PLL outputs */
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ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
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TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
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PLL_OUT_MASK, PLL_OUT_MASK);
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if (ret)
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return ret;
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@ -837,12 +832,12 @@ static void clk_trion_pll_disable(struct clk_hw *hw)
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/* Disable the PLL outputs */
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ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
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TRION_PLL_OUT_MASK, 0);
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PLL_OUT_MASK, 0);
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if (ret)
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return;
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/* Place the PLL mode in STANDBY */
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regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
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regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
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regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
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}
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@ -1089,14 +1084,14 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
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return ret;
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/* Skip If PLL is already running */
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if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
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if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
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return 0;
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ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
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if (ret)
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return ret;
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ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
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ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
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if (ret)
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return ret;
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@ -1105,7 +1100,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
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if (ret)
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return ret;
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ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
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ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
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if (ret)
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return ret;
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@ -1114,7 +1109,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
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return ret;
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ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
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FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
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PLL_OUT_MASK, PLL_OUT_MASK);
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if (ret)
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return ret;
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@ -1144,13 +1139,12 @@ static void alpha_pll_fabia_disable(struct clk_hw *hw)
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return;
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/* Disable main outputs */
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ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
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0);
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ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
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if (ret)
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return;
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/* Place the PLL in STANDBY */
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regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
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regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
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}
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static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
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@ -1171,7 +1165,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 l, alpha_width = pll_alpha_width(pll);
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u64 a;
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unsigned long rrate, max = rate + FABIA_PLL_RATE_MARGIN;
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unsigned long rrate, max = rate + PLL_RATE_MARGIN;
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rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
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@ -1230,7 +1224,7 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw)
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* Due to a limited number of bits for fractional rate programming, the
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* rounded up rate could be marginally higher than the requested rate.
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*/
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if (rrate > (cal_freq + FABIA_PLL_RATE_MARGIN) || rrate < cal_freq)
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if (rrate > (cal_freq + PLL_RATE_MARGIN) || rrate < cal_freq)
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return -EINVAL;
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/* Setup PLL for calibration frequency */
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