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ASoC: fsl_esai: Only bypass sck_div for EXTAL source 

ESAI can only output EXTAL clock source directly. But for FSYS clock source,
ESAI can not output it without getting through PSR PM dividers.

So this patch adds an extra check in the code.

Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Nicolin Chen 2014-05-06 16:56:00 +08:00 committed by Mark Brown
parent 89e47f62cf
commit 57ebbcafab
1 changed files with 7 additions and 1 deletions
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8
sound/soc/fsl/fsl_esai.c
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@ -258,10 +258,16 @@ static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
return -EINVAL;
}
if (ratio == 1) {
/* Only EXTAL source can be output directly without using PSR and PM */
if (ratio == 1 && clksrc == esai_priv->extalclk) {
/* Bypass all the dividers if not being needed */
ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
goto out;
} else if (ratio < 2) {
/* The ratio should be no less than 2 if using other sources */
dev_err(dai->dev, "failed to derive required HCK%c rate\n",
tx ? 'T' : 'R');
return -EINVAL;
}
ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);