mirror of https://gitee.com/openkylin/linux.git
ARM: dts: r8a7791: Stop grouping clocks under a "clocks" subnode
The current practice is to not group clocks under a "clocks" subnode, but just put them together with the other on-SoC devices. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -1097,77 +1097,72 @@ jpu: jpeg-codec@fe980000 {
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power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
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power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
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};
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};
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clocks {
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/* External root clock */
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#address-cells = <2>;
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extal_clk: extal {
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#size-cells = <2>;
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compatible = "fixed-clock";
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ranges;
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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/* External root clock */
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/*
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extal_clk: extal {
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* The external audio clocks are configured as 0 Hz fixed frequency
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compatible = "fixed-clock";
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* clocks by default.
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#clock-cells = <0>;
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* Boards that provide audio clocks should override them.
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/* This value must be overriden by the board. */
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*/
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clock-frequency = <0>;
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audio_clk_a: audio_clk_a {
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};
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_b: audio_clk_b {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_c: audio_clk_c {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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/*
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/* External PCIe clock - can be overridden by the board */
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* The external audio clocks are configured as 0 Hz fixed frequency clocks by
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pcie_bus_clk: pcie_bus {
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* default. Boards that provide audio clocks should override them.
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compatible = "fixed-clock";
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*/
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#clock-cells = <0>;
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audio_clk_a: audio_clk_a {
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clock-frequency = <0>;
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compatible = "fixed-clock";
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};
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_b: audio_clk_b {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_c: audio_clk_c {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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/* External PCIe clock - can be overridden by the board */
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/* External SCIF clock */
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pcie_bus_clk: pcie_bus {
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scif_clk: scif {
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compatible = "fixed-clock";
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compatible = "fixed-clock";
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#clock-cells = <0>;
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#clock-cells = <0>;
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clock-frequency = <0>;
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/* This value must be overridden by the board. */
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};
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clock-frequency = <0>;
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};
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/* External SCIF clock */
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/* External USB clock - can be overridden by the board */
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scif_clk: scif {
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usb_extal_clk: usb_extal {
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compatible = "fixed-clock";
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compatible = "fixed-clock";
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#clock-cells = <0>;
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <48000000>;
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clock-frequency = <0>;
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};
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};
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/* External USB clock - can be overridden by the board */
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/* External CAN clock */
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usb_extal_clk: usb_extal {
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can_clk: can {
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compatible = "fixed-clock";
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compatible = "fixed-clock";
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#clock-cells = <0>;
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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/* This value must be overridden by the board. */
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};
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clock-frequency = <0>;
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};
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/* External CAN clock */
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cpg: clock-controller@e6150000 {
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can_clk: can {
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compatible = "renesas,r8a7791-cpg-mssr";
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compatible = "fixed-clock";
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reg = <0 0xe6150000 0 0x1000>;
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#clock-cells = <0>;
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clocks = <&extal_clk>, <&usb_extal_clk>;
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/* This value must be overridden by the board. */
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clock-names = "extal", "usb_extal";
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clock-frequency = <0>;
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#clock-cells = <2>;
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};
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#power-domain-cells = <0>;
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7791-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&usb_extal_clk>;
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clock-names = "extal", "usb_extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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};
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};
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};
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rst: reset-controller@e6160000 {
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rst: reset-controller@e6160000 {
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