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This is the bulk of pin control patches for the v4.5 

series:
 
 - New drivers:
   - PXA2xx pin controller support
   - Broadcom NSP pin controller support
 
 - New subdrivers:
   - Samsung EXYNOS5410 support
   - Qualcomm MSM8996 support
   - Qualcomm PM8994 support
   - Qualcomm PM8994 MPP support
   - Allwinner sunxi H3 support
   - Allwinner sunxi A80 support
   - Rockchip RK3228 support
 
 - Rename the Cygnus pinctrl driver to "iproc" as it is more
   generic than was originally thought.
 
 - A bunch of Lantiq/Xway updates especially from the OpenWRT
   people.
 
 - Several refactorings for the Super-H SH PFC pin controllers.
   Adding SCIF_CLK support.
 
 - Several fixes to the Atlas 7 driver.
 
 - Various fixes all over the place.
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Merge tag 'pinctrl-v4.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control patches for the v4.5 series.

  Notably I have a patch to driver core from Stephen Boyd in the pull
  request, this has been ACKed by Greg so it should be OK.  The internal
  API needed some tweaking to allow modular Qualcomm pin controllers.

  There is a bit of development history in here but it should all add up
  nicely and has boiled in linux-next.  For example I merged in v4.4-rc5
  to get rid of some nasty merge conflicts.

  Summary:

   - New drivers:
      - PXA2xx pin controller support
      - Broadcom NSP pin controller support

   - New subdrivers:
      - Samsung EXYNOS5410 support
      - Qualcomm MSM8996 support
      - Qualcomm PM8994 support
      - Qualcomm PM8994 MPP support
      - Allwinner sunxi H3 support
      - Allwinner sunxi A80 support
      - Rockchip RK3228 support

   - Rename the Cygnus pinctrl driver to "iproc" as it is more generic
     than was originally thought.

   - A bunch of Lantiq/Xway updates especially from the OpenWRT people.

   - Several refactorings for the Super-H SH PFC pin controllers.
     Adding SCIF_CLK support.

   - Several fixes to the Atlas 7 driver.

   - Various fixes all over the place"

* tag 'pinctrl-v4.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (91 commits)
  pinctrl: mediatek: Modify pinctrl bindings for mt2701
  Revert "pinctrl: qcom: make PMIC drivers bool"
  pinctrl: qcom: Use platform_irq_count() instead of of_irq_count()
  driver-core: platform: Add platform_irq_count()
  pinctrl: lantiq: 2 pins have the wrong mux list
  pinctrl: qcom: make PMIC drivers bool
  pinctrl: nsp-gpio: forever loop in nsp_gpio_get_strength()
  pinctrl: mediatek: convert to arch_initcall
  pinctrl: bcm2835: Fix memory leak in error path
  pinctrl: mediatek: add missing of_node_put
  pinctrl: rockchip: add missing of_node_put
  pinctrl: sh-pfc: add missing of_node_put
  pinctrl: sirf: add missing of_node_put
  pinctrl-tegra: add missing of_node_put
  pinctrl: sunxi: Add A80 special pin controller
  pinctrl: bcm/cygnys/iproc: fixup rebase issue
  pinctrl: fixup problematic flag
  MAINTAINERS: Add co-maintainer for Renesas Pin Controllers
  pinctrl: sh-pfc: r8a7791: add EtherAVB pin groups
  pinctrl: sh-pfc: r8a7795: Add SATA support
  ...
This commit is contained in:
Linus Torvalds 2016-01-11 20:05:39 -08:00
parent fb591fbd0a 14da0a91bf
commit 581dbc8bfc
73 changed files with 9053 additions and 767 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
View File

@ -17,7 +17,10 @@ Required properties:
"allwinner,sun8i-a23-pinctrl"
"allwinner,sun8i-a23-r-pinctrl"
"allwinner,sun8i-a33-pinctrl"
"allwinner,sun9i-a80-pinctrl"
"allwinner,sun9i-a80-r-pinctrl"
"allwinner,sun8i-a83t-pinctrl"
"allwinner,sun8i-h3-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.

9
Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt → Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt
View File

@ -1,4 +1,4 @@
Broadcom Cygnus GPIO/PINCONF Controller
Broadcom iProc GPIO/PINCONF Controller
Required properties:
@ -7,9 +7,12 @@ Required properties:
"brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio"
- reg:
Define the base and range of the I/O address space that contains the Cygnus
Define the base and range of the I/O address space that contains SoC
GPIO/PINCONF controller registers
- ngpios:
Total number of in-use slots in GPIO controller
- #gpio-cells:
Must be two. The first cell is the GPIO pin number (within the
controller's pin space) and the second cell is used for the following:
@ -57,6 +60,7 @@ Example:
compatible = "brcm,cygnus-ccm-gpio";
reg = <0x1800a000 0x50>,
<0x0301d164 0x20>;
ngpios = <24>;
#gpio-cells = <2>;
gpio-controller;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
@ -78,6 +82,7 @@ Example:
gpio_asiu: gpio@180a5000 {
compatible = "brcm,cygnus-asiu-gpio";
reg = <0x180a5000 0x668>;
ngpios = <146>;
#gpio-cells = <2>;
gpio-controller;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

80
Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt Normal file
View File

@ -0,0 +1,80 @@
Broadcom Northstar plus (NSP) GPIO/PINCONF Controller
Required properties:
- compatible:
Must be "brcm,nsp-gpio-a"
- reg:
Should contain the register physical address and length for each of
GPIO base, IO control registers
- #gpio-cells:
Must be two. The first cell is the GPIO pin number (within the
controller's pin space) and the second cell is used for the following:
bit[0]: polarity (0 for active high and 1 for active low)
- gpio-controller:
Specifies that the node is a GPIO controller
- ngpios:
Number of gpios supported (58x25 supports 32 and 58x23 supports 24)
Optional properties:
- interrupts:
Interrupt ID
- interrupt-controller:
Specifies that the node is an interrupt controller
- gpio-ranges:
Specifies the mapping between gpio controller and pin-controllers pins.
This requires 4 fields in cells defined as -
1. Phandle of pin-controller.
2. GPIO base pin offset.
3 Pin-control base pin offset.
4. number of gpio pins which are linearly mapped from pin base.
Supported generic PINCONF properties in child nodes:
- pins:
The list of pins (within the controller's own pin space) that properties
in the node apply to. Pin names are "gpio-<pin>"
- bias-disable:
Disable pin bias
- bias-pull-up:
Enable internal pull up resistor
- bias-pull-down:
Enable internal pull down resistor
- drive-strength:
Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA)
Example:
gpioa: gpio@18000020 {
compatible = "brcm,nsp-gpio-a";
reg = <0x18000020 0x100>,
<0x1803f1c4 0x1c>;
#gpio-cells = <2>;
gpio-controller;
ngpios = <32>;
gpio-ranges = <&pinctrl 0 0 31>;
interrupt-controller;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
/* Hog a few default settings */
pinctrl-names = "default";
pinctrl-0 = <&led>;
led: led {
pins = "gpio-1";
bias-pull-up;
};
pwr: pwr {
gpio-hog;
gpios = <3 1>;
output-high;
};
};

110
Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt
View File

@ -1,7 +1,16 @@
Lantiq XWAY pinmux controller
Required properties:
- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9"
- compatible: "lantiq,pinctrl-xway", (DEPRECATED: Use "lantiq,pinctrl-danube")
"lantiq,pinctrl-xr9", (DEPRECATED: Use "lantiq,xrx100-pinctrl" or
"lantiq,xrx200-pinctrl")
"lantiq,pinctrl-ase", (DEPRECATED: Use "lantiq,ase-pinctrl")
"lantiq,<chip>-pinctrl", where <chip> is:
"ase" (XWAY AMAZON Family)
"danube" (XWAY DANUBE Family)
"xrx100" (XWAY xRX100 Family)
"xrx200" (XWAY xRX200 Family)
"xrx300" (XWAY xRX300 Family)
- reg: Should contain the physical address and length of the gpio/pinmux
register range
@ -36,19 +45,87 @@ Required subnode-properties:
Valid values for group and function names:
XWAY: (DEPRECATED: Use DANUBE)
mux groups:
exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2,
spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2,
gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,
req3
additional mux groups (XR9 only):
mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4
functions:
spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu
XR9: ( DEPRECATED: Use xRX100/xRX200)
mux groups:
exin0, exin1, exin2, exin3, exin4, jtag, ebu a23, ebu a24, ebu a25,
ebu clk, ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy,
nand rd, spi, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6,
asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio,
gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2
functions:
spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio
spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio, gphy
AMAZON:
mux groups:
exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2,
spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0,
clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2
functions:
spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
DANUBE:
mux groups:
exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi,
gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3,
req1, req2, req3, dfe led0, dfe led1
functions:
spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
xRX100:
mux groups:
exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio,
dfe led0, dfe led1
functions:
spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
xRX200:
mux groups:
exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
spi_cs6, usif uart_rx, usif uart_tx, usif uart_rts, usif uart_cts,
usif uart_dtr, usif uart_dsr, usif uart_dcd, usif uart_ri, usif spi_di,
usif spi_do, usif spi_clk, usif spi_cs0, usif spi_cs1, usif spi_cs2,
stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1,
gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, dfe led0, dfe led1,
gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2
functions:
spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
xRX300:
mux groups:
exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
spi_clk, spi_cs1, spi_cs4, spi_cs6, usif uart_rx, usif uart_tx,
usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2,
mdio, dfe led0, dfe led1, ephy0 led0, ephy0 led1, ephy1 led0, ephy1 led1
functions:
spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy
Definition of pin configurations:
@ -62,15 +139,32 @@ Optional subnode-properties:
0: none, 1: down, 2: up.
- lantiq,open-drain: Boolean, enables open-drain on the defined pin.
Valid values for XWAY pin names:
Valid values for XWAY pin names: (DEPRECATED: Use DANUBE)
Pinconf pins can be referenced via the names io0-io31.
Valid values for XR9 pin names:
Valid values for XR9 pin names: (DEPRECATED: Use xrX100/xRX200)
Pinconf pins can be referenced via the names io0-io55.
Valid values for AMAZON pin names:
Pinconf pins can be referenced via the names io0-io31.
Valid values for DANUBE pin names:
Pinconf pins can be referenced via the names io0-io31.
Valid values for xRX100 pin names:
Pinconf pins can be referenced via the names io0-io55.
Valid values for xRX200 pin names:
Pinconf pins can be referenced via the names io0-io49.
Valid values for xRX300 pin names:
Pinconf pins can be referenced via the names io0-io1,io3-io6,io8-io11,
io13-io19,io23-io27,io34-io36,
io42-io43,io48-io61.
Example:
gpio: pinmux@E100B10 {
compatible = "lantiq,pinctrl-xway";
compatible = "lantiq,danube-pinctrl";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;

9
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
View File

@ -4,10 +4,11 @@ The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
(a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
(b) "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
(c) "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
(d) "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
- gpio-controller : Marks the device node as a gpio controller.

199
Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt Normal file
View File

@ -0,0 +1,199 @@
Qualcomm MSM8996 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MSM8996 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,msm8996-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins are:
gpio0-gpio149
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
sdc2_data sdc1_rclk
Supports bias and drive-strength
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
atest_usb20, atest_char0, dac_calib10, qdss_stm10,
qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
gpio
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@01010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x01010000 0x300000>;
interrupts = <0 208 0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
uart_console_active: uart_console_active {
mux {
pins = "gpio4", "gpio5";
function = "blsp_uart8";
};
config {
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-disable;
};
};
};

2
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
View File

@ -14,6 +14,7 @@ PMIC's from Qualcomm.
"qcom,pm8917-gpio"
"qcom,pm8921-gpio"
"qcom,pm8941-gpio"
"qcom,pm8994-gpio"
"qcom,pma8084-gpio"
- reg:
@ -79,6 +80,7 @@ to specify in a pin configuration subnode:
gpio1-gpio38 for pm8917
gpio1-gpio44 for pm8921
gpio1-gpio36 for pm8941
gpio1-gpio22 for pm8994
gpio1-gpio22 for pma8084
- function:

1
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
View File

@ -15,6 +15,7 @@ of PMIC's from Qualcomm.
"qcom,pm8917-mpp",
"qcom,pm8921-mpp",
"qcom,pm8941-mpp",
"qcom,pm8994-mpp",
"qcom,pma8084-mpp",
- reg:

3
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
View File

@ -21,7 +21,8 @@ defined as gpio sub-nodes of the pinmux controller.
Required properties for iomux controller:
- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
"rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl"
"rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl"
"rockchip,rk3368-pinctrl"
- rockchip,grf: phandle referencing a syscon providing the
"general register files"

1
Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
View File

@ -17,6 +17,7 @@ Required Properties:
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.

2
MAINTAINERS
View File

@ -8366,6 +8366,7 @@ F: drivers/pinctrl/intel/
PIN CONTROLLER - RENESAS
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
M: Geert Uytterhoeven <geert+renesas@glider.be>
L: linux-sh@vger.kernel.org
S: Maintained
F: drivers/pinctrl/sh-pfc/
@ -8636,6 +8637,7 @@ S: Maintained
F: arch/arm/mach-pxa/
F: drivers/dma/pxa*
F: drivers/pcmcia/pxa2xx*
F: drivers/pinctrl/pxa/
F: drivers/spi/spi-pxa2xx*
F: drivers/usb/gadget/udc/pxa2*
F: include/sound/pxa2xx-lib.h

20
drivers/base/platform.c
View File

@ -116,6 +116,26 @@ int platform_get_irq(struct platform_device *dev, unsigned int num)
}
EXPORT_SYMBOL_GPL(platform_get_irq);
/**
* platform_irq_count - Count the number of IRQs a platform device uses
* @dev: platform device
*
* Return: Number of IRQs a platform device uses or EPROBE_DEFER
*/
int platform_irq_count(struct platform_device *dev)
{
int ret, nr = 0;
while ((ret = platform_get_irq(dev, nr)) >= 0)
nr++;
if (ret == -EPROBE_DEFER)
return ret;
return nr;
}
EXPORT_SYMBOL_GPL(platform_irq_count);
/**
* platform_get_resource_byname - get a resource for a device by name
* @dev: platform device

3
drivers/pinctrl/Kconfig
View File

@ -244,7 +244,7 @@ config PINCTRL_ZYNQ
select PINMUX
select GENERIC_PINCONF
help
This selectes the pinctrl driver for Xilinx Zynq.
This selects the pinctrl driver for Xilinx Zynq.
source "drivers/pinctrl/bcm/Kconfig"
source "drivers/pinctrl/berlin/Kconfig"
@ -252,6 +252,7 @@ source "drivers/pinctrl/freescale/Kconfig"
source "drivers/pinctrl/intel/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/nomadik/Kconfig"
source "drivers/pinctrl/pxa/Kconfig"
source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/sh-pfc/Kconfig"

7
drivers/pinctrl/Makefile
View File

@ -41,15 +41,16 @@ obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
obj-$(CONFIG_ARCH_BCM) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
obj-$(CONFIG_PINCTRL_BERLIN) += berlin/
obj-y += freescale/
obj-$(CONFIG_X86) += intel/
obj-$(CONFIG_PLAT_ORION) += mvebu/
obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/
obj-y += nomadik/
obj-$(CONFIG_ARCH_PXA) += pxa/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_ARCH_VT8500) += vt8500/

48
drivers/pinctrl/bcm/Kconfig
View File

@ -9,6 +9,7 @@ config PINCTRL_BCM281XX
select PINCONF
select GENERIC_PINCONF
select REGMAP_MMIO
default ARCH_BCM_MOBILE
help
Say Y here to support Broadcom BCM281xx pinctrl driver, which is used
for the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351,
@ -20,27 +21,41 @@ config PINCTRL_BCM2835
select PINMUX
select PINCONF
config PINCTRL_CYGNUS_GPIO
bool "Broadcom Cygnus GPIO (with PINCONF) driver"
depends on OF_GPIO && ARCH_BCM_CYGNUS
config PINCTRL_IPROC_GPIO
bool "Broadcom iProc GPIO (with PINCONF) driver"
depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
select GPIOLIB_IRQCHIP
select PINCONF
select GENERIC_PINCONF
default ARCH_BCM_CYGNUS
default ARCH_BCM_IPROC
help
Say yes here to enable the Broadcom Cygnus GPIO driver.
Say yes here to enable the Broadcom iProc GPIO driver.
The Broadcom iProc based SoCs- Cygnus, NS2, NSP and Stingray, use
same GPIO Controller IP hence this driver could be used for all.
The Broadcom Cygnus SoC has 3 GPIO controllers including the ASIU
GPIO controller (ASIU), the chipCommonG GPIO controller (CCM), and
the always-ON GPIO controller (CRMU/AON). All 3 GPIO controllers are
supported by this driver.
All 3 Cygnus GPIO controllers support basic PINCONF functions such
The Broadcom NSP has two GPIO controllers including the ChipcommonA
GPIO, the ChipcommonB GPIO. Later controller is supported by this
driver.
The Broadcom NS2 has two GPIO controller including the CRMU GPIO,
the ChipcommonG GPIO. Both controllers are supported by this driver.
The Broadcom Stingray GPIO controllers are supported by this driver.
All above SoCs GPIO controllers support basic PINCONF functions such
as bias pull up, pull down, and drive strength configurations, when
these pins are muxed to GPIO.
Pins from the ASIU GPIO can be individually muxed to GPIO function,
through interaction with the Cygnus IOMUX controller.
It provides the framework where pins from the individual GPIO can be
individually muxed to GPIO function, through interaction with the
SoCs IOMUX controller. This features could be used only on SoCs which
support individual pin muxing.
config PINCTRL_CYGNUS_MUX
bool "Broadcom Cygnus IOMUX driver"
@ -54,3 +69,20 @@ config PINCTRL_CYGNUS_MUX
The Broadcom Cygnus IOMUX driver supports group based IOMUX
configuration, with the exception that certain individual pins
can be overrided to GPIO function
config PINCTRL_NSP_GPIO
bool "Broadcom NSP GPIO (with PINCONF) driver"
depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST)
select GPIOLIB_IRQCHIP
select PINCONF
select GENERIC_PINCONF
default ARCH_BCM_NSP
help
Say yes here to enable the Broadcom NSP GPIO driver.
The Broadcom Northstar Plus SoC ChipcommonA GPIO controller is
supported by this driver.
The ChipcommonA GPIO controller support basic PINCONF functions such
as bias pull up, pull down, and drive strength configurations, when
these pins are muxed to GPIO.

3
drivers/pinctrl/bcm/Makefile
View File

@ -2,5 +2,6 @@
obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_CYGNUS_GPIO) += pinctrl-cygnus-gpio.o
obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o
obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
obj-$(CONFIG_PINCTRL_NSP_GPIO) += pinctrl-nsp-gpio.o

2
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View File

@ -795,7 +795,7 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
return 0;
out:
kfree(maps);
bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
return err;
}

358
drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c → drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
View File

@ -10,14 +10,16 @@
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This file contains the Broadcom Cygnus GPIO driver that supports 3
* GPIO controllers on Cygnus including the ASIU GPIO controller, the
* This file contains the Broadcom Iproc GPIO driver that supports 3
* GPIO controllers on Iproc including the ASIU GPIO controller, the
* chipCommonG GPIO controller, and the always-on GPIO controller. Basic
* PINCONF such as bias pull up/down, and drive strength are also supported
* in this driver.
*
* Pins from the ASIU GPIO can be individually muxed to GPIO function,
* through the interaction with the Cygnus IOMUX controller
* It provides the functionality where pins from the GPIO can be
* individually muxed to GPIO function, if individual pad
* configuration is supported, through the interaction with respective
* SoCs IOMUX controller.
*/
#include <linux/kernel.h>
@ -34,42 +36,42 @@
#include "../pinctrl-utils.h"
#define CYGNUS_GPIO_DATA_IN_OFFSET 0x00
#define CYGNUS_GPIO_DATA_OUT_OFFSET 0x04
#define CYGNUS_GPIO_OUT_EN_OFFSET 0x08
#define CYGNUS_GPIO_INT_TYPE_OFFSET 0x0c
#define CYGNUS_GPIO_INT_DE_OFFSET 0x10
#define CYGNUS_GPIO_INT_EDGE_OFFSET 0x14
#define CYGNUS_GPIO_INT_MSK_OFFSET 0x18
#define CYGNUS_GPIO_INT_STAT_OFFSET 0x1c
#define CYGNUS_GPIO_INT_MSTAT_OFFSET 0x20
#define CYGNUS_GPIO_INT_CLR_OFFSET 0x24
#define CYGNUS_GPIO_PAD_RES_OFFSET 0x34
#define CYGNUS_GPIO_RES_EN_OFFSET 0x38
#define IPROC_GPIO_DATA_IN_OFFSET 0x00
#define IPROC_GPIO_DATA_OUT_OFFSET 0x04
#define IPROC_GPIO_OUT_EN_OFFSET 0x08
#define IPROC_GPIO_INT_TYPE_OFFSET 0x0c
#define IPROC_GPIO_INT_DE_OFFSET 0x10
#define IPROC_GPIO_INT_EDGE_OFFSET 0x14
#define IPROC_GPIO_INT_MSK_OFFSET 0x18
#define IPROC_GPIO_INT_STAT_OFFSET 0x1c
#define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
#define IPROC_GPIO_INT_CLR_OFFSET 0x24
#define IPROC_GPIO_PAD_RES_OFFSET 0x34
#define IPROC_GPIO_RES_EN_OFFSET 0x38
/* drive strength control for ASIU GPIO */
#define CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
#define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
/* drive strength control for CCM/CRMU (AON) GPIO */
#define CYGNUS_GPIO_DRV0_CTRL_OFFSET 0x00
#define IPROC_GPIO_DRV0_CTRL_OFFSET 0x00
#define GPIO_BANK_SIZE 0x200
#define NGPIOS_PER_BANK 32
#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
#define CYGNUS_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
#define CYGNUS_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
#define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
#define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
#define GPIO_DRV_STRENGTH_BIT_SHIFT 20
#define GPIO_DRV_STRENGTH_BITS 3
#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
/*
* Cygnus GPIO core
* Iproc GPIO core
*
* @dev: pointer to device
* @base: I/O register base for Cygnus GPIO controller
* @io_ctrl: I/O register base for certain type of Cygnus GPIO controller that
* @base: I/O register base for Iproc GPIO controller
* @io_ctrl: I/O register base for certain type of Iproc GPIO controller that
* has the PINCONF support implemented outside of the GPIO block
* @lock: lock to protect access to I/O registers
* @gc: GPIO chip
@ -79,7 +81,7 @@
* @pctl: pointer to pinctrl_dev
* @pctldesc: pinctrl descriptor
*/
struct cygnus_gpio {
struct iproc_gpio {
struct device *dev;
void __iomem *base;
@ -96,33 +98,33 @@ struct cygnus_gpio {
struct pinctrl_desc pctldesc;
};
static inline struct cygnus_gpio *to_cygnus_gpio(struct gpio_chip *gc)
static inline struct iproc_gpio *to_iproc_gpio(struct gpio_chip *gc)
{
return container_of(gc, struct cygnus_gpio, gc);
return container_of(gc, struct iproc_gpio, gc);
}
/*
* Mapping from PINCONF pins to GPIO pins is 1-to-1
*/
static inline unsigned cygnus_pin_to_gpio(unsigned pin)
static inline unsigned iproc_pin_to_gpio(unsigned pin)
{
return pin;
}
/**
* cygnus_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
* Cygnus GPIO register
* iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
* Iproc GPIO register
*
* @cygnus_gpio: Cygnus GPIO device
* @iproc_gpio: Iproc GPIO device
* @reg: register offset
* @gpio: GPIO pin
* @set: set or clear
*/
static inline void cygnus_set_bit(struct cygnus_gpio *chip, unsigned int reg,
static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
unsigned gpio, bool set)
{
unsigned int offset = CYGNUS_GPIO_REG(gpio, reg);
unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
unsigned int offset = IPROC_GPIO_REG(gpio, reg);
unsigned int shift = IPROC_GPIO_SHIFT(gpio);
u32 val;
val = readl(chip->base + offset);
@ -133,19 +135,19 @@ static inline void cygnus_set_bit(struct cygnus_gpio *chip, unsigned int reg,
writel(val, chip->base + offset);
}
static inline bool cygnus_get_bit(struct cygnus_gpio *chip, unsigned int reg,
static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
unsigned gpio)
{
unsigned int offset = CYGNUS_GPIO_REG(gpio, reg);
unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
unsigned int offset = IPROC_GPIO_REG(gpio, reg);
unsigned int shift = IPROC_GPIO_SHIFT(gpio);
return !!(readl(chip->base + offset) & BIT(shift));
}
static void cygnus_gpio_irq_handler(struct irq_desc *desc)
static void iproc_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
struct iproc_gpio *chip = to_iproc_gpio(gc);
struct irq_chip *irq_chip = irq_desc_get_chip(desc);
int i, bit;
@ -154,7 +156,7 @@ static void cygnus_gpio_irq_handler(struct irq_desc *desc)
/* go through the entire GPIO banks and handle all interrupts */
for (i = 0; i < chip->num_banks; i++) {
unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
CYGNUS_GPIO_INT_MSTAT_OFFSET);
IPROC_GPIO_INT_MSTAT_OFFSET);
for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
unsigned pin = NGPIOS_PER_BANK * i + bit;
@ -165,7 +167,7 @@ static void cygnus_gpio_irq_handler(struct irq_desc *desc)
* handler, so we do not leave any window
*/
writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
CYGNUS_GPIO_INT_CLR_OFFSET);
IPROC_GPIO_INT_CLR_OFFSET);
generic_handle_irq(child_irq);
}
@ -175,60 +177,60 @@ static void cygnus_gpio_irq_handler(struct irq_desc *desc)
}
static void cygnus_gpio_irq_ack(struct irq_data *d)
static void iproc_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
struct iproc_gpio *chip = to_iproc_gpio(gc);
unsigned gpio = d->hwirq;
unsigned int offset = CYGNUS_GPIO_REG(gpio,
CYGNUS_GPIO_INT_CLR_OFFSET);
unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
unsigned int offset = IPROC_GPIO_REG(gpio,
IPROC_GPIO_INT_CLR_OFFSET);
unsigned int shift = IPROC_GPIO_SHIFT(gpio);
u32 val = BIT(shift);
writel(val, chip->base + offset);
}
/**
* cygnus_gpio_irq_set_mask - mask/unmask a GPIO interrupt
* iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
*
* @d: IRQ chip data
* @unmask: mask/unmask GPIO interrupt
*/
static void cygnus_gpio_irq_set_mask(struct irq_data *d, bool unmask)
static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
struct iproc_gpio *chip = to_iproc_gpio(gc);
unsigned gpio = d->hwirq;
cygnus_set_bit(chip, CYGNUS_GPIO_INT_MSK_OFFSET, gpio, unmask);
iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
}
static void cygnus_gpio_irq_mask(struct irq_data *d)
static void iproc_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
struct iproc_gpio *chip = to_iproc_gpio(gc);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
cygnus_gpio_irq_set_mask(d, false);
iproc_gpio_irq_set_mask(d, false);
spin_unlock_irqrestore(&chip->lock, flags);
}
static void cygnus_gpio_irq_unmask(struct irq_data *d)
static void iproc_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
struct iproc_gpio *chip = to_iproc_gpio(gc);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
cygnus_gpio_irq_set_mask(d, true);
iproc_gpio_irq_set_mask(d, true);
spin_unlock_irqrestore(&chip->lock, flags);
}
static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type)
static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
struct iproc_gpio *chip = to_iproc_gpio(gc);
unsigned gpio = d->hwirq;
bool level_triggered = false;
bool dual_edge = false;
@ -263,10 +265,10 @@ static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type)
}
spin_lock_irqsave(&chip->lock, flags);
cygnus_set_bit(chip, CYGNUS_GPIO_INT_TYPE_OFFSET, gpio,
iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
level_triggered);
cygnus_set_bit(chip, CYGNUS_GPIO_INT_DE_OFFSET, gpio, dual_edge);
cygnus_set_bit(chip, CYGNUS_GPIO_INT_EDGE_OFFSET, gpio,
iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
rising_or_high);
spin_unlock_irqrestore(&chip->lock, flags);
@ -277,32 +279,32 @@ static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type)
return 0;
}
static struct irq_chip cygnus_gpio_irq_chip = {
.name = "bcm-cygnus-gpio",
.irq_ack = cygnus_gpio_irq_ack,
.irq_mask = cygnus_gpio_irq_mask,
.irq_unmask = cygnus_gpio_irq_unmask,
.irq_set_type = cygnus_gpio_irq_set_type,
static struct irq_chip iproc_gpio_irq_chip = {
.name = "bcm-iproc-gpio",
.irq_ack = iproc_gpio_irq_ack,
.irq_mask = iproc_gpio_irq_mask,
.irq_unmask = iproc_gpio_irq_unmask,
.irq_set_type = iproc_gpio_irq_set_type,
};
/*
* Request the Cygnus IOMUX pinmux controller to mux individual pins to GPIO
* Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
*/
static int cygnus_gpio_request(struct gpio_chip *gc, unsigned offset)
static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
{
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
struct iproc_gpio *chip = to_iproc_gpio(gc);
unsigned gpio = gc->base + offset;
/* not all Cygnus GPIO pins can be muxed individually */
/* not all Iproc GPIO pins can be muxed individually */
if (!chip->pinmux_is_supported)
return 0;
return pinctrl_request_gpio(gpio);
}
static void cygnus_gpio_free(struct gpio_chip *gc, unsigned offset)
static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
{
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
struct iproc_gpio *chip = to_iproc_gpio(gc);
unsigned gpio = gc->base + offset;
if (!chip->pinmux_is_supported)
@ -311,13 +313,13 @@ static void cygnus_gpio_free(struct gpio_chip *gc, unsigned offset)
pinctrl_free_gpio(gpio);
}
static int cygnus_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
{
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
struct iproc_gpio *chip = to_iproc_gpio(gc);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, false);
iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
@ -325,15 +327,15 @@ static int cygnus_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
return 0;
}
static int cygnus_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
int val)
{
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
struct iproc_gpio *chip = to_iproc_gpio(gc);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, true);
cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
@ -341,29 +343,29 @@ static int cygnus_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
return 0;
}
static void cygnus_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
{
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
struct iproc_gpio *chip = to_iproc_gpio(gc);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
}
static int cygnus_gpio_get(struct gpio_chip *gc, unsigned gpio)
static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
{
struct cygnus_gpio *chip = to_cygnus_gpio(gc);
unsigned int offset = CYGNUS_GPIO_REG(gpio,
CYGNUS_GPIO_DATA_IN_OFFSET);
unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
struct iproc_gpio *chip = to_iproc_gpio(gc);
unsigned int offset = IPROC_GPIO_REG(gpio,
IPROC_GPIO_DATA_IN_OFFSET);
unsigned int shift = IPROC_GPIO_SHIFT(gpio);
return !!(readl(chip->base + offset) & BIT(shift));
}
static int cygnus_get_groups_count(struct pinctrl_dev *pctldev)
static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
{
return 1;
}
@ -372,20 +374,20 @@ static int cygnus_get_groups_count(struct pinctrl_dev *pctldev)
* Only one group: "gpio_grp", since this local pinctrl device only performs
* GPIO specific PINCONF configurations
*/
static const char *cygnus_get_group_name(struct pinctrl_dev *pctldev,
static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return "gpio_grp";
}
static const struct pinctrl_ops cygnus_pctrl_ops = {
.get_groups_count = cygnus_get_groups_count,
.get_group_name = cygnus_get_group_name,
static const struct pinctrl_ops iproc_pctrl_ops = {
.get_groups_count = iproc_get_groups_count,
.get_group_name = iproc_get_group_name,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_dt_free_map,
};
static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio,
static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
bool disable, bool pull_up)
{
unsigned long flags;
@ -393,11 +395,11 @@ static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio,
spin_lock_irqsave(&chip->lock, flags);
if (disable) {
cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, false);
iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false);
} else {
cygnus_set_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio,
iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
pull_up);
cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, true);
iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true);
}
spin_unlock_irqrestore(&chip->lock, flags);
@ -407,18 +409,18 @@ static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio,
return 0;
}
static void cygnus_gpio_get_pull(struct cygnus_gpio *chip, unsigned gpio,
static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
bool *disable, bool *pull_up)
{
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
*disable = !cygnus_get_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio);
*pull_up = cygnus_get_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio);
*disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
*pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
spin_unlock_irqrestore(&chip->lock, flags);
}
static int cygnus_gpio_set_strength(struct cygnus_gpio *chip, unsigned gpio,
static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
unsigned strength)
{
void __iomem *base;
@ -432,14 +434,14 @@ static int cygnus_gpio_set_strength(struct cygnus_gpio *chip, unsigned gpio,
if (chip->io_ctrl) {
base = chip->io_ctrl;
offset = CYGNUS_GPIO_DRV0_CTRL_OFFSET;
offset = IPROC_GPIO_DRV0_CTRL_OFFSET;
} else {
base = chip->base;
offset = CYGNUS_GPIO_REG(gpio,
CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET);
offset = IPROC_GPIO_REG(gpio,
IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET);
}
shift = CYGNUS_GPIO_SHIFT(gpio);
shift = IPROC_GPIO_SHIFT(gpio);
dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
strength);
@ -458,7 +460,7 @@ static int cygnus_gpio_set_strength(struct cygnus_gpio *chip, unsigned gpio,
return 0;
}
static int cygnus_gpio_get_strength(struct cygnus_gpio *chip, unsigned gpio,
static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
u16 *strength)
{
void __iomem *base;
@ -468,14 +470,14 @@ static int cygnus_gpio_get_strength(struct cygnus_gpio *chip, unsigned gpio,
if (chip->io_ctrl) {
base = chip->io_ctrl;
offset = CYGNUS_GPIO_DRV0_CTRL_OFFSET;
offset = IPROC_GPIO_DRV0_CTRL_OFFSET;
} else {
base = chip->base;
offset = CYGNUS_GPIO_REG(gpio,
CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET);
offset = IPROC_GPIO_REG(gpio,
IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET);
}
shift = CYGNUS_GPIO_SHIFT(gpio);
shift = IPROC_GPIO_SHIFT(gpio);
spin_lock_irqsave(&chip->lock, flags);
*strength = 0;
@ -493,44 +495,43 @@ static int cygnus_gpio_get_strength(struct cygnus_gpio *chip, unsigned gpio,
return 0;
}
static int cygnus_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *config)
{
struct cygnus_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned gpio = cygnus_pin_to_gpio(pin);
unsigned gpio = iproc_pin_to_gpio(pin);
u16 arg;
bool disable, pull_up;
int ret;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up);
iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
if (disable)
return 0;
else
return -EINVAL;
case PIN_CONFIG_BIAS_PULL_UP:
cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up);
iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
if (!disable && pull_up)
return 0;
else
return -EINVAL;
case PIN_CONFIG_BIAS_PULL_DOWN:
cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up);
iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
if (!disable && !pull_up)
return 0;
else
return -EINVAL;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = cygnus_gpio_get_strength(chip, gpio, &arg);
ret = iproc_gpio_get_strength(chip, gpio, &arg);
if (ret)
return ret;
else
*config = pinconf_to_config_packed(param, arg);
*config = pinconf_to_config_packed(param, arg);
return 0;
@ -541,13 +542,13 @@ static int cygnus_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
return -ENOTSUPP;
}
static int cygnus_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, unsigned num_configs)
{
struct cygnus_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
u16 arg;
unsigned i, gpio = cygnus_pin_to_gpio(pin);
unsigned i, gpio = iproc_pin_to_gpio(pin);
int ret = -ENOTSUPP;
for (i = 0; i < num_configs; i++) {
@ -556,25 +557,25 @@ static int cygnus_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ret = cygnus_gpio_set_pull(chip, gpio, true, false);
ret = iproc_gpio_set_pull(chip, gpio, true, false);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = cygnus_gpio_set_pull(chip, gpio, false, true);
ret = iproc_gpio_set_pull(chip, gpio, false, true);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = cygnus_gpio_set_pull(chip, gpio, false, false);
ret = iproc_gpio_set_pull(chip, gpio, false, false);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = cygnus_gpio_set_strength(chip, gpio, arg);
ret = iproc_gpio_set_strength(chip, gpio, arg);
if (ret < 0)
goto out;
break;
@ -589,20 +590,20 @@ static int cygnus_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
return ret;
}
static const struct pinconf_ops cygnus_pconf_ops = {
static const struct pinconf_ops iproc_pconf_ops = {
.is_generic = true,
.pin_config_get = cygnus_pin_config_get,
.pin_config_set = cygnus_pin_config_set,
.pin_config_get = iproc_pin_config_get,
.pin_config_set = iproc_pin_config_set,
};
/*
* Cygnus GPIO controller supports some PINCONF related configurations such as
* Iproc GPIO controller supports some PINCONF related configurations such as
* pull up, pull down, and drive strength, when the pin is configured to GPIO
*
* Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
* local GPIO pins
*/
static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip)
static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
{
struct pinctrl_desc *pctldesc = &chip->pctldesc;
struct pinctrl_pin_desc *pins;
@ -622,10 +623,10 @@ static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip)
}
pctldesc->name = dev_name(chip->dev);
pctldesc->pctlops = &cygnus_pctrl_ops;
pctldesc->pctlops = &iproc_pctrl_ops;
pctldesc->pins = pins;
pctldesc->npins = gc->ngpio;
pctldesc->confops = &cygnus_pconf_ops;
pctldesc->confops = &iproc_pconf_ops;
chip->pctl = pinctrl_register(pctldesc, chip->dev, chip);
if (IS_ERR(chip->pctl)) {
@ -636,59 +637,27 @@ static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip)
return 0;
}
static void cygnus_gpio_unregister_pinconf(struct cygnus_gpio *chip)
static void iproc_gpio_unregister_pinconf(struct iproc_gpio *chip)
{
if (chip->pctl)
pinctrl_unregister(chip->pctl);
pinctrl_unregister(chip->pctl);
}
struct cygnus_gpio_data {
unsigned num_gpios;
static const struct of_device_id iproc_gpio_of_match[] = {
{ .compatible = "brcm,cygnus-ccm-gpio" },
{ .compatible = "brcm,cygnus-asiu-gpio" },
{ .compatible = "brcm,cygnus-crmu-gpio" },
{ .compatible = "brcm,iproc-gpio" },
{ }
};
static const struct cygnus_gpio_data cygnus_cmm_gpio_data = {
.num_gpios = 24,
};
static const struct cygnus_gpio_data cygnus_asiu_gpio_data = {
.num_gpios = 146,
};
static const struct cygnus_gpio_data cygnus_crmu_gpio_data = {
.num_gpios = 6,
};
static const struct of_device_id cygnus_gpio_of_match[] = {
{
.compatible = "brcm,cygnus-ccm-gpio",
.data = &cygnus_cmm_gpio_data,
},
{
.compatible = "brcm,cygnus-asiu-gpio",
.data = &cygnus_asiu_gpio_data,
},
{
.compatible = "brcm,cygnus-crmu-gpio",
.data = &cygnus_crmu_gpio_data,
}
};
static int cygnus_gpio_probe(struct platform_device *pdev)
static int iproc_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct resource *res;
struct cygnus_gpio *chip;
struct iproc_gpio *chip;
struct gpio_chip *gc;
u32 ngpios;
int irq, ret;
const struct of_device_id *match;
const struct cygnus_gpio_data *gpio_data;
match = of_match_device(cygnus_gpio_of_match, dev);
if (!match)
return -ENODEV;
gpio_data = match->data;
ngpios = gpio_data->num_gpios;
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
@ -713,6 +682,11 @@ static int cygnus_gpio_probe(struct platform_device *pdev)
}
}
if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
dev_err(&pdev->dev, "missing ngpios DT property\n");
return -ENODEV;
}
spin_lock_init(&chip->lock);
gc = &chip->gc;
@ -722,12 +696,12 @@ static int cygnus_gpio_probe(struct platform_device *pdev)
gc->label = dev_name(dev);
gc->dev = dev;
gc->of_node = dev->of_node;
gc->request = cygnus_gpio_request;
gc->free = cygnus_gpio_free;
gc->direction_input = cygnus_gpio_direction_input;
gc->direction_output = cygnus_gpio_direction_output;
gc->set = cygnus_gpio_set;
gc->get = cygnus_gpio_get;
gc->request = iproc_gpio_request;
gc->free = iproc_gpio_free;
gc->direction_input = iproc_gpio_direction_input;
gc->direction_output = iproc_gpio_direction_output;
gc->set = iproc_gpio_set;
gc->get = iproc_gpio_get;
chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
"gpio-ranges");
@ -738,7 +712,7 @@ static int cygnus_gpio_probe(struct platform_device *pdev)
return ret;
}
ret = cygnus_gpio_register_pinconf(chip);
ret = iproc_gpio_register_pinconf(chip);
if (ret) {
dev_err(dev, "unable to register pinconf\n");
goto err_rm_gpiochip;
@ -747,21 +721,21 @@ static int cygnus_gpio_probe(struct platform_device *pdev)
/* optional GPIO interrupt support */
irq = platform_get_irq(pdev, 0);
if (irq) {
ret = gpiochip_irqchip_add(gc, &cygnus_gpio_irq_chip, 0,
ret = gpiochip_irqchip_add(gc, &iproc_gpio_irq_chip, 0,
handle_simple_irq, IRQ_TYPE_NONE);
if (ret) {
dev_err(dev, "no GPIO irqchip\n");
goto err_unregister_pinconf;
}
gpiochip_set_chained_irqchip(gc, &cygnus_gpio_irq_chip, irq,
cygnus_gpio_irq_handler);
gpiochip_set_chained_irqchip(gc, &iproc_gpio_irq_chip, irq,
iproc_gpio_irq_handler);
}
return 0;
err_unregister_pinconf:
cygnus_gpio_unregister_pinconf(chip);
iproc_gpio_unregister_pinconf(chip);
err_rm_gpiochip:
gpiochip_remove(gc);
@ -769,16 +743,16 @@ static int cygnus_gpio_probe(struct platform_device *pdev)
return ret;
}
static struct platform_driver cygnus_gpio_driver = {
static struct platform_driver iproc_gpio_driver = {
.driver = {
.name = "cygnus-gpio",
.of_match_table = cygnus_gpio_of_match,
.name = "iproc-gpio",
.of_match_table = iproc_gpio_of_match,
},
.probe = cygnus_gpio_probe,
.probe = iproc_gpio_probe,
};
static int __init cygnus_gpio_init(void)
static int __init iproc_gpio_init(void)
{
return platform_driver_probe(&cygnus_gpio_driver, cygnus_gpio_probe);
return platform_driver_probe(&iproc_gpio_driver, iproc_gpio_probe);
}
arch_initcall_sync(cygnus_gpio_init);
arch_initcall_sync(iproc_gpio_init);

749
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c Normal file
View File

@ -0,0 +1,749 @@
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
* supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
* pull up/down, slew and drive strength are also supported in this driver.
*
* Pins from the chipCommonA GPIO can be individually muxed to GPIO function,
* through the interaction with the NSP IOMUX controller.
*/
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/slab.h>
#include "../pinctrl-utils.h"
#define NSP_CHIP_A_INT_STATUS 0x00
#define NSP_CHIP_A_INT_MASK 0x04
#define NSP_GPIO_DATA_IN 0x40
#define NSP_GPIO_DATA_OUT 0x44
#define NSP_GPIO_OUT_EN 0x48
#define NSP_GPIO_INT_POLARITY 0x50
#define NSP_GPIO_INT_MASK 0x54
#define NSP_GPIO_EVENT 0x58
#define NSP_GPIO_EVENT_INT_MASK 0x5c
#define NSP_GPIO_EVENT_INT_POLARITY 0x64
#define NSP_CHIP_A_GPIO_INT_BIT 0x01
/* I/O parameters offset for chipcommon A GPIO */
#define NSP_GPIO_DRV_CTRL 0x00
#define NSP_GPIO_HYSTERESIS_EN 0x10
#define NSP_GPIO_SLEW_RATE_EN 0x14
#define NSP_PULL_UP_EN 0x18
#define NSP_PULL_DOWN_EN 0x1c
#define GPIO_DRV_STRENGTH_BITS 0x03
/*
* nsp GPIO core
*
* @dev: pointer to device
* @base: I/O register base for nsp GPIO controller
* @io_ctrl: I/O register base for PINCONF support outside the GPIO block
* @gc: GPIO chip
* @pctl: pointer to pinctrl_dev
* @pctldesc: pinctrl descriptor
* @irq_domain: pointer to irq domain
* @lock: lock to protect access to I/O registers
*/
struct nsp_gpio {
struct device *dev;
void __iomem *base;
void __iomem *io_ctrl;
struct gpio_chip gc;
struct pinctrl_dev *pctl;
struct pinctrl_desc pctldesc;
struct irq_domain *irq_domain;
spinlock_t lock;
};
enum base_type {
REG,
IO_CTRL
};
static inline struct nsp_gpio *to_nsp_gpio(struct gpio_chip *gc)
{
return container_of(gc, struct nsp_gpio, gc);
}
/*
* Mapping from PINCONF pins to GPIO pins is 1-to-1
*/
static inline unsigned nsp_pin_to_gpio(unsigned pin)
{
return pin;
}
/*
* nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
* nsp GPIO register
*
* @nsp_gpio: nsp GPIO device
* @base_type: reg base to modify
* @reg: register offset
* @gpio: GPIO pin
* @set: set or clear
*/
static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address,
unsigned int reg, unsigned gpio, bool set)
{
u32 val;
void __iomem *base_address;
if (address == IO_CTRL)
base_address = chip->io_ctrl;
else
base_address = chip->base;
val = readl(base_address + reg);
if (set)
val |= BIT(gpio);
else
val &= ~BIT(gpio);
writel(val, base_address + reg);
}
/*
* nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
* nsp GPIO register
*/
static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address,
unsigned int reg, unsigned gpio)
{
if (address == IO_CTRL)
return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
else
return !!(readl(chip->base + reg) & BIT(gpio));
}
static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
{
struct nsp_gpio *chip = (struct nsp_gpio *)data;
struct gpio_chip gc = chip->gc;
int bit;
unsigned long int_bits = 0;
u32 int_status;
/* go through the entire GPIOs and handle all interrupts */
int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
if (int_status & NSP_CHIP_A_GPIO_INT_BIT) {
unsigned int event, level;
/* Get level and edge interrupts */
event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
readl(chip->base + NSP_GPIO_EVENT);
level = readl(chip->base + NSP_GPIO_DATA_IN) ^
readl(chip->base + NSP_GPIO_INT_POLARITY);
level &= readl(chip->base + NSP_GPIO_INT_MASK);
int_bits = level | event;
for_each_set_bit(bit, &int_bits, gc.ngpio) {
/*
* Clear the interrupt before invoking the
* handler, so we do not leave any window
*/
writel(BIT(bit), chip->base + NSP_GPIO_EVENT);
generic_handle_irq(
irq_linear_revmap(chip->irq_domain, bit));
}
}
return int_bits ? IRQ_HANDLED : IRQ_NONE;
}
static void nsp_gpio_irq_ack(struct irq_data *d)
{
struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
unsigned gpio = d->hwirq;
u32 val = BIT(gpio);
u32 trigger_type;
trigger_type = irq_get_trigger_type(d->irq);
if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val);
}
/*
* nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
*
* @d: IRQ chip data
* @unmask: mask/unmask GPIO interrupt
*/
static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
{
struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
unsigned gpio = d->hwirq;
u32 trigger_type;
trigger_type = irq_get_trigger_type(d->irq);
if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
else
nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
}
static void nsp_gpio_irq_mask(struct irq_data *d)
{
struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
nsp_gpio_irq_set_mask(d, false);
spin_unlock_irqrestore(&chip->lock, flags);
}
static void nsp_gpio_irq_unmask(struct irq_data *d)
{
struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
nsp_gpio_irq_set_mask(d, true);
spin_unlock_irqrestore(&chip->lock, flags);
}
static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
unsigned gpio = d->hwirq;
bool level_low;
bool falling;
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
falling = false;
break;
case IRQ_TYPE_EDGE_FALLING:
falling = true;
break;
case IRQ_TYPE_LEVEL_HIGH:
level_low = false;
break;
case IRQ_TYPE_LEVEL_LOW:
level_low = true;
break;
default:
dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
type);
spin_unlock_irqrestore(&chip->lock, flags);
return -EINVAL;
}
nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
level_low ? "true" : "false", falling ? "true" : "false");
return 0;
}
static struct irq_chip nsp_gpio_irq_chip = {
.name = "gpio-a",
.irq_enable = nsp_gpio_irq_unmask,
.irq_disable = nsp_gpio_irq_mask,
.irq_ack = nsp_gpio_irq_ack,
.irq_mask = nsp_gpio_irq_mask,
.irq_unmask = nsp_gpio_irq_unmask,
.irq_set_type = nsp_gpio_irq_set_type,
};
/*
* Request the nsp IOMUX pinmux controller to mux individual pins to GPIO
*/
static int nsp_gpio_request(struct gpio_chip *gc, unsigned offset)
{
unsigned gpio = gc->base + offset;
return pinctrl_request_gpio(gpio);
}
static void nsp_gpio_free(struct gpio_chip *gc, unsigned offset)
{
unsigned gpio = gc->base + offset;
pinctrl_free_gpio(gpio);
}
static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
{
struct nsp_gpio *chip = to_nsp_gpio(gc);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
return 0;
}
static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
int val)
{
struct nsp_gpio *chip = to_nsp_gpio(gc);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
return 0;
}
static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
{
struct nsp_gpio *chip = to_nsp_gpio(gc);
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
}
static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
{
struct nsp_gpio *chip = to_nsp_gpio(gc);
return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
}
static int nsp_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct nsp_gpio *chip = to_nsp_gpio(gc);
return irq_linear_revmap(chip->irq_domain, offset);
}
static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
{
return 1;
}
/*
* Only one group: "gpio_grp", since this local pinctrl device only performs
* GPIO specific PINCONF configurations
*/
static const char *nsp_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return "gpio_grp";
}
static const struct pinctrl_ops nsp_pctrl_ops = {
.get_groups_count = nsp_get_groups_count,
.get_group_name = nsp_get_group_name,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_dt_free_map,
};
static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u16 slew)
{
if (slew)
nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true);
else
nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false);
return 0;
}
static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
bool pull_up, bool pull_down)
{
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
gpio, pull_up, pull_down);
return 0;
}
static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
bool *pull_up, bool *pull_down)
{
unsigned long flags;
spin_lock_irqsave(&chip->lock, flags);
*pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
*pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
spin_unlock_irqrestore(&chip->lock, flags);
}
static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
u16 strength)
{
u32 offset, shift, i;
u32 val;
unsigned long flags;
/* make sure drive strength is supported */
if (strength < 2 || strength > 16 || (strength % 2))
return -ENOTSUPP;
shift = gpio;
offset = NSP_GPIO_DRV_CTRL;
dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
strength);
spin_lock_irqsave(&chip->lock, flags);
strength = (strength / 2) - 1;
for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
val = readl(chip->io_ctrl + offset);
val &= ~BIT(shift);
val |= ((strength >> (i-1)) & 0x1) << shift;
writel(val, chip->io_ctrl + offset);
offset += 4;
}
spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
u16 *strength)
{
unsigned int offset, shift;
u32 val;
unsigned long flags;
int i;
offset = NSP_GPIO_DRV_CTRL;
shift = gpio;
spin_lock_irqsave(&chip->lock, flags);
*strength = 0;
for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
val = readl(chip->io_ctrl + offset) & BIT(shift);
val >>= shift;
*strength += (val << i);
offset += 4;
}
/* convert to mA */
*strength = (*strength + 1) * 2;
spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
int nsp_pin_config_group_get(struct pinctrl_dev *pctldev, unsigned selector,
unsigned long *config)
{
return 0;
}
int nsp_pin_config_group_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned long *configs, unsigned num_configs)
{
return 0;
}
static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *config)
{
struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned int gpio;
u16 arg = 0;
bool pull_up, pull_down;
int ret;
gpio = nsp_pin_to_gpio(pin);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
if ((pull_up == false) && (pull_down == false))
return 0;
else
return -EINVAL;
case PIN_CONFIG_BIAS_PULL_UP:
nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
if (pull_up)
return 0;
else
return -EINVAL;
case PIN_CONFIG_BIAS_PULL_DOWN:
nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
if (pull_down)
return 0;
else
return -EINVAL;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = nsp_gpio_get_strength(chip, gpio, &arg);
if (ret)
return ret;
*config = pinconf_to_config_packed(param, arg);
return 0;
default:
return -ENOTSUPP;
}
}
static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, unsigned num_configs)
{
struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
u16 arg;
unsigned int i, gpio;
int ret = -ENOTSUPP;
gpio = nsp_pin_to_gpio(pin);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ret = nsp_gpio_set_pull(chip, gpio, false, false);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = nsp_gpio_set_pull(chip, gpio, true, false);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = nsp_gpio_set_pull(chip, gpio, false, true);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = nsp_gpio_set_strength(chip, gpio, arg);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_SLEW_RATE:
ret = nsp_gpio_set_slew(chip, gpio, arg);
if (ret < 0)
goto out;
break;
default:
dev_err(chip->dev, "invalid configuration\n");
return -ENOTSUPP;
}
}
out:
return ret;
}
static const struct pinconf_ops nsp_pconf_ops = {
.is_generic = true,
.pin_config_get = nsp_pin_config_get,
.pin_config_set = nsp_pin_config_set,
.pin_config_group_get = nsp_pin_config_group_get,
.pin_config_group_set = nsp_pin_config_group_set,
};
/*
* NSP GPIO controller supports some PINCONF related configurations such as
* pull up, pull down, slew and drive strength, when the pin is configured
* to GPIO.
*
* Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
* local GPIO pins
*/
static int nsp_gpio_register_pinconf(struct nsp_gpio *chip)
{
struct pinctrl_desc *pctldesc = &chip->pctldesc;
struct pinctrl_pin_desc *pins;
struct gpio_chip *gc = &chip->gc;
int i;
pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < gc->ngpio; i++) {
pins[i].number = i;
pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
"gpio-%d", i);
if (!pins[i].name)
return -ENOMEM;
}
pctldesc->name = dev_name(chip->dev);
pctldesc->pctlops = &nsp_pctrl_ops;
pctldesc->pins = pins;
pctldesc->npins = gc->ngpio;
pctldesc->confops = &nsp_pconf_ops;
chip->pctl = pinctrl_register(pctldesc, chip->dev, chip);
if (IS_ERR(chip->pctl)) {
dev_err(chip->dev, "unable to register pinctrl device\n");
return PTR_ERR(chip->pctl);
}
return 0;
}
static const struct of_device_id nsp_gpio_of_match[] = {
{.compatible = "brcm,nsp-gpio-a",},
{}
};
static int nsp_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct resource *res;
struct nsp_gpio *chip;
struct gpio_chip *gc;
u32 val, count;
int irq, ret;
if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
dev_err(&pdev->dev, "Missing ngpios OF property\n");
return -ENODEV;
}
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->dev = dev;
platform_set_drvdata(pdev, chip);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
chip->base = devm_ioremap_resource(dev, res);
if (IS_ERR(chip->base)) {
dev_err(dev, "unable to map I/O memory\n");
return PTR_ERR(chip->base);
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
chip->io_ctrl = devm_ioremap_resource(dev, res);
if (IS_ERR(chip->io_ctrl)) {
dev_err(dev, "unable to map I/O memory\n");
return PTR_ERR(chip->io_ctrl);
}
spin_lock_init(&chip->lock);
gc = &chip->gc;
gc->base = -1;
gc->can_sleep = false;
gc->ngpio = val;
gc->label = dev_name(dev);
gc->dev = dev;
gc->of_node = dev->of_node;
gc->request = nsp_gpio_request;
gc->free = nsp_gpio_free;
gc->direction_input = nsp_gpio_direction_input;
gc->direction_output = nsp_gpio_direction_output;
gc->set = nsp_gpio_set;
gc->get = nsp_gpio_get;
gc->to_irq = nsp_gpio_to_irq;
/* optional GPIO interrupt support */
irq = platform_get_irq(pdev, 0);
if (irq > 0) {
/* Create irq domain so that each pin can be assigned an IRQ.*/
chip->irq_domain = irq_domain_add_linear(gc->of_node, gc->ngpio,
&irq_domain_simple_ops,
chip);
if (!chip->irq_domain) {
dev_err(&pdev->dev, "Couldn't allocate IRQ domain\n");
return -ENXIO;
}
/* Map each gpio to an IRQ and set the handler for gpiolib. */
for (count = 0; count < gc->ngpio; count++) {
int irq = irq_create_mapping(chip->irq_domain, count);
irq_set_chip_and_handler(irq, &nsp_gpio_irq_chip,
handle_simple_irq);
irq_set_chip_data(irq, chip);
}
/* Install ISR for this GPIO controller. */
ret = devm_request_irq(&pdev->dev, irq, nsp_gpio_irq_handler,
IRQF_SHARED, "gpio-a", chip);
if (ret) {
dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
irq, ret);
goto err_rm_gpiochip;
}
val = readl(chip->base + NSP_CHIP_A_INT_MASK);
val = val | NSP_CHIP_A_GPIO_INT_BIT;
writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
}
ret = gpiochip_add(gc);
if (ret < 0) {
dev_err(dev, "unable to add GPIO chip\n");
return ret;
}
ret = nsp_gpio_register_pinconf(chip);
if (ret) {
dev_err(dev, "unable to register pinconf\n");
goto err_rm_gpiochip;
}
return 0;
err_rm_gpiochip:
gpiochip_remove(gc);
return ret;
}
static struct platform_driver nsp_gpio_driver = {
.driver = {
.name = "nsp-gpio-a",
.of_match_table = nsp_gpio_of_match,
},
.probe = nsp_gpio_probe,
};
static int __init nsp_gpio_init(void)
{
return platform_driver_probe(&nsp_gpio_driver, nsp_gpio_probe);
}
arch_initcall_sync(nsp_gpio_init);

2
drivers/pinctrl/berlin/Makefile
View File

@ -1,4 +1,4 @@
obj-$(CONFIG_PINCTRL_BERLIN) += berlin.o
obj-y += berlin.o
obj-$(CONFIG_PINCTRL_BERLIN_BG2) += berlin-bg2.o
obj-$(CONFIG_PINCTRL_BERLIN_BG2CD) += berlin-bg2cd.o
obj-$(CONFIG_PINCTRL_BERLIN_BG2Q) += berlin-bg2q.o

2
drivers/pinctrl/mediatek/pinctrl-mt8127.c
View File

@ -351,7 +351,7 @@ static int __init mtk_pinctrl_init(void)
return platform_driver_register(&mtk_pinctrl_driver);
}
module_init(mtk_pinctrl_init);
arch_initcall(mtk_pinctrl_init);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver");

2
drivers/pinctrl/mediatek/pinctrl-mt8135.c
View File

@ -366,7 +366,7 @@ static int __init mtk_pinctrl_init(void)
return platform_driver_register(&mtk_pinctrl_driver);
}
module_init(mtk_pinctrl_init);
arch_initcall(mtk_pinctrl_init);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("MediaTek Pinctrl Driver");

2
drivers/pinctrl/mediatek/pinctrl-mt8173.c
View File

@ -394,7 +394,7 @@ static int __init mtk_pinctrl_init(void)
return platform_driver_register(&mtk_pinctrl_driver);
}
module_init(mtk_pinctrl_init);
arch_initcall(mtk_pinctrl_init);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek Pinctrl Driver");

28
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
View File

@ -509,6 +509,9 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
&num_configs);
if (err)
return err;
if (num_configs)
has_config = 1;
@ -520,21 +523,23 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
if (has_config && num_pins >= 1)
maps_per_pin++;
if (!num_pins || !maps_per_pin)
return -EINVAL;
if (!num_pins || !maps_per_pin) {
err = -EINVAL;
goto exit;
}
reserve = num_pins * maps_per_pin;
err = pinctrl_utils_reserve_map(pctldev, map,
reserved_maps, num_maps, reserve);
if (err < 0)
goto fail;
goto exit;
for (i = 0; i < num_pins; i++) {
err = of_property_read_u32_index(node, "pinmux",
i, &pinfunc);
if (err)
goto fail;
goto exit;
pin = MTK_GET_PIN_NO(pinfunc);
func = MTK_GET_PIN_FUNC(pinfunc);
@ -543,20 +548,21 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
func >= ARRAY_SIZE(mtk_gpio_functions)) {
dev_err(pctl->dev, "invalid pins value.\n");
err = -EINVAL;
goto fail;
goto exit;
}
grp = mtk_pctrl_find_group_by_pin(pctl, pin);
if (!grp) {
dev_err(pctl->dev, "unable to match pin %d to group\n",
pin);
return -EINVAL;
err = -EINVAL;
goto exit;
}
err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
reserved_maps, num_maps);
if (err < 0)
goto fail;
goto exit;
if (has_config) {
err = pinctrl_utils_add_map_configs(pctldev, map,
@ -564,13 +570,14 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (err < 0)
goto fail;
goto exit;
}
}
return 0;
err = 0;
fail:
exit:
kfree(configs);
return err;
}
@ -591,6 +598,7 @@ static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
&reserved_maps, num_maps);
if (ret < 0) {
pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
of_node_put(np);
return ret;
}
}

2
drivers/pinctrl/mvebu/Makefile
View File

@ -1,4 +1,4 @@
obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
obj-y += pinctrl-mvebu.o
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o

29
drivers/pinctrl/mvebu/pinctrl-mvebu.c
View File

@ -663,28 +663,20 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
/* assign mpp modes to groups */
for (n = 0; n < soc->nmodes; n++) {
struct mvebu_mpp_mode *mode = &soc->modes[n];
struct mvebu_pinctrl_group *grp =
mvebu_pinctrl_find_group_by_pid(pctl, mode->pid);
struct mvebu_mpp_ctrl_setting *set = &mode->settings[0];
struct mvebu_pinctrl_group *grp;
unsigned num_settings;
if (!grp) {
dev_warn(&pdev->dev, "unknown pinctrl group %d\n",
mode->pid);
continue;
}
for (num_settings = 0; ;) {
struct mvebu_mpp_ctrl_setting *set =
&mode->settings[num_settings];
for (num_settings = 0; ; set++) {
if (!set->name)
break;
num_settings++;
/* skip unsupported settings for this variant */
if (pctl->variant && !(pctl->variant & set->variant))
continue;
num_settings++;
/* find gpio/gpo/gpi settings */
if (strcmp(set->name, "gpio") == 0)
set->flags = MVEBU_SETTING_GPI |
@ -695,6 +687,17 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
set->flags = MVEBU_SETTING_GPI;
}
/* skip modes with no settings for this variant */
if (!num_settings)
continue;
grp = mvebu_pinctrl_find_group_by_pid(pctl, mode->pid);
if (!grp) {
dev_warn(&pdev->dev, "unknown pinctrl group %d\n",
mode->pid);
continue;
}
grp->settings = mode->settings;
grp->num_settings = num_settings;
}

1
drivers/pinctrl/pinconf-generic.c
View File

@ -220,6 +220,7 @@ static void parse_dt_cfg(struct device_node *np,
* parse the config properties into generic pinconfig values.
* @np: node containing the pinconfig properties
* @configs: array with nconfigs entries containing the generic pinconf values
* must be freed when no longer necessary.
* @nconfigs: umber of configurations
*/
int pinconf_generic_parse_dt_config(struct device_node *np,

24
drivers/pinctrl/pinctrl-adi2.c
View File

@ -1102,32 +1102,24 @@ static struct platform_driver adi_gpio_driver = {
},
};
static struct platform_driver * const drivers[] = {
&adi_pinctrl_driver,
&adi_gpio_pint_driver,
&adi_gpio_driver,
};
static int __init adi_pinctrl_setup(void)
{
int ret;
ret = platform_driver_register(&adi_pinctrl_driver);
ret = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
if (ret)
return ret;
ret = platform_driver_register(&adi_gpio_pint_driver);
if (ret)
goto pint_error;
ret = platform_driver_register(&adi_gpio_driver);
if (ret)
goto gpio_error;
#ifdef CONFIG_PM
register_syscore_ops(&gpio_pm_syscore_ops);
#endif
return ret;
gpio_error:
platform_driver_unregister(&adi_gpio_pint_driver);
pint_error:
platform_driver_unregister(&adi_pinctrl_driver);
return ret;
return 0;
}
arch_initcall(adi_pinctrl_setup);

17
drivers/pinctrl/pinctrl-at91-pio4.c
View File

@ -500,7 +500,8 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
if (!num_pins) {
dev_err(pctldev->dev, "no pins found in node %s\n",
of_node_full_name(np));
return -EINVAL;
ret = -EINVAL;
goto exit;
}
/*
@ -514,19 +515,19 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
reserve);
if (ret < 0)
return ret;
goto exit;
for (i = 0; i < num_pins; i++) {
const char *group, *func;
ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
if (ret)
return ret;
goto exit;
ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
&func);
if (ret)
return ret;
goto exit;
pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
group, func);
@ -537,11 +538,13 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (ret < 0)
return ret;
goto exit;
}
}
return 0;
exit:
kfree(configs);
return ret;
}
static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
@ -1000,7 +1003,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
atmel_pioctrl->irqs[i] = res->start;
irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
irq_set_handler_data(res->start, atmel_pioctrl);
dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start);
dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
}
atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,

14
drivers/pinctrl/pinctrl-at91.c
View File

@ -1828,20 +1828,20 @@ static struct platform_driver at91_pinctrl_driver = {
.remove = at91_pinctrl_remove,
};
static struct platform_driver * const drivers[] = {
&at91_gpio_driver,
&at91_pinctrl_driver,
};
static int __init at91_pinctrl_init(void)
{
int ret;
ret = platform_driver_register(&at91_gpio_driver);
if (ret)
return ret;
return platform_driver_register(&at91_pinctrl_driver);
return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
}
arch_initcall(at91_pinctrl_init);
static void __exit at91_pinctrl_exit(void)
{
platform_driver_unregister(&at91_pinctrl_driver);
platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
}
module_exit(at91_pinctrl_exit);

8
drivers/pinctrl/pinctrl-lantiq.h
View File

@ -162,6 +162,14 @@ enum ltq_pin {
GPIO53,
GPIO54,
GPIO55,
GPIO56,
GPIO57,
GPIO58,
GPIO59,
GPIO60, /* 60 */
GPIO61,
GPIO62,
GPIO63,
GPIO64,
GPIO65,

58
drivers/pinctrl/pinctrl-rockchip.c
View File

@ -614,6 +614,40 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
}
}
#define RK3228_PULL_OFFSET 0x100
static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
*reg = RK3228_PULL_OFFSET;
*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
}
#define RK3228_DRV_GRF_OFFSET 0x200
static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
*reg = RK3228_DRV_GRF_OFFSET;
*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
*bit *= RK3288_DRV_BITS_PER_PIN;
}
#define RK3368_PULL_GRF_OFFSET 0x100
#define RK3368_PULL_PMU_OFFSET 0x10
@ -1258,8 +1292,10 @@ static int rockchip_pinctrl_parse_functions(struct device_node *np,
func->groups[i] = child->name;
grp = &info->groups[grp_index++];
ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
if (ret)
if (ret) {
of_node_put(child);
return ret;
}
}
return 0;
@ -1304,6 +1340,7 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
ret = rockchip_pinctrl_parse_functions(child, info, i++);
if (ret) {
dev_err(&pdev->dev, "failed to parse function\n");
of_node_put(child);
return ret;
}
}
@ -2143,6 +2180,23 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
.pull_calc_reg = rk3188_calc_pull_reg_and_bit,
};
static struct rockchip_pin_bank rk3228_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
.pin_banks = rk3228_pin_banks,
.nr_banks = ARRAY_SIZE(rk3228_pin_banks),
.label = "RK3228-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
.pull_calc_reg = rk3228_calc_pull_reg_and_bit,
.drv_calc_reg = rk3228_calc_drv_reg_and_bit,
};
static struct rockchip_pin_bank rk3288_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
@ -2220,6 +2274,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = (void *)&rk3066b_pin_ctrl },
{ .compatible = "rockchip,rk3188-pinctrl",
.data = (void *)&rk3188_pin_ctrl },
{ .compatible = "rockchip,rk3228-pinctrl",
.data = (void *)&rk3228_pin_ctrl },
{ .compatible = "rockchip,rk3288-pinctrl",
.data = (void *)&rk3288_pin_ctrl },
{ .compatible = "rockchip,rk3368-pinctrl",

5
drivers/pinctrl/pinctrl-single.c
View File

@ -1484,10 +1484,7 @@ static void pcs_irq_free(struct pcs_device *pcs)
static void pcs_free_resources(struct pcs_device *pcs)
{
pcs_irq_free(pcs);
if (pcs->pctl)
pinctrl_unregister(pcs->pctl);
pinctrl_unregister(pcs->pctl);
pcs_free_funcs(pcs);
pcs_free_pingroups(pcs);
}

4
drivers/pinctrl/pinctrl-tegra-xusb.c
View File

@ -253,8 +253,10 @@ static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
&reserved_maps,
num_maps);
if (err < 0)
if (err < 0) {
of_node_put(np);
return err;
}
}
return 0;

1
drivers/pinctrl/pinctrl-tegra.c
View File

@ -217,6 +217,7 @@ static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
if (ret < 0) {
pinctrl_utils_dt_free_map(pctldev, *map,
*num_maps);
of_node_put(np);
return ret;
}
}

1187
drivers/pinctrl/pinctrl-xway.c
View File

File diff suppressed because it is too large Load Diff

17
drivers/pinctrl/pxa/Kconfig Normal file
View File

@ -0,0 +1,17 @@
if (ARCH_PXA || COMPILE_TEST)
config PINCTRL_PXA
bool
select PINMUX
select PINCONF
select GENERIC_PINCONF
config PINCTRL_PXA27X
tristate "Marvell PXA27x pin controller driver"
select PINCTRL_PXA
default y if PXA27x
help
This is the pinctrl, pinmux, pinconf driver for the Marvell
PXA2xx block found in the pxa25x and pxa27x platforms.
endif

2
drivers/pinctrl/pxa/Makefile Normal file
View File

@ -0,0 +1,2 @@
# Marvell PXA pin control drivers
obj-$(CONFIG_PINCTRL_PXA27X) += pinctrl-pxa2xx.o pinctrl-pxa27x.o

566
drivers/pinctrl/pxa/pinctrl-pxa27x.c Normal file
View File

@ -0,0 +1,566 @@
/*
* Marvell PXA27x family pin control
*
* Copyright (C) 2015 Robert Jarzmik
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-pxa2xx.h"
static const struct pxa_desc_pin pxa27x_pins[] = {
PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(0)),
PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(1)),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(9),
PXA_FUNCTION(0, 3, "FFCTS"),
PXA_FUNCTION(1, 1, "HZ_CLK"),
PXA_FUNCTION(1, 3, "CHOUT<0>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(10),
PXA_FUNCTION(0, 1, "FFDCD"),
PXA_FUNCTION(0, 3, "USB_P3_5"),
PXA_FUNCTION(1, 1, "HZ_CLK"),
PXA_FUNCTION(1, 3, "CHOUT<1>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(11),
PXA_FUNCTION(0, 1, "EXT_SYNC<0>"),
PXA_FUNCTION(0, 2, "SSPRXD2"),
PXA_FUNCTION(0, 3, "USB_P3_1"),
PXA_FUNCTION(1, 1, "CHOUT<0>"),
PXA_FUNCTION(1, 1, "PWM_OUT<2>"),
PXA_FUNCTION(1, 3, "48_MHz")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(12),
PXA_FUNCTION(0, 1, "EXT_SYNC<1>"),
PXA_FUNCTION(0, 2, "CIF_DD<7>"),
PXA_FUNCTION(1, 1, "CHOUT<1>"),
PXA_FUNCTION(1, 1, "PWM_OUT<3>"),
PXA_FUNCTION(1, 3, "48_MHz")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(13),
PXA_FUNCTION(0, 1, "CLK_EXT"),
PXA_FUNCTION(0, 2, "KP_DKIN<7>"),
PXA_FUNCTION(0, 3, "KP_MKIN<7>"),
PXA_FUNCTION(1, 1, "SSPTXD2")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(14),
PXA_FUNCTION(0, 1, "L_VSYNC"),
PXA_FUNCTION(0, 2, "SSPSFRM2"),
PXA_FUNCTION(1, 1, "SSPSFRM2"),
PXA_FUNCTION(1, 3, "UCLK")),
PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(15)),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(16),
PXA_FUNCTION(0, 1, "KP_MKIN<5>"),
PXA_FUNCTION(1, 2, "PWM_OUT<0>"),
PXA_FUNCTION(1, 3, "FFTXD")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(17),
PXA_FUNCTION(0, 1, "KP_MKIN<6>"),
PXA_FUNCTION(0, 2, "CIF_DD<6>"),
PXA_FUNCTION(1, 2, "PWM_OUT<1>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(18),
PXA_FUNCTION(0, 1, "RDY")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(19),
PXA_FUNCTION(0, 1, "SSPSCLK2"),
PXA_FUNCTION(0, 3, "FFRXD"),
PXA_FUNCTION(1, 1, "SSPSCLK2"),
PXA_FUNCTION(1, 2, "L_CS"),
PXA_FUNCTION(1, 3, "nURST")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(20),
PXA_FUNCTION(0, 1, "DREQ<0>"),
PXA_FUNCTION(0, 2, "MBREQ"),
PXA_FUNCTION(1, 1, "nSDCS<2>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(21),
PXA_FUNCTION(1, 1, "nSDCS<3>"),
PXA_FUNCTION(1, 2, "DVAL<0>"),
PXA_FUNCTION(1, 3, "MBGNT")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(22),
PXA_FUNCTION(0, 1, "SSPEXTCLK2"),
PXA_FUNCTION(0, 2, "SSPSCLKEN2"),
PXA_FUNCTION(0, 3, "SSPSCLK2"),
PXA_FUNCTION(1, 1, "KP_MKOUT<7>"),
PXA_FUNCTION(1, 2, "SSPSYSCLK2"),
PXA_FUNCTION(1, 3, "SSPSCLK2")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(23),
PXA_FUNCTION(0, 2, "SSPSCLK"),
PXA_FUNCTION(1, 1, "CIF_MCLK"),
PXA_FUNCTION(1, 1, "SSPSCLK")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(24),
PXA_FUNCTION(0, 1, "CIF_FV"),
PXA_FUNCTION(0, 2, "SSPSFRM"),
PXA_FUNCTION(1, 1, "CIF_FV"),
PXA_FUNCTION(1, 2, "SSPSFRM")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(25),
PXA_FUNCTION(0, 1, "CIF_LV"),
PXA_FUNCTION(1, 1, "CIF_LV"),
PXA_FUNCTION(1, 2, "SSPTXD")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(26),
PXA_FUNCTION(0, 1, "SSPRXD"),
PXA_FUNCTION(0, 2, "CIF_PCLK"),
PXA_FUNCTION(0, 3, "FFCTS")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(27),
PXA_FUNCTION(0, 1, "SSPEXTCLK"),
PXA_FUNCTION(0, 2, "SSPSCLKEN"),
PXA_FUNCTION(0, 3, "CIF_DD<0>"),
PXA_FUNCTION(1, 1, "SSPSYSCLK"),
PXA_FUNCTION(1, 3, "FFRTS")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(28),
PXA_FUNCTION(0, 1, "AC97_BITCLK"),
PXA_FUNCTION(0, 2, "I2S_BITCLK"),
PXA_FUNCTION(0, 3, "SSPSFRM"),
PXA_FUNCTION(1, 1, "I2S_BITCLK"),
PXA_FUNCTION(1, 3, "SSPSFRM")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(29),
PXA_FUNCTION(0, 1, "AC97_SDATA_IN_0"),
PXA_FUNCTION(0, 2, "I2S_SDATA_IN"),
PXA_FUNCTION(0, 3, "SSPSCLK"),
PXA_FUNCTION(1, 1, "SSPRXD2"),
PXA_FUNCTION(1, 3, "SSPSCLK")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(30),
PXA_FUNCTION(1, 1, "I2S_SDATA_OUT"),
PXA_FUNCTION(1, 2, "AC97_SDATA_OUT"),
PXA_FUNCTION(1, 3, "USB_P3_2")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(31),
PXA_FUNCTION(1, 1, "I2S_SYNC"),
PXA_FUNCTION(1, 2, "AC97_SYNC"),
PXA_FUNCTION(1, 3, "USB_P3_6")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(32),
PXA_FUNCTION(1, 1, "MSSCLK"),
PXA_FUNCTION(1, 2, "MMCLK")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(33),
PXA_FUNCTION(0, 1, "FFRXD"),
PXA_FUNCTION(0, 2, "FFDSR"),
PXA_FUNCTION(1, 1, "DVAL<1>"),
PXA_FUNCTION(1, 2, "nCS<5>"),
PXA_FUNCTION(1, 3, "MBGNT")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(34),
PXA_FUNCTION(0, 1, "FFRXD"),
PXA_FUNCTION(0, 2, "KP_MKIN<3>"),
PXA_FUNCTION(0, 3, "SSPSCLK3"),
PXA_FUNCTION(1, 1, "USB_P2_2"),
PXA_FUNCTION(1, 3, "SSPSCLK3")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(35),
PXA_FUNCTION(0, 1, "FFCTS"),
PXA_FUNCTION(0, 2, "USB_P2_1"),
PXA_FUNCTION(0, 3, "SSPSFRM3"),
PXA_FUNCTION(1, 2, "KP_MKOUT<6>"),
PXA_FUNCTION(1, 3, "SSPTXD3")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(36),
PXA_FUNCTION(0, 1, "FFDCD"),
PXA_FUNCTION(0, 2, "SSPSCLK2"),
PXA_FUNCTION(0, 3, "KP_MKIN<7>"),
PXA_FUNCTION(1, 1, "USB_P2_4"),
PXA_FUNCTION(1, 2, "SSPSCLK2")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(37),
PXA_FUNCTION(0, 1, "FFDSR"),
PXA_FUNCTION(0, 2, "SSPSFRM2"),
PXA_FUNCTION(0, 3, "KP_MKIN<3>"),
PXA_FUNCTION(1, 1, "USB_P2_8"),
PXA_FUNCTION(1, 2, "SSPSFRM2"),
PXA_FUNCTION(1, 3, "FFTXD")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(38),
PXA_FUNCTION(0, 1, "FFRI"),
PXA_FUNCTION(0, 2, "KP_MKIN<4>"),
PXA_FUNCTION(0, 3, "USB_P2_3"),
PXA_FUNCTION(1, 1, "SSPTXD3"),
PXA_FUNCTION(1, 2, "SSPTXD2"),
PXA_FUNCTION(1, 3, "PWM_OUT<0>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(39),
PXA_FUNCTION(0, 1, "KP_MKIN<4>"),
PXA_FUNCTION(0, 3, "SSPSFRM3"),
PXA_FUNCTION(1, 1, "USB_P2_6"),
PXA_FUNCTION(1, 2, "FFTXD"),
PXA_FUNCTION(1, 3, "SSPSFRM3")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(40),
PXA_FUNCTION(0, 1, "SSPRXD2"),
PXA_FUNCTION(0, 3, "USB_P2_5"),
PXA_FUNCTION(1, 1, "KP_MKOUT<6>"),
PXA_FUNCTION(1, 2, "FFDTR"),
PXA_FUNCTION(1, 3, "SSPSCLK3")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(41),
PXA_FUNCTION(0, 1, "FFRXD"),
PXA_FUNCTION(0, 2, "USB_P2_7"),
PXA_FUNCTION(0, 3, "SSPRXD3"),
PXA_FUNCTION(1, 1, "KP_MKOUT<7>"),
PXA_FUNCTION(1, 2, "FFRTS")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(42),
PXA_FUNCTION(0, 1, "BTRXD"),
PXA_FUNCTION(0, 2, "ICP_RXD"),
PXA_FUNCTION(1, 3, "CIF_MCLK")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(43),
PXA_FUNCTION(0, 3, "CIF_FV"),
PXA_FUNCTION(1, 1, "ICP_TXD"),
PXA_FUNCTION(1, 2, "BTTXD"),
PXA_FUNCTION(1, 3, "CIF_FV")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(44),
PXA_FUNCTION(0, 1, "BTCTS"),
PXA_FUNCTION(0, 3, "CIF_LV"),
PXA_FUNCTION(1, 3, "CIF_LV")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(45),
PXA_FUNCTION(0, 3, "CIF_PCLK"),
PXA_FUNCTION(1, 1, "AC97_SYSCLK"),
PXA_FUNCTION(1, 2, "BTRTS"),
PXA_FUNCTION(1, 3, "SSPSYSCLK3")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(46),
PXA_FUNCTION(0, 1, "ICP_RXD"),
PXA_FUNCTION(0, 2, "STD_RXD"),
PXA_FUNCTION(1, 2, "PWM_OUT<2>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(47),
PXA_FUNCTION(0, 1, "CIF_DD<0>"),
PXA_FUNCTION(1, 1, "STD_TXD"),
PXA_FUNCTION(1, 2, "ICP_TXD"),
PXA_FUNCTION(1, 3, "PWM_OUT<3>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(48),
PXA_FUNCTION(0, 1, "CIF_DD<5>"),
PXA_FUNCTION(1, 1, "BB_OB_DAT<1>"),
PXA_FUNCTION(1, 2, "nPOE")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(49),
PXA_FUNCTION(1, 2, "nPWE")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(50),
PXA_FUNCTION(0, 1, "CIF_DD<3>"),
PXA_FUNCTION(0, 3, "SSPSCLK2"),
PXA_FUNCTION(1, 1, "BB_OB_DAT<2>"),
PXA_FUNCTION(1, 2, "nPIOR"),
PXA_FUNCTION(1, 3, "SSPSCLK2")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(51),
PXA_FUNCTION(0, 1, "CIF_DD<2>"),
PXA_FUNCTION(1, 1, "BB_OB_DAT<3>"),
PXA_FUNCTION(1, 2, "nPIOW")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(52),
PXA_FUNCTION(0, 1, "CIF_DD<4>"),
PXA_FUNCTION(0, 2, "SSPSCLK3"),
PXA_FUNCTION(1, 1, "BB_OB_CLK"),
PXA_FUNCTION(1, 2, "SSPSCLK3")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(53),
PXA_FUNCTION(0, 1, "FFRXD"),
PXA_FUNCTION(0, 2, "USB_P2_3"),
PXA_FUNCTION(1, 1, "BB_OB_STB"),
PXA_FUNCTION(1, 2, "CIF_MCLK"),
PXA_FUNCTION(1, 3, "SSPSYSCLK")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(54),
PXA_FUNCTION(0, 2, "BB_OB_WAIT"),
PXA_FUNCTION(0, 3, "CIF_PCLK"),
PXA_FUNCTION(1, 2, "nPCE<2>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(55),
PXA_FUNCTION(0, 1, "CIF_DD<1>"),
PXA_FUNCTION(0, 2, "BB_IB_DAT<1>"),
PXA_FUNCTION(1, 2, "nPREG")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(56),
PXA_FUNCTION(0, 1, "nPWAIT"),
PXA_FUNCTION(0, 2, "BB_IB_DAT<2>"),
PXA_FUNCTION(1, 1, "USB_P3_4")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(57),
PXA_FUNCTION(0, 1, "nIOS16"),
PXA_FUNCTION(0, 2, "BB_IB_DAT<3>"),
PXA_FUNCTION(1, 3, "SSPTXD")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(58),
PXA_FUNCTION(0, 2, "LDD<0>"),
PXA_FUNCTION(1, 2, "LDD<0>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(59),
PXA_FUNCTION(0, 2, "LDD<1>"),
PXA_FUNCTION(1, 2, "LDD<1>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(60),
PXA_FUNCTION(0, 2, "LDD<2>"),
PXA_FUNCTION(1, 2, "LDD<2>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(61),
PXA_FUNCTION(0, 2, "LDD<3>"),
PXA_FUNCTION(1, 2, "LDD<3>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(62),
PXA_FUNCTION(0, 2, "LDD<4>"),
PXA_FUNCTION(1, 2, "LDD<4>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(63),
PXA_FUNCTION(0, 2, "LDD<5>"),
PXA_FUNCTION(1, 2, "LDD<5>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(64),
PXA_FUNCTION(0, 2, "LDD<6>"),
PXA_FUNCTION(1, 2, "LDD<6>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(65),
PXA_FUNCTION(0, 2, "LDD<7>"),
PXA_FUNCTION(1, 2, "LDD<7>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(66),
PXA_FUNCTION(0, 2, "LDD<8>"),
PXA_FUNCTION(1, 2, "LDD<8>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(67),
PXA_FUNCTION(0, 2, "LDD<9>"),
PXA_FUNCTION(1, 2, "LDD<9>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(68),
PXA_FUNCTION(0, 2, "LDD<10>"),
PXA_FUNCTION(1, 2, "LDD<10>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(69),
PXA_FUNCTION(0, 2, "LDD<11>"),
PXA_FUNCTION(1, 2, "LDD<11>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(70),
PXA_FUNCTION(0, 2, "LDD<12>"),
PXA_FUNCTION(1, 2, "LDD<12>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(71),
PXA_FUNCTION(0, 2, "LDD<13>"),
PXA_FUNCTION(1, 2, "LDD<13>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(72),
PXA_FUNCTION(0, 2, "LDD<14>"),
PXA_FUNCTION(1, 2, "LDD<14>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(73),
PXA_FUNCTION(0, 2, "LDD<15>"),
PXA_FUNCTION(1, 2, "LDD<15>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(74),
PXA_FUNCTION(1, 2, "L_FCLK_RD")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(75),
PXA_FUNCTION(1, 2, "L_LCLK_A0")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(76),
PXA_FUNCTION(1, 2, "L_PCLK_WR")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(77),
PXA_FUNCTION(1, 2, "L_BIAS")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(78),
PXA_FUNCTION(1, 1, "nPCE<2>"),
PXA_FUNCTION(1, 2, "nCS<2>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(79),
PXA_FUNCTION(1, 1, "PSKTSEL"),
PXA_FUNCTION(1, 2, "nCS<3>"),
PXA_FUNCTION(1, 3, "PWM_OUT<2>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(80),
PXA_FUNCTION(0, 1, "DREQ<1>"),
PXA_FUNCTION(0, 2, "MBREQ"),
PXA_FUNCTION(1, 2, "nCS<4>"),
PXA_FUNCTION(1, 3, "PWM_OUT<3>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(81),
PXA_FUNCTION(0, 2, "CIF_DD<0>"),
PXA_FUNCTION(1, 1, "SSPTXD3"),
PXA_FUNCTION(1, 2, "BB_OB_DAT<0>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(82),
PXA_FUNCTION(0, 1, "SSPRXD3"),
PXA_FUNCTION(0, 2, "BB_IB_DAT<0>"),
PXA_FUNCTION(0, 3, "CIF_DD<5>"),
PXA_FUNCTION(1, 3, "FFDTR")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(83),
PXA_FUNCTION(0, 1, "SSPSFRM3"),
PXA_FUNCTION(0, 2, "BB_IB_CLK"),
PXA_FUNCTION(0, 3, "CIF_DD<5>"),
PXA_FUNCTION(1, 1, "SSPSFRM3"),
PXA_FUNCTION(1, 2, "FFTXD"),
PXA_FUNCTION(1, 3, "FFRTS")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(84),
PXA_FUNCTION(0, 1, "SSPCLK3"),
PXA_FUNCTION(0, 2, "BB_IB_STB"),
PXA_FUNCTION(0, 3, "CIF_FV"),
PXA_FUNCTION(1, 1, "SSPCLK3"),
PXA_FUNCTION(1, 3, "CIF_FV")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(85),
PXA_FUNCTION(0, 1, "FFRXD"),
PXA_FUNCTION(0, 2, "DREQ<2>"),
PXA_FUNCTION(0, 3, "CIF_LV"),
PXA_FUNCTION(1, 1, "nPCE<1>"),
PXA_FUNCTION(1, 2, "BB_IB_WAIT"),
PXA_FUNCTION(1, 3, "CIF_LV")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(86),
PXA_FUNCTION(0, 1, "SSPRXD2"),
PXA_FUNCTION(0, 2, "LDD<16>"),
PXA_FUNCTION(0, 3, "USB_P3_5"),
PXA_FUNCTION(1, 1, "nPCE<1>"),
PXA_FUNCTION(1, 2, "LDD<16>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(87),
PXA_FUNCTION(0, 1, "nPCE<2>"),
PXA_FUNCTION(0, 2, "LDD<17>"),
PXA_FUNCTION(0, 3, "USB_P3_1"),
PXA_FUNCTION(1, 1, "SSPTXD2"),
PXA_FUNCTION(1, 2, "LDD<17>"),
PXA_FUNCTION(1, 3, "SSPSFRM2")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(88),
PXA_FUNCTION(0, 1, "USBHPWR<1>"),
PXA_FUNCTION(0, 2, "SSPRXD2"),
PXA_FUNCTION(0, 3, "SSPSFRM2"),
PXA_FUNCTION(1, 2, "SSPTXD2"),
PXA_FUNCTION(1, 3, "SSPSFRM2")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(89),
PXA_FUNCTION(0, 1, "SSPRXD3"),
PXA_FUNCTION(0, 3, "FFRI"),
PXA_FUNCTION(1, 1, "AC97_SYSCLK"),
PXA_FUNCTION(1, 2, "USBHPEN<1>"),
PXA_FUNCTION(1, 3, "SSPTXD2")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(90),
PXA_FUNCTION(0, 1, "KP_MKIN<5>"),
PXA_FUNCTION(0, 3, "USB_P3_5"),
PXA_FUNCTION(1, 1, "CIF_DD<4>"),
PXA_FUNCTION(1, 2, "nURST")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(91),
PXA_FUNCTION(0, 1, "KP_MKIN<6>"),
PXA_FUNCTION(0, 3, "USB_P3_1"),
PXA_FUNCTION(1, 1, "CIF_DD<5>"),
PXA_FUNCTION(1, 2, "UCLK")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(92),
PXA_FUNCTION(0, 1, "MMDAT<0>"),
PXA_FUNCTION(1, 1, "MMDAT<0>"),
PXA_FUNCTION(1, 2, "MSBS")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(93),
PXA_FUNCTION(0, 1, "KP_DKIN<0>"),
PXA_FUNCTION(0, 2, "CIF_DD<6>"),
PXA_FUNCTION(1, 1, "AC97_SDATA_OUT")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(94),
PXA_FUNCTION(0, 1, "KP_DKIN<1>"),
PXA_FUNCTION(0, 2, "CIF_DD<5>"),
PXA_FUNCTION(1, 1, "AC97_SYNC")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(95),
PXA_FUNCTION(0, 1, "KP_DKIN<2>"),
PXA_FUNCTION(0, 2, "CIF_DD<4>"),
PXA_FUNCTION(0, 3, "KP_MKIN<6>"),
PXA_FUNCTION(1, 1, "AC97_RESET_n")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(96),
PXA_FUNCTION(0, 1, "KP_DKIN<3>"),
PXA_FUNCTION(0, 2, "MBREQ"),
PXA_FUNCTION(0, 3, "FFRXD"),
PXA_FUNCTION(1, 2, "DVAL<1>"),
PXA_FUNCTION(1, 3, "KP_MKOUT<6>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(97),
PXA_FUNCTION(0, 1, "KP_DKIN<4>"),
PXA_FUNCTION(0, 2, "DREQ<1>"),
PXA_FUNCTION(0, 3, "KP_MKIN<3>"),
PXA_FUNCTION(1, 2, "MBGNT")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(98),
PXA_FUNCTION(0, 1, "KP_DKIN<5>"),
PXA_FUNCTION(0, 2, "CIF_DD<0>"),
PXA_FUNCTION(0, 3, "KP_MKIN<4>"),
PXA_FUNCTION(1, 1, "AC97_SYSCLK"),
PXA_FUNCTION(1, 3, "FFRTS")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(99),
PXA_FUNCTION(0, 1, "KP_DKIN<6>"),
PXA_FUNCTION(0, 2, "AC97_SDATA_IN_1"),
PXA_FUNCTION(0, 3, "KP_MKIN<5>"),
PXA_FUNCTION(1, 3, "FFTXD")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(100),
PXA_FUNCTION(0, 1, "KP_MKIN<0>"),
PXA_FUNCTION(0, 2, "DREQ<2>"),
PXA_FUNCTION(0, 3, "FFCTS")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(101),
PXA_FUNCTION(0, 1, "KP_MKIN<1>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(102),
PXA_FUNCTION(0, 1, "KP_MKIN<2>"),
PXA_FUNCTION(0, 3, "FFRXD"),
PXA_FUNCTION(1, 1, "nPCE<1>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(103),
PXA_FUNCTION(0, 1, "CIF_DD<3>"),
PXA_FUNCTION(1, 2, "KP_MKOUT<0>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(104),
PXA_FUNCTION(0, 1, "CIF_DD<2>"),
PXA_FUNCTION(1, 1, "PSKTSEL"),
PXA_FUNCTION(1, 2, "KP_MKOUT<1>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(105),
PXA_FUNCTION(0, 1, "CIF_DD<1>"),
PXA_FUNCTION(1, 1, "nPCE<2>"),
PXA_FUNCTION(1, 2, "KP_MKOUT<2>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(106),
PXA_FUNCTION(0, 1, "CIF_DD<9>"),
PXA_FUNCTION(1, 2, "KP_MKOUT<3>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(107),
PXA_FUNCTION(0, 1, "CIF_DD<8>"),
PXA_FUNCTION(1, 2, "KP_MKOUT<4>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(108),
PXA_FUNCTION(0, 1, "CIF_DD<7>"),
PXA_FUNCTION(1, 1, "CHOUT<0>"),
PXA_FUNCTION(1, 2, "KP_MKOUT<5>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(109),
PXA_FUNCTION(0, 1, "MMDAT<1>"),
PXA_FUNCTION(0, 2, "MSSDIO"),
PXA_FUNCTION(1, 1, "MMDAT<1>"),
PXA_FUNCTION(1, 2, "MSSDIO")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(110),
PXA_FUNCTION(0, 1, "MMDAT<2>"),
PXA_FUNCTION(1, 1, "MMDAT<2>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(111),
PXA_FUNCTION(0, 1, "MMDAT<3>"),
PXA_FUNCTION(1, 1, "MMDAT<3>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(112),
PXA_FUNCTION(0, 1, "MMCMD"),
PXA_FUNCTION(0, 2, "nMSINS"),
PXA_FUNCTION(1, 1, "MMCMD")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(113),
PXA_FUNCTION(0, 3, "USB_P3_3"),
PXA_FUNCTION(1, 1, "I2S_SYSCLK"),
PXA_FUNCTION(1, 2, "AC97_RESET_n")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(114),
PXA_FUNCTION(0, 1, "CIF_DD<1>"),
PXA_FUNCTION(1, 1, "UEN"),
PXA_FUNCTION(1, 2, "UVS0")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(115),
PXA_FUNCTION(0, 1, "DREQ<0>"),
PXA_FUNCTION(0, 2, "CIF_DD<3>"),
PXA_FUNCTION(0, 3, "MBREQ"),
PXA_FUNCTION(1, 1, "UEN"),
PXA_FUNCTION(1, 2, "nUVS1"),
PXA_FUNCTION(1, 3, "PWM_OUT<1>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(116),
PXA_FUNCTION(0, 1, "CIF_DD<2>"),
PXA_FUNCTION(0, 2, "AC97_SDATA_IN_0"),
PXA_FUNCTION(0, 3, "UDET"),
PXA_FUNCTION(1, 1, "DVAL<0>"),
PXA_FUNCTION(1, 2, "nUVS2"),
PXA_FUNCTION(1, 3, "MBGNT")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(117),
PXA_FUNCTION(0, 1, "SCL"),
PXA_FUNCTION(1, 1, "SCL")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(118),
PXA_FUNCTION(0, 1, "SDA"),
PXA_FUNCTION(1, 1, "SDA")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(119),
PXA_FUNCTION(0, 1, "USBHPWR<2>")),
PXA_GPIO_PIN(PXA_PINCTRL_PIN(120),
PXA_FUNCTION(1, 2, "USBHPEN<2>")),
};
static int pxa27x_pinctrl_probe(struct platform_device *pdev)
{
int ret, i;
void __iomem *base_af[8];
void __iomem *base_dir[4];
void __iomem *base_sleep[4];
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_af[0] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base_af[0]))
return PTR_ERR(base_af[0]);
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
base_dir[0] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base_dir[0]))
return PTR_ERR(base_dir[0]);
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
base_dir[3] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base_dir[3]))
return PTR_ERR(base_dir[3]);
res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
base_sleep[0] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base_sleep[0]))
return PTR_ERR(base_sleep[0]);
for (i = 0; i < ARRAY_SIZE(base_af); i++)
base_af[i] = base_af[0] + sizeof(base_af[0]) * i;
for (i = 0; i < 3; i++)
base_dir[i] = base_dir[0] + sizeof(base_dir[0]) * i;
for (i = 0; i < ARRAY_SIZE(base_sleep); i++)
base_sleep[i] = base_sleep[0] + sizeof(base_af[0]) * i;
ret = pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins),
base_af, base_dir, base_sleep);
return ret;
}
static const struct of_device_id pxa27x_pinctrl_match[] = {
{ .compatible = "marvell,pxa27x-pinctrl", },
{}
};
MODULE_DEVICE_TABLE(of, pxa27x_pinctrl_match);
static struct platform_driver pxa27x_pinctrl_driver = {
.probe = pxa27x_pinctrl_probe,
.driver = {
.name = "pxa27x-pinctrl",
.of_match_table = pxa27x_pinctrl_match,
},
};
module_platform_driver(pxa27x_pinctrl_driver);
MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
MODULE_DESCRIPTION("Marvell PXA27x pinctrl driver");
MODULE_LICENSE("GPL v2");

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drivers/pinctrl/pxa/pinctrl-pxa2xx.c Normal file
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/*
* Marvell PXA2xx family pin control
*
* Copyright (C) 2015 Robert Jarzmik
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
*/
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/module.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "../pinctrl-utils.h"
#include "pinctrl-pxa2xx.h"
static int pxa2xx_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->ngroups;
}
static const char *pxa2xx_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned tgroup)
{
struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pxa_pinctrl_group *group = pctl->groups + tgroup;
return group->name;
}
static int pxa2xx_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned tgroup,
const unsigned **pins,
unsigned *num_pins)
{
struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pxa_pinctrl_group *group = pctl->groups + tgroup;
*pins = (unsigned *)&group->pin;
*num_pins = 1;
return 0;
}
static const struct pinctrl_ops pxa2xx_pctl_ops = {
#ifdef CONFIG_OF
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_dt_free_map,
#endif
.get_groups_count = pxa2xx_pctrl_get_groups_count,
.get_group_name = pxa2xx_pctrl_get_group_name,
.get_group_pins = pxa2xx_pctrl_get_group_pins,
};
static struct pxa_desc_function *
pxa_desc_by_func_group(struct pxa_pinctrl *pctl, const char *pin_name,
const char *func_name)
{
int i;
struct pxa_desc_function *df;
for (i = 0; i < pctl->npins; i++) {
const struct pxa_desc_pin *pin = pctl->ppins + i;
if (!strcmp(pin->pin.name, pin_name))
for (df = pin->functions; df->name; df++)
if (!strcmp(df->name, func_name))
return df;
}
return NULL;
}
static int pxa2xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned pin,
bool input)
{
struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
uint32_t val;
void __iomem *gpdr;
gpdr = pctl->base_gpdr[pin / 32];
dev_dbg(pctl->dev, "set_direction(pin=%d): dir=%d\n",
pin, !input);
spin_lock_irqsave(&pctl->lock, flags);
val = readl_relaxed(gpdr);
val = (val & ~BIT(pin % 32)) | (input ? 0 : BIT(pin % 32));
writel_relaxed(val, gpdr);
spin_unlock_irqrestore(&pctl->lock, flags);
return 0;
}
static const char *pxa2xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned function)
{
struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pxa_pinctrl_function *pf = pctl->functions + function;
return pf->name;
}
static int pxa2xx_get_functions_count(struct pinctrl_dev *pctldev)
{
struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->nfuncs;
}
static int pxa2xx_pmx_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function,
const char * const **groups,
unsigned * const num_groups)
{
struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pxa_pinctrl_function *pf = pctl->functions + function;
*groups = pf->groups;
*num_groups = pf->ngroups;
return 0;
}
static int pxa2xx_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned function,
unsigned tgroup)
{
struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pxa_pinctrl_group *group = pctl->groups + tgroup;
struct pxa_desc_function *df;
int pin, shift;
unsigned long flags;
void __iomem *gafr, *gpdr;
u32 val;
df = pxa_desc_by_func_group(pctl, group->name,
(pctl->functions + function)->name);
if (!df)
return -EINVAL;
pin = group->pin;
gafr = pctl->base_gafr[pin / 16];
gpdr = pctl->base_gpdr[pin / 32];
shift = (pin % 16) << 1;
dev_dbg(pctl->dev, "set_mux(pin=%d): af=%d dir=%d\n",
pin, df->muxval >> 1, df->muxval & 0x1);
spin_lock_irqsave(&pctl->lock, flags);
val = readl_relaxed(gafr);
val = (val & ~(0x3 << shift)) | ((df->muxval >> 1) << shift);
writel_relaxed(val, gafr);
val = readl_relaxed(gpdr);
val = (val & ~BIT(pin % 32)) | ((df->muxval & 1) ? BIT(pin % 32) : 0);
writel_relaxed(val, gpdr);
spin_unlock_irqrestore(&pctl->lock, flags);
return 0;
}
static const struct pinmux_ops pxa2xx_pinmux_ops = {
.get_functions_count = pxa2xx_get_functions_count,
.get_function_name = pxa2xx_pmx_get_func_name,
.get_function_groups = pxa2xx_pmx_get_func_groups,
.set_mux = pxa2xx_pmx_set_mux,
.gpio_set_direction = pxa2xx_pmx_gpio_set_direction,
};
static int pxa2xx_pconf_group_get(struct pinctrl_dev *pctldev,
unsigned group,
unsigned long *config)
{
struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pxa_pinctrl_group *g = pctl->groups + group;
unsigned long flags;
unsigned pin = g->pin;
void __iomem *pgsr = pctl->base_pgsr[pin / 32];
u32 val;
spin_lock_irqsave(&pctl->lock, flags);
val = readl_relaxed(pgsr) & BIT(pin % 32);
*config = val ? PIN_CONFIG_LOW_POWER_MODE : 0;
spin_unlock_irqrestore(&pctl->lock, flags);
dev_dbg(pctl->dev, "get sleep gpio state(pin=%d) %d\n",
pin, !!val);
return 0;
}
static int pxa2xx_pconf_group_set(struct pinctrl_dev *pctldev,
unsigned group,
unsigned long *configs,
unsigned num_configs)
{
struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pxa_pinctrl_group *g = pctl->groups + group;
unsigned long flags;
unsigned pin = g->pin;
void __iomem *pgsr = pctl->base_pgsr[pin / 32];
int i, is_set = 0;
u32 val;
for (i = 0; i < num_configs; i++) {
switch (pinconf_to_config_param(configs[i])) {
case PIN_CONFIG_LOW_POWER_MODE:
is_set = pinconf_to_config_argument(configs[i]);
break;
default:
return -EINVAL;
}
}
dev_dbg(pctl->dev, "set sleep gpio state(pin=%d) %d\n",
pin, is_set);
spin_lock_irqsave(&pctl->lock, flags);
val = readl_relaxed(pgsr);
val = (val & ~BIT(pin % 32)) | (is_set ? BIT(pin % 32) : 0);
writel_relaxed(val, pgsr);
spin_unlock_irqrestore(&pctl->lock, flags);
return 0;
}
static const struct pinconf_ops pxa2xx_pconf_ops = {
.pin_config_group_get = pxa2xx_pconf_group_get,
.pin_config_group_set = pxa2xx_pconf_group_set,
.is_generic = true,
};
static struct pinctrl_desc pxa2xx_pinctrl_desc = {
.confops = &pxa2xx_pconf_ops,
.pctlops = &pxa2xx_pctl_ops,
.pmxops = &pxa2xx_pinmux_ops,
};
static const struct pxa_pinctrl_function *
pxa2xx_find_function(struct pxa_pinctrl *pctl, const char *fname,
const struct pxa_pinctrl_function *functions)
{
const struct pxa_pinctrl_function *func;
for (func = functions; func->name; func++)
if (!strcmp(fname, func->name))
return func;
return NULL;
}
static int pxa2xx_build_functions(struct pxa_pinctrl *pctl)
{
int i;
struct pxa_pinctrl_function *functions;
struct pxa_desc_function *df;
/*
* Each pin can have at most 6 alternate functions, and 2 gpio functions
* which are common to each pin. As there are more than 2 pins without
* alternate function, 6 * npins is an absolute high limit of the number
* of functions.
*/
functions = devm_kcalloc(pctl->dev, pctl->npins * 6,
sizeof(*functions), GFP_KERNEL);
if (!functions)
return -ENOMEM;
for (i = 0; i < pctl->npins; i++)
for (df = pctl->ppins[i].functions; df->name; df++)
if (!pxa2xx_find_function(pctl, df->name, functions))
(functions + pctl->nfuncs++)->name = df->name;
pctl->functions = devm_kmemdup(pctl->dev, functions,
pctl->nfuncs * sizeof(*functions),
GFP_KERNEL);
if (!pctl->functions)
return -ENOMEM;
devm_kfree(pctl->dev, functions);
return 0;
}
static int pxa2xx_build_groups(struct pxa_pinctrl *pctl)
{
int i, j, ngroups;
struct pxa_pinctrl_function *func;
struct pxa_desc_function *df;
char **gtmp;
gtmp = devm_kmalloc_array(pctl->dev, pctl->npins, sizeof(*gtmp),
GFP_KERNEL);
if (!gtmp)
return -ENOMEM;
for (i = 0; i < pctl->nfuncs; i++) {
ngroups = 0;
for (j = 0; j < pctl->npins; j++)
for (df = pctl->ppins[j].functions; df->name;
df++)
if (!strcmp(pctl->functions[i].name,
df->name))
gtmp[ngroups++] = (char *)
pctl->ppins[j].pin.name;
func = pctl->functions + i;
func->ngroups = ngroups;
func->groups =
devm_kmalloc_array(pctl->dev, ngroups,
sizeof(char *), GFP_KERNEL);
if (!func->groups)
return -ENOMEM;
memcpy(func->groups, gtmp, ngroups * sizeof(*gtmp));
}
devm_kfree(pctl->dev, gtmp);
return 0;
}
static int pxa2xx_build_state(struct pxa_pinctrl *pctl,
const struct pxa_desc_pin *ppins, int npins)
{
struct pxa_pinctrl_group *group;
struct pinctrl_pin_desc *pins;
int ret, i;
pctl->npins = npins;
pctl->ppins = ppins;
pctl->ngroups = npins;
pctl->desc.npins = npins;
pins = devm_kcalloc(pctl->dev, npins, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
pctl->desc.pins = pins;
for (i = 0; i < npins; i++)
pins[i] = ppins[i].pin;
pctl->groups = devm_kmalloc_array(pctl->dev, pctl->ngroups,
sizeof(*pctl->groups), GFP_KERNEL);
if (!pctl->groups)
return -ENOMEM;
for (i = 0; i < npins; i++) {
group = pctl->groups + i;
group->name = ppins[i].pin.name;
group->pin = ppins[i].pin.number;
}
ret = pxa2xx_build_functions(pctl);
if (ret)
return ret;
ret = pxa2xx_build_groups(pctl);
if (ret)
return ret;
return 0;
}
int pxa2xx_pinctrl_init(struct platform_device *pdev,
const struct pxa_desc_pin *ppins, int npins,
void __iomem *base_gafr[], void __iomem *base_gpdr[],
void __iomem *base_pgsr[])
{
struct pxa_pinctrl *pctl;
int ret, i, maxpin = 0;
for (i = 0; i < npins; i++)
maxpin = max_t(int, ppins[i].pin.number, maxpin);
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
pctl->base_gafr = devm_kcalloc(&pdev->dev, roundup(maxpin, 16),
sizeof(*pctl->base_gafr), GFP_KERNEL);
pctl->base_gpdr = devm_kcalloc(&pdev->dev, roundup(maxpin, 32),
sizeof(*pctl->base_gpdr), GFP_KERNEL);
pctl->base_pgsr = devm_kcalloc(&pdev->dev, roundup(maxpin, 32),
sizeof(*pctl->base_pgsr), GFP_KERNEL);
if (!pctl->base_gafr || !pctl->base_gpdr || !pctl->base_pgsr)
return -ENOMEM;
platform_set_drvdata(pdev, pctl);
spin_lock_init(&pctl->lock);
pctl->dev = &pdev->dev;
pctl->desc = pxa2xx_pinctrl_desc;
pctl->desc.name = dev_name(&pdev->dev);
pctl->desc.owner = THIS_MODULE;
for (i = 0; i < roundup(maxpin, 16); i += 16)
pctl->base_gafr[i / 16] = base_gafr[i / 16];
for (i = 0; i < roundup(maxpin, 32); i += 32) {
pctl->base_gpdr[i / 32] = base_gpdr[i / 32];
pctl->base_pgsr[i / 32] = base_pgsr[i / 32];
}
ret = pxa2xx_build_state(pctl, ppins, npins);
if (ret)
return ret;
pctl->pctl_dev = pinctrl_register(&pctl->desc, &pdev->dev, pctl);
if (IS_ERR(pctl->pctl_dev)) {
dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
return PTR_ERR(pctl->pctl_dev);
}
dev_info(&pdev->dev, "initialized pxa2xx pinctrl driver\n");
return 0;
}
int pxa2xx_pinctrl_exit(struct platform_device *pdev)
{
struct pxa_pinctrl *pctl = platform_get_drvdata(pdev);
pinctrl_unregister(pctl->pctl_dev);
return 0;
}

92
drivers/pinctrl/pxa/pinctrl-pxa2xx.h Normal file
View File

@ -0,0 +1,92 @@
/*
* Marvell PXA2xx family pin control
*
* Copyright (C) 2015 Robert Jarzmik
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
*/
#ifndef __PINCTRL_PXA_H
#define __PINCTRL_PXA_H
#define PXA_FUNCTION(_dir, _af, _name) \
{ \
.name = _name, \
.muxval = (_dir | (_af << 1)), \
}
#define PXA_PIN(_pin, funcs...) \
{ \
.pin = _pin, \
.functions = (struct pxa_desc_function[]){ \
funcs, { } }, \
}
#define PXA_GPIO_PIN(_pin, funcs...) \
{ \
.pin = _pin, \
.functions = (struct pxa_desc_function[]){ \
PXA_FUNCTION(0, 0, "gpio_in"), \
PXA_FUNCTION(1, 0, "gpio_out"), \
funcs, { } }, \
}
#define PXA_GPIO_ONLY_PIN(_pin) \
{ \
.pin = _pin, \
.functions = (struct pxa_desc_function[]){ \
PXA_FUNCTION(0, 0, "gpio_in"), \
PXA_FUNCTION(1, 0, "gpio_out"), \
{ } }, \
}
#define PXA_PINCTRL_PIN(pin) \
PINCTRL_PIN(pin, "P" #pin)
struct pxa_desc_function {
const char *name;
u8 muxval;
};
struct pxa_desc_pin {
struct pinctrl_pin_desc pin;
struct pxa_desc_function *functions;
};
struct pxa_pinctrl_group {
const char *name;
unsigned pin;
};
struct pxa_pinctrl_function {
const char *name;
const char **groups;
unsigned ngroups;
};
struct pxa_pinctrl {
spinlock_t lock;
void __iomem **base_gafr;
void __iomem **base_gpdr;
void __iomem **base_pgsr;
struct device *dev;
struct pinctrl_desc desc;
struct pinctrl_dev *pctl_dev;
unsigned npins;
const struct pxa_desc_pin *ppins;
unsigned ngroups;
struct pxa_pinctrl_group *groups;
unsigned nfuncs;
struct pxa_pinctrl_function *functions;
char *name;
};
int pxa2xx_pinctrl_init(struct platform_device *pdev,
const struct pxa_desc_pin *ppins, int npins,
void __iomem *base_gafr[], void __iomem *base_gpdr[],
void __iomem *base_gpsr[]);
#endif /* __PINCTRL_PXA_H */

8
drivers/pinctrl/qcom/Kconfig
View File

@ -63,6 +63,14 @@ config PINCTRL_MSM8916
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm 8916 platform.
config PINCTRL_MSM8996
tristate "Qualcomm MSM8996 pin controller driver"
depends on GPIOLIB && OF
select PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm MSM8996 platform.
config PINCTRL_QDF2XXX
tristate "Qualcomm Technologies QDF2xxx pin controller driver"
depends on GPIOLIB && ACPI

1
drivers/pinctrl/qcom/Makefile
View File

@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o
obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o

1942
drivers/pinctrl/qcom/pinctrl-msm8996.c Normal file
View File

File diff suppressed because it is too large Load Diff

16
drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
View File

@ -32,6 +32,9 @@
static struct msm_pinctrl_soc_data qdf2xxx_pinctrl;
/* A reasonable limit to the number of GPIOS */
#define MAX_GPIOS 256
static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
{
struct pinctrl_pin_desc *pins;
@ -42,11 +45,13 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
/* Query the number of GPIOs from ACPI */
ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
if (ret < 0)
return ret;
if (!num_gpios) {
if (ret < 0) {
dev_warn(&pdev->dev, "missing num-gpios property\n");
return ret;
}
if (!num_gpios || num_gpios > MAX_GPIOS) {
dev_warn(&pdev->dev, "invalid num-gpios property\n");
return -ENODEV;
}
@ -55,6 +60,9 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
groups = devm_kcalloc(&pdev->dev, num_gpios,
sizeof(struct msm_pingroup), GFP_KERNEL);
if (!pins || !groups)
return -ENOMEM;
for (i = 0; i < num_gpios; i++) {
pins[i].number = i;

15
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View File

@ -14,6 +14,7 @@
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
@ -693,18 +694,19 @@ static int pmic_gpio_probe(struct platform_device *pdev)
struct pmic_gpio_pad *pad, *pads;
struct pmic_gpio_state *state;
int ret, npins, i;
u32 res[2];
u32 reg;
ret = of_property_read_u32_array(dev->of_node, "reg", res, 2);
ret = of_property_read_u32(dev->of_node, "reg", &reg);
if (ret < 0) {
dev_err(dev, "missing base address and/or range");
dev_err(dev, "missing base address");
return ret;
}
npins = res[1] / PMIC_GPIO_ADDRESS_RANGE;
npins = platform_irq_count(pdev);
if (!npins)
return -EINVAL;
if (npins < 0)
return npins;
BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
@ -752,7 +754,7 @@ static int pmic_gpio_probe(struct platform_device *pdev)
if (pad->irq < 0)
return pad->irq;
pad->base = res[0] + i * PMIC_GPIO_ADDRESS_RANGE;
pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
ret = pmic_gpio_populate(state, pad);
if (ret < 0)
@ -804,6 +806,7 @@ static int pmic_gpio_remove(struct platform_device *pdev)
static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */
{ .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
{ .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
{ .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
{ },
};

14
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
View File

@ -14,6 +14,7 @@
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
@ -795,17 +796,19 @@ static int pmic_mpp_probe(struct platform_device *pdev)
struct pmic_mpp_pad *pad, *pads;
struct pmic_mpp_state *state;
int ret, npins, i;
u32 res[2];
u32 reg;
ret = of_property_read_u32_array(dev->of_node, "reg", res, 2);
ret = of_property_read_u32(dev->of_node, "reg", &reg);
if (ret < 0) {
dev_err(dev, "missing base address and/or range");
dev_err(dev, "missing base address");
return ret;
}
npins = res[1] / PMIC_MPP_ADDRESS_RANGE;
npins = platform_irq_count(pdev);
if (!npins)
return -EINVAL;
if (npins < 0)
return npins;
BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups));
@ -854,7 +857,7 @@ static int pmic_mpp_probe(struct platform_device *pdev)
if (pad->irq < 0)
return pad->irq;
pad->base = res[0] + i * PMIC_MPP_ADDRESS_RANGE;
pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE;
ret = pmic_mpp_populate(state, pad);
if (ret < 0)
@ -907,6 +910,7 @@ static const struct of_device_id pmic_mpp_of_match[] = {
{ .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */
{ .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */
{ .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */
{ .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */
{ .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */
{ },
};

21
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
View File

@ -23,6 +23,7 @@
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
@ -650,11 +651,12 @@ static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl,
}
static const struct of_device_id pm8xxx_gpio_of_match[] = {
{ .compatible = "qcom,pm8018-gpio", .data = (void *)6 },
{ .compatible = "qcom,pm8038-gpio", .data = (void *)12 },
{ .compatible = "qcom,pm8058-gpio", .data = (void *)40 },
{ .compatible = "qcom,pm8917-gpio", .data = (void *)38 },
{ .compatible = "qcom,pm8921-gpio", .data = (void *)44 },
{ .compatible = "qcom,pm8018-gpio" },
{ .compatible = "qcom,pm8038-gpio" },
{ .compatible = "qcom,pm8058-gpio" },
{ .compatible = "qcom,pm8917-gpio" },
{ .compatible = "qcom,pm8921-gpio" },
{ .compatible = "qcom,ssbi-gpio" },
{ },
};
MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match);
@ -665,14 +667,19 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev)
struct pinctrl_pin_desc *pins;
struct pm8xxx_gpio *pctrl;
int ret;
int i;
int i, npins;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->dev = &pdev->dev;
pctrl->npins = (unsigned long)of_device_get_match_data(&pdev->dev);
npins = platform_irq_count(pdev);
if (!npins)
return -EINVAL;
if (npins < 0)
return npins;
pctrl->npins = npins;
pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!pctrl->regmap) {

21
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
View File

@ -23,6 +23,7 @@
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
@ -741,11 +742,12 @@ static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl,
}
static const struct of_device_id pm8xxx_mpp_of_match[] = {
{ .compatible = "qcom,pm8018-mpp", .data = (void *)6 },
{ .compatible = "qcom,pm8038-mpp", .data = (void *)6 },
{ .compatible = "qcom,pm8917-mpp", .data = (void *)10 },
{ .compatible = "qcom,pm8821-mpp", .data = (void *)4 },
{ .compatible = "qcom,pm8921-mpp", .data = (void *)12 },
{ .compatible = "qcom,pm8018-mpp" },
{ .compatible = "qcom,pm8038-mpp" },
{ .compatible = "qcom,pm8917-mpp" },
{ .compatible = "qcom,pm8821-mpp" },
{ .compatible = "qcom,pm8921-mpp" },
{ .compatible = "qcom,ssbi-mpp" },
{ },
};
MODULE_DEVICE_TABLE(of, pm8xxx_mpp_of_match);
@ -756,14 +758,19 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev)
struct pinctrl_pin_desc *pins;
struct pm8xxx_mpp *pctrl;
int ret;
int i;
int i, npins;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->dev = &pdev->dev;
pctrl->npins = (unsigned long)of_device_get_match_data(&pdev->dev);
npins = platform_irq_count(pdev);
if (!npins)
return -EINVAL;
if (npins < 0)
return npins;
pctrl->npins = npins;
pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!pctrl->regmap) {

103
drivers/pinctrl/samsung/pinctrl-exynos.c
View File

@ -1150,6 +1150,109 @@ const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
},
};
/* pin banks of exynos5410 pin-controller 0 */
static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
};
/* pin banks of exynos5410 pin-controller 1 */
static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
};
/* pin banks of exynos5410 pin-controller 2 */
static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
};
/* pin banks of exynos5410 pin-controller 3 */
static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
};
/*
* Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
* four gpio/pin-mux/pinconfig controllers.
*/
const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 data */
.pin_banks = exynos5410_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos5410_pin_banks0),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos5410_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos5410_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
}, {
/* pin-controller instance 2 data */
.pin_banks = exynos5410_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos5410_pin_banks2),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
}, {
/* pin-controller instance 3 data */
.pin_banks = exynos5410_pin_banks3,
.nr_banks = ARRAY_SIZE(exynos5410_pin_banks3),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
},
};
/* pin banks of exynos5420 pin-controller 0 */
static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),

2
drivers/pinctrl/samsung/pinctrl-samsung.c
View File

@ -1222,6 +1222,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = (void *)exynos5250_pin_ctrl },
{ .compatible = "samsung,exynos5260-pinctrl",
.data = (void *)exynos5260_pin_ctrl },
{ .compatible = "samsung,exynos5410-pinctrl",
.data = (void *)exynos5410_pin_ctrl },
{ .compatible = "samsung,exynos5420-pinctrl",
.data = (void *)exynos5420_pin_ctrl },
{ .compatible = "samsung,exynos5433-pinctrl",

1
drivers/pinctrl/samsung/pinctrl-samsung.h
View File

@ -270,6 +270,7 @@ extern const struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
extern const struct samsung_pin_ctrl exynos4415_pin_ctrl[];
extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[];
extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[];
extern const struct samsung_pin_ctrl exynos5410_pin_ctrl[];
extern const struct samsung_pin_ctrl exynos5420_pin_ctrl[];
extern const struct samsung_pin_ctrl exynos5433_pin_ctrl[];
extern const struct samsung_pin_ctrl exynos7_pin_ctrl[];

136
drivers/pinctrl/sh-pfc/pfc-emev2.c
View File

@ -258,18 +258,18 @@ static const u16 pinmux_data[] = {
/* GPSR0 */
/* V9 */
PINMUX_DATA(JT_SEL_MARK, FN_JT_SEL),
PINMUX_SINGLE(JT_SEL),
/* U9 */
PINMUX_DATA(ERR_RST_REQB_MARK, FN_ERR_RST_REQB),
PINMUX_SINGLE(ERR_RST_REQB),
/* V8 */
PINMUX_DATA(REF_CLKO_MARK, FN_REF_CLKO),
PINMUX_SINGLE(REF_CLKO),
/* U8 */
PINMUX_DATA(EXT_CLKI_MARK, FN_EXT_CLKI),
PINMUX_SINGLE(EXT_CLKI),
/* B22*/
PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, LCD3_PXCLK, SEL_LCD3_1_0_00),
PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, YUV3_CLK_O, SEL_LCD3_1_0_01),
/* C21 */
PINMUX_DATA(LCD3_PXCLKB_MARK, FN_LCD3_PXCLKB),
PINMUX_SINGLE(LCD3_PXCLKB),
/* A21 */
PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, LCD3_CLK_I, SEL_LCD3_1_0_00),
PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, YUV3_CLK_I, SEL_LCD3_1_0_01),
@ -285,17 +285,17 @@ static const u16 pinmux_data[] = {
/* GPSR1 */
/* A20 */
PINMUX_DATA(LCD3_R0_MARK, FN_LCD3_R0),
PINMUX_SINGLE(LCD3_R0),
/* B20 */
PINMUX_DATA(LCD3_R1_MARK, FN_LCD3_R1),
PINMUX_SINGLE(LCD3_R1),
/* A19 */
PINMUX_DATA(LCD3_R2_MARK, FN_LCD3_R2),
PINMUX_SINGLE(LCD3_R2),
/* B19 */
PINMUX_DATA(LCD3_R3_MARK, FN_LCD3_R3),
PINMUX_SINGLE(LCD3_R3),
/* C19 */
PINMUX_DATA(LCD3_R4_MARK, FN_LCD3_R4),
PINMUX_SINGLE(LCD3_R4),
/* B18 */
PINMUX_DATA(LCD3_R5_MARK, FN_LCD3_R5),
PINMUX_SINGLE(LCD3_R5),
/* C18 */
PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, LCD3_R6, SEL_LCD3_9_8_00),
PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, TP33_CLK, SEL_LCD3_9_8_10),
@ -367,9 +367,9 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D15, SEL_LCD3_11_10_01),
PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA15, SEL_LCD3_11_10_10),
/* AA9 */
PINMUX_DATA(IIC0_SCL_MARK, FN_IIC0_SCL),
PINMUX_SINGLE(IIC0_SCL),
/* AA8 */
PINMUX_DATA(IIC0_SDA_MARK, FN_IIC0_SDA),
PINMUX_SINGLE(IIC0_SDA),
/* Y9 */
PINMUX_IPSR_NOFN(IIC_1_0_PORT46, IIC1_SCL, SEL_IIC_1_0_00),
PINMUX_IPSR_NOFN(IIC_1_0_PORT46, UART3_RX, SEL_IIC_1_0_01),
@ -377,51 +377,51 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_NOFN(IIC_1_0_PORT47, IIC1_SDA, SEL_IIC_1_0_00),
PINMUX_IPSR_NOFN(IIC_1_0_PORT47, UART3_TX, SEL_IIC_1_0_01),
/* AC19 */
PINMUX_DATA(SD_CKI_MARK, FN_SD_CKI),
PINMUX_SINGLE(SD_CKI),
/* AB18 */
PINMUX_DATA(SDI0_CKO_MARK, FN_SDI0_CKO),
PINMUX_SINGLE(SDI0_CKO),
/* AC18 */
PINMUX_DATA(SDI0_CKI_MARK, FN_SDI0_CKI),
PINMUX_SINGLE(SDI0_CKI),
/* Y12 */
PINMUX_DATA(SDI0_CMD_MARK, FN_SDI0_CMD),
PINMUX_SINGLE(SDI0_CMD),
/* AA13 */
PINMUX_DATA(SDI0_DATA0_MARK, FN_SDI0_DATA0),
PINMUX_SINGLE(SDI0_DATA0),
/* Y13 */
PINMUX_DATA(SDI0_DATA1_MARK, FN_SDI0_DATA1),
PINMUX_SINGLE(SDI0_DATA1),
/* AA14 */
PINMUX_DATA(SDI0_DATA2_MARK, FN_SDI0_DATA2),
PINMUX_SINGLE(SDI0_DATA2),
/* Y14 */
PINMUX_DATA(SDI0_DATA3_MARK, FN_SDI0_DATA3),
PINMUX_SINGLE(SDI0_DATA3),
/* AA15 */
PINMUX_DATA(SDI0_DATA4_MARK, FN_SDI0_DATA4),
PINMUX_SINGLE(SDI0_DATA4),
/* Y15 */
PINMUX_DATA(SDI0_DATA5_MARK, FN_SDI0_DATA5),
PINMUX_SINGLE(SDI0_DATA5),
/* AA16 */
PINMUX_DATA(SDI0_DATA6_MARK, FN_SDI0_DATA6),
PINMUX_SINGLE(SDI0_DATA6),
/* Y16 */
PINMUX_DATA(SDI0_DATA7_MARK, FN_SDI0_DATA7),
PINMUX_SINGLE(SDI0_DATA7),
/* AB22 */
PINMUX_DATA(SDI1_CKO_MARK, FN_SDI1_CKO),
PINMUX_SINGLE(SDI1_CKO),
/* AA23 */
PINMUX_DATA(SDI1_CKI_MARK, FN_SDI1_CKI),
PINMUX_SINGLE(SDI1_CKI),
/* AC21 */
PINMUX_DATA(SDI1_CMD_MARK, FN_SDI1_CMD),
PINMUX_SINGLE(SDI1_CMD),
/* GPSR2 */
/* AB21 */
PINMUX_DATA(SDI1_DATA0_MARK, FN_SDI1_DATA0),
PINMUX_SINGLE(SDI1_DATA0),
/* AB20 */
PINMUX_DATA(SDI1_DATA1_MARK, FN_SDI1_DATA1),
PINMUX_SINGLE(SDI1_DATA1),
/* AB19 */
PINMUX_DATA(SDI1_DATA2_MARK, FN_SDI1_DATA2),
PINMUX_SINGLE(SDI1_DATA2),
/* AA19 */
PINMUX_DATA(SDI1_DATA3_MARK, FN_SDI1_DATA3),
PINMUX_SINGLE(SDI1_DATA3),
/* J23 */
PINMUX_DATA(AB_CLK_MARK, FN_AB_CLK),
PINMUX_SINGLE(AB_CLK),
/* D21 */
PINMUX_DATA(AB_CSB0_MARK, FN_AB_CSB0),
PINMUX_SINGLE(AB_CSB0),
/* E21 */
PINMUX_DATA(AB_CSB1_MARK, FN_AB_CSB1),
PINMUX_SINGLE(AB_CSB1),
/* F20 */
PINMUX_IPSR_NOFN(AB_1_0_PORT71, AB_CSB2, SEL_AB_1_0_00),
PINMUX_IPSR_NOFN(AB_1_0_PORT71, CF_CSB0, SEL_AB_1_0_10),
@ -514,7 +514,7 @@ static const u16 pinmux_data[] = {
/* GPSR3 */
/* M21 */
PINMUX_DATA(AB_A20_MARK, FN_AB_A20),
PINMUX_SINGLE(AB_A20),
/* N21 */
PINMUX_IPSR_NOFN(AB_9_8_PORT97, AB_A21, SEL_AB_9_8_00),
PINMUX_IPSR_NOFN(AB_9_8_PORT97, SDI2_CKO, SEL_AB_9_8_01),
@ -541,13 +541,13 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_A28, SEL_AB_13_12_00),
PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_BEN1, SEL_AB_13_12_10),
/* B8 */
PINMUX_DATA(USI0_CS1_MARK, FN_USI0_CS1),
PINMUX_SINGLE(USI0_CS1),
/* B9 */
PINMUX_DATA(USI0_CS2_MARK, FN_USI0_CS2),
PINMUX_SINGLE(USI0_CS2),
/* C10 */
PINMUX_DATA(USI1_DI_MARK, FN_USI1_DI),
PINMUX_SINGLE(USI1_DI),
/* D10 */
PINMUX_DATA(USI1_DO_MARK, FN_USI1_DO),
PINMUX_SINGLE(USI1_DO),
/* AB5 */
PINMUX_IPSR_NOFN(USI_1_0_PORT109, USI2_CLK, SEL_USI_1_0_00),
PINMUX_IPSR_NOFN(USI_1_0_PORT109, DTV_BCLK_B, SEL_USI_1_0_01),
@ -587,49 +587,49 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_NOFN(USI_9_8_PORT121, PWM1, SEL_USI_9_8_00),
PINMUX_IPSR_NOFN(USI_9_8_PORT121, USI4_DO, SEL_USI_9_8_01),
/* V20 */
PINMUX_DATA(NTSC_CLK_MARK, FN_NTSC_CLK),
PINMUX_SINGLE(NTSC_CLK),
/* P20 */
PINMUX_DATA(NTSC_DATA0_MARK, FN_NTSC_DATA0),
PINMUX_SINGLE(NTSC_DATA0),
/* P18 */
PINMUX_DATA(NTSC_DATA1_MARK, FN_NTSC_DATA1),
PINMUX_SINGLE(NTSC_DATA1),
/* R20 */
PINMUX_DATA(NTSC_DATA2_MARK, FN_NTSC_DATA2),
PINMUX_SINGLE(NTSC_DATA2),
/* R18 */
PINMUX_DATA(NTSC_DATA3_MARK, FN_NTSC_DATA3),
PINMUX_SINGLE(NTSC_DATA3),
/* T20 */
PINMUX_DATA(NTSC_DATA4_MARK, FN_NTSC_DATA4),
PINMUX_SINGLE(NTSC_DATA4),
/* GPRS3 */
/* T18 */
PINMUX_DATA(NTSC_DATA5_MARK, FN_NTSC_DATA5),
PINMUX_SINGLE(NTSC_DATA5),
/* U20 */
PINMUX_DATA(NTSC_DATA6_MARK, FN_NTSC_DATA6),
PINMUX_SINGLE(NTSC_DATA6),
/* U18 */
PINMUX_DATA(NTSC_DATA7_MARK, FN_NTSC_DATA7),
PINMUX_SINGLE(NTSC_DATA7),
/* W23 */
PINMUX_DATA(CAM_CLKO_MARK, FN_CAM_CLKO),
PINMUX_SINGLE(CAM_CLKO),
/* Y23 */
PINMUX_DATA(CAM_CLKI_MARK, FN_CAM_CLKI),
PINMUX_SINGLE(CAM_CLKI),
/* W22 */
PINMUX_DATA(CAM_VS_MARK, FN_CAM_VS),
PINMUX_SINGLE(CAM_VS),
/* V21 */
PINMUX_DATA(CAM_HS_MARK, FN_CAM_HS),
PINMUX_SINGLE(CAM_HS),
/* T21 */
PINMUX_DATA(CAM_YUV0_MARK, FN_CAM_YUV0),
PINMUX_SINGLE(CAM_YUV0),
/* T22 */
PINMUX_DATA(CAM_YUV1_MARK, FN_CAM_YUV1),
PINMUX_SINGLE(CAM_YUV1),
/* T23 */
PINMUX_DATA(CAM_YUV2_MARK, FN_CAM_YUV2),
PINMUX_SINGLE(CAM_YUV2),
/* U21 */
PINMUX_DATA(CAM_YUV3_MARK, FN_CAM_YUV3),
PINMUX_SINGLE(CAM_YUV3),
/* U22 */
PINMUX_DATA(CAM_YUV4_MARK, FN_CAM_YUV4),
PINMUX_SINGLE(CAM_YUV4),
/* U23 */
PINMUX_DATA(CAM_YUV5_MARK, FN_CAM_YUV5),
PINMUX_SINGLE(CAM_YUV5),
/* V22 */
PINMUX_DATA(CAM_YUV6_MARK, FN_CAM_YUV6),
PINMUX_SINGLE(CAM_YUV6),
/* V23 */
PINMUX_DATA(CAM_YUV7_MARK, FN_CAM_YUV7),
PINMUX_SINGLE(CAM_YUV7),
/* K22 */
PINMUX_IPSR_NOFN(HSI_1_0_PORT143, USI5_CLK_B, SEL_HSI_1_0_01),
/* K23 */
@ -647,17 +647,17 @@ static const u16 pinmux_data[] = {
/* M22 */
PINMUX_IPSR_NOFN(HSI_1_0_PORT150, USI5_DI_B, SEL_HSI_1_0_01),
/* D13 */
PINMUX_DATA(JT_TDO_MARK, FN_JT_TDO),
PINMUX_SINGLE(JT_TDO),
/* F13 */
PINMUX_DATA(JT_TDOEN_MARK, FN_JT_TDOEN),
PINMUX_SINGLE(JT_TDOEN),
/* AA12 */
PINMUX_DATA(USB_VBUS_MARK, FN_USB_VBUS),
PINMUX_SINGLE(USB_VBUS),
/* A12 */
PINMUX_DATA(LOWPWR_MARK, FN_LOWPWR),
PINMUX_SINGLE(LOWPWR),
/* Y11 */
PINMUX_DATA(UART1_RX_MARK, FN_UART1_RX),
PINMUX_SINGLE(UART1_RX),
/* Y10 */
PINMUX_DATA(UART1_TX_MARK, FN_UART1_TX),
PINMUX_SINGLE(UART1_TX),
/* AA10 */
PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART1_CTSB, SEL_UART_1_0_00),
PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART2_RX, SEL_UART_1_0_01),
@ -749,7 +749,7 @@ static const unsigned int cf_ctrl_mux[] = {
};
static const unsigned int cf_data8_pins[] = {
/* CF_D[0:8] */
/* CF_D[0:7] */
77, 78, 79, 80,
81, 82, 83, 84,
};

2
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View File

@ -2214,7 +2214,7 @@ static const unsigned int lcd1_data9_mux[] = {
LCD1_D8_MARK,
};
static const unsigned int lcd1_data12_pins[] = {
/* D[0:12] */
/* D[0:11] */
4, 3, 2, 1, 0, 91, 92, 23,
93, 94, 21, 201,
};

22
drivers/pinctrl/sh-pfc/pfc-r8a7778.c
View File

@ -548,17 +548,17 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(PENC0_MARK, FN_PENC0),
PINMUX_DATA(PENC1_MARK, FN_PENC1),
PINMUX_DATA(A1_MARK, FN_A1),
PINMUX_DATA(A2_MARK, FN_A2),
PINMUX_DATA(A3_MARK, FN_A3),
PINMUX_DATA(WE0_MARK, FN_WE0),
PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
PINMUX_DATA(AUDIO_CLKB_MARK, FN_AUDIO_CLKB),
PINMUX_DATA(SSI_SCK34_MARK, FN_SSI_SCK34),
PINMUX_DATA(AVS1_MARK, FN_AVS1),
PINMUX_DATA(AVS2_MARK, FN_AVS2),
PINMUX_SINGLE(PENC0),
PINMUX_SINGLE(PENC1),
PINMUX_SINGLE(A1),
PINMUX_SINGLE(A2),
PINMUX_SINGLE(A3),
PINMUX_SINGLE(WE0),
PINMUX_SINGLE(AUDIO_CLKA),
PINMUX_SINGLE(AUDIO_CLKB),
PINMUX_SINGLE(SSI_SCK34),
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
/* IPSR0 */
PINMUX_IPSR_DATA(IP0_1_0, PRESETOUT),

62
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
View File

@ -23,13 +23,6 @@
#include "sh_pfc.h"
#define PORT_GP_9(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
@ -609,14 +602,14 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(AVS1_MARK, FN_AVS1),
PINMUX_DATA(AVS1_MARK, FN_AVS1),
PINMUX_DATA(A17_MARK, FN_A17),
PINMUX_DATA(A18_MARK, FN_A18),
PINMUX_DATA(A19_MARK, FN_A19),
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(A17),
PINMUX_SINGLE(A18),
PINMUX_SINGLE(A19),
PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0),
PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
PINMUX_SINGLE(USB_PENC0),
PINMUX_SINGLE(USB_PENC1),
PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0),
@ -2289,6 +2282,35 @@ static const unsigned int scif5_clk_d_pins[] = {
static const unsigned int scif5_clk_d_mux[] = {
SCK5_D_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(4, 28),
};
static const unsigned int scif_clk_mux[] = {
SCIF_CLK_MARK,
};
static const unsigned int scif_clk_b_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(4, 5),
};
static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
static const unsigned int scif_clk_c_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(4, 18),
};
static const unsigned int scif_clk_c_mux[] = {
SCIF_CLK_C_MARK,
};
static const unsigned int scif_clk_d_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(2, 29),
};
static const unsigned int scif_clk_d_mux[] = {
SCIF_CLK_D_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
@ -2700,6 +2722,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif5_clk_c),
SH_PFC_PIN_GROUP(scif5_data_d),
SH_PFC_PIN_GROUP(scif5_clk_d),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(scif_clk_c),
SH_PFC_PIN_GROUP(scif_clk_d),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
@ -2909,6 +2935,13 @@ static const char * const scif5_groups[] = {
"scif5_clk_d",
};
static const char * const scif_clk_groups[] = {
"scif_clk",
"scif_clk_b",
"scif_clk_c",
"scif_clk_d",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
@ -3004,6 +3037,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif5),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),

58
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
View File

@ -26,23 +26,6 @@
#include "core.h"
#include "sh_pfc.h"
#define PORT_GP_30(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_30(1, fn, sfx), \
@ -806,15 +789,15 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
PINMUX_DATA(AVS1_MARK, FN_AVS1),
PINMUX_DATA(AVS2_MARK, FN_AVS2),
PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
PINMUX_SINGLE(VI1_DATA7_VI1_B7),
PINMUX_SINGLE(USB0_PWEN),
PINMUX_SINGLE(USB0_OVC_VBUS),
PINMUX_SINGLE(USB2_PWEN),
PINMUX_SINGLE(USB2_OVC),
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(DU_DOTCLKIN0),
PINMUX_SINGLE(DU_DOTCLKIN2),
PINMUX_IPSR_DATA(IP0_2_0, D0),
PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
@ -3236,6 +3219,21 @@ static const unsigned int scifb2_data_c_pins[] = {
static const unsigned int scifb2_data_c_mux[] = {
SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(4, 26),
};
static const unsigned int scif_clk_mux[] = {
SCIF_CLK_MARK,
};
static const unsigned int scif_clk_b_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(5, 4),
};
static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
@ -4139,6 +4137,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb2_clk_b),
SH_PFC_PIN_GROUP(scifb2_ctrl_b),
SH_PFC_PIN_GROUP(scifb2_data_c),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
@ -4555,6 +4555,11 @@ static const char * const scifb2_groups[] = {
"scifb2_data_c",
};
static const char * const scif_clk_groups[] = {
"scif_clk",
"scif_clk_b",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
@ -4729,6 +4734,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scifb0),
SH_PFC_FUNCTION(scifb1),
SH_PFC_FUNCTION(scifb2),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),

167
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
View File

@ -2,6 +2,7 @@
* r8a7791 processor support - PFC hardware block.
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2014-2015 Cogent Embedded, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
@ -13,21 +14,6 @@
#include "core.h"
#include "sh_pfc.h"
#define PORT_GP_26(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_26(1, fn, sfx), \
@ -787,23 +773,23 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
PINMUX_DATA(RD_N_MARK, FN_RD_N),
PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1),
PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2),
PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4),
PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5),
PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6),
PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7),
PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN),
PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
PINMUX_SINGLE(EX_CS0_N),
PINMUX_SINGLE(RD_N),
PINMUX_SINGLE(AUDIO_CLKA),
PINMUX_SINGLE(VI0_CLK),
PINMUX_SINGLE(VI0_DATA0_VI0_B0),
PINMUX_SINGLE(VI0_DATA1_VI0_B1),
PINMUX_SINGLE(VI0_DATA2_VI0_B2),
PINMUX_SINGLE(VI0_DATA4_VI0_B4),
PINMUX_SINGLE(VI0_DATA5_VI0_B5),
PINMUX_SINGLE(VI0_DATA6_VI0_B6),
PINMUX_SINGLE(VI0_DATA7_VI0_B7),
PINMUX_SINGLE(USB0_PWEN),
PINMUX_SINGLE(USB0_OVC),
PINMUX_SINGLE(USB1_PWEN),
PINMUX_SINGLE(USB1_OVC),
PINMUX_SINGLE(DU0_DOTCLKIN),
PINMUX_SINGLE(SD1_CLK),
/* IPSR0 */
PINMUX_IPSR_DATA(IP0_0, D0),
@ -1740,6 +1726,82 @@ static const unsigned int audio_clkout_mux[] = {
AUDIO_CLKOUT_MARK,
};
/* - AVB -------------------------------------------------------------------- */
static const unsigned int avb_link_pins[] = {
RCAR_GP_PIN(5, 14),
};
static const unsigned int avb_link_mux[] = {
AVB_LINK_MARK,
};
static const unsigned int avb_magic_pins[] = {
RCAR_GP_PIN(5, 11),
};
static const unsigned int avb_magic_mux[] = {
AVB_MAGIC_MARK,
};
static const unsigned int avb_phy_int_pins[] = {
RCAR_GP_PIN(5, 16),
};
static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
static const unsigned int avb_mdio_pins[] = {
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
};
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
};
static const unsigned int avb_mii_pins[] = {
RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
RCAR_GP_PIN(5, 21),
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
RCAR_GP_PIN(5, 3),
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
};
static const unsigned int avb_mii_mux[] = {
AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
AVB_TXD3_MARK,
AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
AVB_RXD3_MARK,
AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
AVB_TX_CLK_MARK, AVB_COL_MARK,
};
static const unsigned int avb_gmii_pins[] = {
RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
RCAR_GP_PIN(5, 29),
};
static const unsigned int avb_gmii_mux[] = {
AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
AVB_TXD6_MARK, AVB_TXD7_MARK,
AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
AVB_RXD6_MARK, AVB_RXD7_MARK,
AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
AVB_COL_MARK,
};
/* - CAN -------------------------------------------------------------------- */
static const unsigned int can0_data_pins[] = {
@ -3602,6 +3664,23 @@ static const unsigned int scifb2_data_d_pins[] = {
static const unsigned int scifb2_data_d_mux[] = {
SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(2, 29),
};
static const unsigned int scif_clk_mux[] = {
SCIF_CLK_MARK,
};
static const unsigned int scif_clk_b_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(7, 19),
};
static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
@ -4258,6 +4337,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_b_b),
SH_PFC_PIN_GROUP(audio_clk_c),
SH_PFC_PIN_GROUP(audio_clkout),
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_gmii),
SH_PFC_PIN_GROUP(can0_data),
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can0_data_c),
@ -4510,6 +4595,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb2_data_c),
SH_PFC_PIN_GROUP(scifb2_clk_c),
SH_PFC_PIN_GROUP(scifb2_data_d),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
@ -4597,6 +4684,15 @@ static const char * const audio_clk_groups[] = {
"audio_clkout",
};
static const char * const avb_groups[] = {
"avb_link",
"avb_magic",
"avb_phy_int",
"avb_mdio",
"avb_mii",
"avb_gmii",
};
static const char * const can0_groups[] = {
"can0_data",
"can0_data_b",
@ -4976,6 +5072,11 @@ static const char * const scifb2_groups[] = {
"scifb2_data_d",
};
static const char * const scif_clk_groups[] = {
"scif_clk",
"scif_clk_b",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
@ -5081,6 +5182,7 @@ static const char * const vin2_groups[] = {
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(du),
@ -5126,6 +5228,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scifb0),
SH_PFC_FUNCTION(scifb1),
SH_PFC_FUNCTION(scifb2),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),

86
drivers/pinctrl/sh-pfc/pfc-r8a7794.c
View File

@ -15,25 +15,6 @@
#include "core.h"
#include "sh_pfc.h"
#define PORT_GP_26(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
#define PORT_GP_28(bank, fn, sfx) \
PORT_GP_26(bank, fn, sfx), \
PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_26(1, fn, sfx), \
@ -618,28 +599,28 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(A2_MARK, FN_A2),
PINMUX_DATA(WE0_N_MARK, FN_WE0_N),
PINMUX_DATA(WE1_N_MARK, FN_WE1_N),
PINMUX_DATA(DACK0_MARK, FN_DACK0),
PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0),
PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1),
PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2),
PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3),
PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD),
PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0),
PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1),
PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
PINMUX_SINGLE(A2),
PINMUX_SINGLE(WE0_N),
PINMUX_SINGLE(WE1_N),
PINMUX_SINGLE(DACK0),
PINMUX_SINGLE(USB0_PWEN),
PINMUX_SINGLE(USB0_OVC),
PINMUX_SINGLE(USB1_PWEN),
PINMUX_SINGLE(USB1_OVC),
PINMUX_SINGLE(SD0_CLK),
PINMUX_SINGLE(SD0_CMD),
PINMUX_SINGLE(SD0_DATA0),
PINMUX_SINGLE(SD0_DATA1),
PINMUX_SINGLE(SD0_DATA2),
PINMUX_SINGLE(SD0_DATA3),
PINMUX_SINGLE(SD0_CD),
PINMUX_SINGLE(SD0_WP),
PINMUX_SINGLE(SD1_CLK),
PINMUX_SINGLE(SD1_CMD),
PINMUX_SINGLE(SD1_DATA0),
PINMUX_SINGLE(SD1_DATA1),
PINMUX_SINGLE(SD1_DATA2),
PINMUX_SINGLE(SD1_DATA3),
/* IPSR0 */
PINMUX_IPSR_DATA(IP0_0, SD1_CD),
@ -2644,6 +2625,21 @@ static const unsigned int scifb2_ctrl_pins[] = {
static const unsigned int scifb2_ctrl_mux[] = {
SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(1, 23),
};
static const unsigned int scif_clk_mux[] = {
SCIF_CLK_MARK,
};
static const unsigned int scif_clk_b_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(3, 29),
};
static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
@ -3071,6 +3067,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scifb2_data),
SH_PFC_PIN_GROUP(scifb2_clk),
SH_PFC_PIN_GROUP(scifb2_ctrl),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
@ -3354,6 +3352,11 @@ static const char * const scifb2_groups[] = {
"scifb2_ctrl",
};
static const char * const scif_clk_groups[] = {
"scif_clk",
"scif_clk_b",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
@ -3441,6 +3444,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scifb0),
SH_PFC_FUNCTION(scifb1),
SH_PFC_FUNCTION(scifb2),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),

1505
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
View File

File diff suppressed because it is too large Load Diff

548
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
View File

@ -2059,7 +2059,7 @@ static const unsigned int lcd2_data9_mux[] = {
LCD2D8_MARK,
};
static const unsigned int lcd2_data12_pins[] = {
/* D[0:12] */
/* D[0:11] */
128, 129, 142, 143, 144, 145, 138, 139,
140, 141, 130, 131,
};
@ -2198,6 +2198,420 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
static const unsigned int mmc0_ctrl_1_mux[] = {
MMCCMD1_MARK, MMCCLK1_MARK,
};
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_rsck_pins[] = {
/* RSCK */
66,
};
static const unsigned int msiof0_rsck_mux[] = {
MSIOF0_RSCK_MARK,
};
static const unsigned int msiof0_tsck_pins[] = {
/* TSCK */
64,
};
static const unsigned int msiof0_tsck_mux[] = {
MSIOF0_TSCK_MARK,
};
static const unsigned int msiof0_rsync_pins[] = {
/* RSYNC */
67,
};
static const unsigned int msiof0_rsync_mux[] = {
MSIOF0_RSYNC_MARK,
};
static const unsigned int msiof0_tsync_pins[] = {
/* TSYNC */
63,
};
static const unsigned int msiof0_tsync_mux[] = {
MSIOF0_TSYNC_MARK,
};
static const unsigned int msiof0_ss1_pins[] = {
/* SS1 */
62,
};
static const unsigned int msiof0_ss1_mux[] = {
MSIOF0_SS1_MARK,
};
static const unsigned int msiof0_ss2_pins[] = {
/* SS2 */
71,
};
static const unsigned int msiof0_ss2_mux[] = {
MSIOF0_SS2_MARK,
};
static const unsigned int msiof0_rxd_pins[] = {
/* RXD */
70,
};
static const unsigned int msiof0_rxd_mux[] = {
MSIOF0_RXD_MARK,
};
static const unsigned int msiof0_txd_pins[] = {
/* TXD */
65,
};
static const unsigned int msiof0_txd_mux[] = {
MSIOF0_TXD_MARK,
};
static const unsigned int msiof0_mck0_pins[] = {
/* MSCK0 */
68,
};
static const unsigned int msiof0_mck0_mux[] = {
MSIOF0_MCK0_MARK,
};
static const unsigned int msiof0_mck1_pins[] = {
/* MSCK1 */
69,
};
static const unsigned int msiof0_mck1_mux[] = {
MSIOF0_MCK1_MARK,
};
static const unsigned int msiof0l_rsck_pins[] = {
/* RSCK */
214,
};
static const unsigned int msiof0l_rsck_mux[] = {
MSIOF0L_RSCK_MARK,
};
static const unsigned int msiof0l_tsck_pins[] = {
/* TSCK */
219,
};
static const unsigned int msiof0l_tsck_mux[] = {
MSIOF0L_TSCK_MARK,
};
static const unsigned int msiof0l_rsync_pins[] = {
/* RSYNC */
215,
};
static const unsigned int msiof0l_rsync_mux[] = {
MSIOF0L_RSYNC_MARK,
};
static const unsigned int msiof0l_tsync_pins[] = {
/* TSYNC */
217,
};
static const unsigned int msiof0l_tsync_mux[] = {
MSIOF0L_TSYNC_MARK,
};
static const unsigned int msiof0l_ss1_a_pins[] = {
/* SS1 */
207,
};
static const unsigned int msiof0l_ss1_a_mux[] = {
PORT207_MSIOF0L_SS1_MARK,
};
static const unsigned int msiof0l_ss1_b_pins[] = {
/* SS1 */
210,
};
static const unsigned int msiof0l_ss1_b_mux[] = {
PORT210_MSIOF0L_SS1_MARK,
};
static const unsigned int msiof0l_ss2_a_pins[] = {
/* SS2 */
208,
};
static const unsigned int msiof0l_ss2_a_mux[] = {
PORT208_MSIOF0L_SS2_MARK,
};
static const unsigned int msiof0l_ss2_b_pins[] = {
/* SS2 */
211,
};
static const unsigned int msiof0l_ss2_b_mux[] = {
PORT211_MSIOF0L_SS2_MARK,
};
static const unsigned int msiof0l_rxd_pins[] = {
/* RXD */
221,
};
static const unsigned int msiof0l_rxd_mux[] = {
MSIOF0L_RXD_MARK,
};
static const unsigned int msiof0l_txd_pins[] = {
/* TXD */
222,
};
static const unsigned int msiof0l_txd_mux[] = {
MSIOF0L_TXD_MARK,
};
static const unsigned int msiof0l_mck0_pins[] = {
/* MSCK0 */
212,
};
static const unsigned int msiof0l_mck0_mux[] = {
MSIOF0L_MCK0_MARK,
};
static const unsigned int msiof0l_mck1_pins[] = {
/* MSCK1 */
213,
};
static const unsigned int msiof0l_mck1_mux[] = {
MSIOF0L_MCK1_MARK,
};
/* - MSIOF1 ----------------------------------------------------------------- */
static const unsigned int msiof1_rsck_pins[] = {
/* RSCK */
234,
};
static const unsigned int msiof1_rsck_mux[] = {
MSIOF1_RSCK_MARK,
};
static const unsigned int msiof1_tsck_pins[] = {
/* TSCK */
232,
};
static const unsigned int msiof1_tsck_mux[] = {
MSIOF1_TSCK_MARK,
};
static const unsigned int msiof1_rsync_pins[] = {
/* RSYNC */
235,
};
static const unsigned int msiof1_rsync_mux[] = {
MSIOF1_RSYNC_MARK,
};
static const unsigned int msiof1_tsync_pins[] = {
/* TSYNC */
231,
};
static const unsigned int msiof1_tsync_mux[] = {
MSIOF1_TSYNC_MARK,
};
static const unsigned int msiof1_ss1_pins[] = {
/* SS1 */
238,
};
static const unsigned int msiof1_ss1_mux[] = {
MSIOF1_SS1_MARK,
};
static const unsigned int msiof1_ss2_pins[] = {
/* SS2 */
239,
};
static const unsigned int msiof1_ss2_mux[] = {
MSIOF1_SS2_MARK,
};
static const unsigned int msiof1_rxd_pins[] = {
/* RXD */
233,
};
static const unsigned int msiof1_rxd_mux[] = {
MSIOF1_RXD_MARK,
};
static const unsigned int msiof1_txd_pins[] = {
/* TXD */
230,
};
static const unsigned int msiof1_txd_mux[] = {
MSIOF1_TXD_MARK,
};
static const unsigned int msiof1_mck0_pins[] = {
/* MSCK0 */
236,
};
static const unsigned int msiof1_mck0_mux[] = {
MSIOF1_MCK0_MARK,
};
static const unsigned int msiof1_mck1_pins[] = {
/* MSCK1 */
237,
};
static const unsigned int msiof1_mck1_mux[] = {
MSIOF1_MCK1_MARK,
};
/* - MSIOF2 ----------------------------------------------------------------- */
static const unsigned int msiof2_rsck_pins[] = {
/* RSCK */
151,
};
static const unsigned int msiof2_rsck_mux[] = {
MSIOF2_RSCK_MARK,
};
static const unsigned int msiof2_tsck_pins[] = {
/* TSCK */
135,
};
static const unsigned int msiof2_tsck_mux[] = {
MSIOF2_TSCK_MARK,
};
static const unsigned int msiof2_rsync_pins[] = {
/* RSYNC */
152,
};
static const unsigned int msiof2_rsync_mux[] = {
MSIOF2_RSYNC_MARK,
};
static const unsigned int msiof2_tsync_pins[] = {
/* TSYNC */
133,
};
static const unsigned int msiof2_tsync_mux[] = {
MSIOF2_TSYNC_MARK,
};
static const unsigned int msiof2_ss1_a_pins[] = {
/* SS1 */
131,
};
static const unsigned int msiof2_ss1_a_mux[] = {
PORT131_MSIOF2_SS1_MARK,
};
static const unsigned int msiof2_ss1_b_pins[] = {
/* SS1 */
153,
};
static const unsigned int msiof2_ss1_b_mux[] = {
PORT153_MSIOF2_SS1_MARK,
};
static const unsigned int msiof2_ss2_a_pins[] = {
/* SS2 */
132,
};
static const unsigned int msiof2_ss2_a_mux[] = {
PORT132_MSIOF2_SS2_MARK,
};
static const unsigned int msiof2_ss2_b_pins[] = {
/* SS2 */
156,
};
static const unsigned int msiof2_ss2_b_mux[] = {
PORT156_MSIOF2_SS2_MARK,
};
static const unsigned int msiof2_rxd_a_pins[] = {
/* RXD */
130,
};
static const unsigned int msiof2_rxd_a_mux[] = {
PORT130_MSIOF2_RXD_MARK,
};
static const unsigned int msiof2_rxd_b_pins[] = {
/* RXD */
157,
};
static const unsigned int msiof2_rxd_b_mux[] = {
PORT157_MSIOF2_RXD_MARK,
};
static const unsigned int msiof2_txd_pins[] = {
/* TXD */
134,
};
static const unsigned int msiof2_txd_mux[] = {
MSIOF2_TXD_MARK,
};
static const unsigned int msiof2_mck0_pins[] = {
/* MSCK0 */
154,
};
static const unsigned int msiof2_mck0_mux[] = {
MSIOF2_MCK0_MARK,
};
static const unsigned int msiof2_mck1_pins[] = {
/* MSCK1 */
155,
};
static const unsigned int msiof2_mck1_mux[] = {
MSIOF2_MCK1_MARK,
};
static const unsigned int msiof2r_tsck_pins[] = {
/* TSCK */
248,
};
static const unsigned int msiof2r_tsck_mux[] = {
MSIOF2R_TSCK_MARK,
};
static const unsigned int msiof2r_tsync_pins[] = {
/* TSYNC */
249,
};
static const unsigned int msiof2r_tsync_mux[] = {
MSIOF2R_TSYNC_MARK,
};
static const unsigned int msiof2r_rxd_pins[] = {
/* RXD */
244,
};
static const unsigned int msiof2r_rxd_mux[] = {
MSIOF2R_RXD_MARK,
};
static const unsigned int msiof2r_txd_pins[] = {
/* TXD */
245,
};
static const unsigned int msiof2r_txd_mux[] = {
MSIOF2R_TXD_MARK,
};
/* - MSIOF3 (Pin function name of MSIOF3 is named BBIF1) -------------------- */
static const unsigned int msiof3_rsck_pins[] = {
/* RSCK */
115,
};
static const unsigned int msiof3_rsck_mux[] = {
BBIF1_RSCK_MARK,
};
static const unsigned int msiof3_tsck_pins[] = {
/* TSCK */
112,
};
static const unsigned int msiof3_tsck_mux[] = {
BBIF1_TSCK_MARK,
};
static const unsigned int msiof3_rsync_pins[] = {
/* RSYNC */
116,
};
static const unsigned int msiof3_rsync_mux[] = {
BBIF1_RSYNC_MARK,
};
static const unsigned int msiof3_tsync_pins[] = {
/* TSYNC */
113,
};
static const unsigned int msiof3_tsync_mux[] = {
BBIF1_TSYNC_MARK,
};
static const unsigned int msiof3_ss1_pins[] = {
/* SS1 */
117,
};
static const unsigned int msiof3_ss1_mux[] = {
BBIF1_SS1_MARK,
};
static const unsigned int msiof3_ss2_pins[] = {
/* SS2 */
109,
};
static const unsigned int msiof3_ss2_mux[] = {
BBIF1_SS2_MARK,
};
static const unsigned int msiof3_rxd_pins[] = {
/* RXD */
111,
};
static const unsigned int msiof3_rxd_mux[] = {
BBIF1_RXD_MARK,
};
static const unsigned int msiof3_txd_pins[] = {
/* TXD */
114,
};
static const unsigned int msiof3_txd_mux[] = {
BBIF1_TXD_MARK,
};
static const unsigned int msiof3_flow_pins[] = {
/* FLOW */
117,
};
static const unsigned int msiof3_flow_mux[] = {
BBIF1_FLOW_MARK,
};
/* - SCIFA0 ----------------------------------------------------------------- */
static const unsigned int scifa0_data_pins[] = {
/* RXD, TXD */
@ -2782,6 +3196,64 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(mmc0_data4_1),
SH_PFC_PIN_GROUP(mmc0_data8_1),
SH_PFC_PIN_GROUP(mmc0_ctrl_1),
SH_PFC_PIN_GROUP(msiof0_rsck),
SH_PFC_PIN_GROUP(msiof0_tsck),
SH_PFC_PIN_GROUP(msiof0_rsync),
SH_PFC_PIN_GROUP(msiof0_tsync),
SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(msiof0_ss2),
SH_PFC_PIN_GROUP(msiof0_rxd),
SH_PFC_PIN_GROUP(msiof0_txd),
SH_PFC_PIN_GROUP(msiof0_mck0),
SH_PFC_PIN_GROUP(msiof0_mck1),
SH_PFC_PIN_GROUP(msiof0l_rsck),
SH_PFC_PIN_GROUP(msiof0l_tsck),
SH_PFC_PIN_GROUP(msiof0l_rsync),
SH_PFC_PIN_GROUP(msiof0l_tsync),
SH_PFC_PIN_GROUP(msiof0l_ss1_a),
SH_PFC_PIN_GROUP(msiof0l_ss1_b),
SH_PFC_PIN_GROUP(msiof0l_ss2_a),
SH_PFC_PIN_GROUP(msiof0l_ss2_b),
SH_PFC_PIN_GROUP(msiof0l_rxd),
SH_PFC_PIN_GROUP(msiof0l_txd),
SH_PFC_PIN_GROUP(msiof0l_mck0),
SH_PFC_PIN_GROUP(msiof0l_mck1),
SH_PFC_PIN_GROUP(msiof1_rsck),
SH_PFC_PIN_GROUP(msiof1_tsck),
SH_PFC_PIN_GROUP(msiof1_rsync),
SH_PFC_PIN_GROUP(msiof1_tsync),
SH_PFC_PIN_GROUP(msiof1_ss1),
SH_PFC_PIN_GROUP(msiof1_ss2),
SH_PFC_PIN_GROUP(msiof1_rxd),
SH_PFC_PIN_GROUP(msiof1_txd),
SH_PFC_PIN_GROUP(msiof1_mck0),
SH_PFC_PIN_GROUP(msiof1_mck1),
SH_PFC_PIN_GROUP(msiof2_rsck),
SH_PFC_PIN_GROUP(msiof2_tsck),
SH_PFC_PIN_GROUP(msiof2_rsync),
SH_PFC_PIN_GROUP(msiof2_tsync),
SH_PFC_PIN_GROUP(msiof2_ss1_a),
SH_PFC_PIN_GROUP(msiof2_ss1_b),
SH_PFC_PIN_GROUP(msiof2_ss2_a),
SH_PFC_PIN_GROUP(msiof2_ss2_b),
SH_PFC_PIN_GROUP(msiof2_rxd_a),
SH_PFC_PIN_GROUP(msiof2_rxd_b),
SH_PFC_PIN_GROUP(msiof2_txd),
SH_PFC_PIN_GROUP(msiof2_mck0),
SH_PFC_PIN_GROUP(msiof2_mck1),
SH_PFC_PIN_GROUP(msiof2r_tsck),
SH_PFC_PIN_GROUP(msiof2r_tsync),
SH_PFC_PIN_GROUP(msiof2r_rxd),
SH_PFC_PIN_GROUP(msiof2r_txd),
SH_PFC_PIN_GROUP(msiof3_rsck),
SH_PFC_PIN_GROUP(msiof3_tsck),
SH_PFC_PIN_GROUP(msiof3_rsync),
SH_PFC_PIN_GROUP(msiof3_tsync),
SH_PFC_PIN_GROUP(msiof3_ss1),
SH_PFC_PIN_GROUP(msiof3_ss2),
SH_PFC_PIN_GROUP(msiof3_rxd),
SH_PFC_PIN_GROUP(msiof3_txd),
SH_PFC_PIN_GROUP(msiof3_flow),
SH_PFC_PIN_GROUP(scifa0_data),
SH_PFC_PIN_GROUP(scifa0_clk),
SH_PFC_PIN_GROUP(scifa0_ctrl),
@ -2982,6 +3454,76 @@ static const char * const mmc0_groups[] = {
"mmc0_ctrl_1",
};
static const char * const msiof0_groups[] = {
"msiof0_rsck",
"msiof0_tsck",
"msiof0_rsync",
"msiof0_tsync",
"msiof0_ss1",
"msiof0_ss2",
"msiof0_rxd",
"msiof0_txd",
"msiof0_mck0",
"msiof0_mck1",
"msiof0l_rsck",
"msiof0l_tsck",
"msiof0l_rsync",
"msiof0l_tsync",
"msiof0l_ss1_a",
"msiof0l_ss1_b",
"msiof0l_ss2_a",
"msiof0l_ss2_b",
"msiof0l_rxd",
"msiof0l_txd",
"msiof0l_mck0",
"msiof0l_mck1",
};
static const char * const msiof1_groups[] = {
"msiof1_rsck",
"msiof1_tsck",
"msiof1_rsync",
"msiof1_tsync",
"msiof1_ss1",
"msiof1_ss2",
"msiof1_rxd",
"msiof1_txd",
"msiof1_mck0",
"msiof1_mck1",
};
static const char * const msiof2_groups[] = {
"msiof2_rsck",
"msiof2_tsck",
"msiof2_rsync",
"msiof2_tsync",
"msiof2_ss1_a",
"msiof2_ss1_b",
"msiof2_ss2_a",
"msiof2_ss2_b",
"msiof2_rxd_a",
"msiof2_rxd_b",
"msiof2_txd",
"msiof2_mck0",
"msiof2_mck1",
"msiof2r_tsck",
"msiof2r_tsync",
"msiof2r_rxd",
"msiof2r_txd",
};
static const char * const msiof3_groups[] = {
"msiof3_rsck",
"msiof3_tsck",
"msiof3_rsync",
"msiof3_tsync",
"msiof3_ss1",
"msiof3_ss2",
"msiof3_rxd",
"msiof3_txd",
"msiof3_flow",
};
static const char * const scifa0_groups[] = {
"scifa0_data",
"scifa0_clk",
@ -3116,6 +3658,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(lcd),
SH_PFC_FUNCTION(lcd2),
SH_PFC_FUNCTION(mmc0),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
SH_PFC_FUNCTION(scifa0),
SH_PFC_FUNCTION(scifa1),
SH_PFC_FUNCTION(scifa2),

29
drivers/pinctrl/sh-pfc/pfc-sh7734.c
View File

@ -14,14 +14,6 @@
#include "sh_pfc.h"
#define PORT_GP_12(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
@ -585,15 +577,18 @@ enum {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT),
PINMUX_DATA(BS_MARK, FN_BS), PINMUX_DATA(CS0_MARK, FN_CS0),
PINMUX_DATA(EX_CS0_MARK, FN_EX_CS0),
PINMUX_DATA(RD_MARK, FN_RD), PINMUX_DATA(WE0_MARK, FN_WE0),
PINMUX_DATA(WE1_MARK, FN_WE1),
PINMUX_DATA(SCL0_MARK, FN_SCL0), PINMUX_DATA(PENC0_MARK, FN_PENC0),
PINMUX_DATA(USB_OVC0_MARK, FN_USB_OVC0),
PINMUX_DATA(IRQ2_B_MARK, FN_IRQ2_B),
PINMUX_DATA(IRQ3_B_MARK, FN_IRQ3_B),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(BS),
PINMUX_SINGLE(CS0),
PINMUX_SINGLE(EX_CS0),
PINMUX_SINGLE(RD),
PINMUX_SINGLE(WE0),
PINMUX_SINGLE(WE1),
PINMUX_SINGLE(SCL0),
PINMUX_SINGLE(PENC0),
PINMUX_SINGLE(USB_OVC0),
PINMUX_SINGLE(IRQ2_B),
PINMUX_SINGLE(IRQ3_B),
/* IPSR0 */
PINMUX_IPSR_DATA(IP0_1_0, A0),

4
drivers/pinctrl/sh-pfc/pinctrl.c
View File

@ -273,8 +273,10 @@ static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
for_each_child_of_node(np, child) {
ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps,
&index);
if (ret < 0)
if (ret < 0) {
of_node_put(child);
goto done;
}
}
/* If no mapping has been found in child nodes try the config node. */

74
drivers/pinctrl/sh-pfc/sh_pfc.h
View File

@ -198,6 +198,14 @@ struct sh_pfc_soc_info {
#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
/*
* Describe a pinmux configuration for a single-function pin with GPIO
* capability.
* - fn: Function name
*/
#define PINMUX_SINGLE(fn) \
PINMUX_DATA(fn##_MARK, FN_##fn)
/*
* GP port style (32 ports banks)
*/
@ -205,22 +213,68 @@ struct sh_pfc_soc_info {
#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
PORT_GP_CFG_8(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
PORT_GP_CFG_8(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 8, fn, sfx, cfg), PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
PORT_GP_CFG_12(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
PORT_GP_CFG_14(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
PORT_GP_CFG_14(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
PORT_GP_CFG_16(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
PORT_GP_CFG_26(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
PORT_GP_CFG_28(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
PORT_GP_CFG_30(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)

134
drivers/pinctrl/sirf/pinctrl-atlas7.c
View File

@ -161,6 +161,9 @@ enum altas7_pad_type {
#define IN_DISABLE_VAL_1_REG_SET 0x0A88
#define IN_DISABLE_VAL_1_REG_CLR 0x0A8C
/* Offset of the SDIO9SEL*/
#define SYS2PCI_SDIO9SEL 0x14
struct dt_params {
const char *property;
int value;
@ -370,6 +373,7 @@ struct atlas7_pmx {
struct pinctrl_desc pctl_desc;
struct atlas7_pinctrl_data *pctl_data;
void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
void __iomem *sys2pci_base;
u32 status_ds[NUM_OF_IN_DISABLE_REG];
u32 status_dsv[NUM_OF_IN_DISABLE_REG];
struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
@ -885,11 +889,12 @@ static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
155, 156, 157, 158, };
static const unsigned int nd_df_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37,
47, 46, 52, 51, 45, 49, 50, 48, 124, };
static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38,
37, 47, 46, 52, 51, 45, 49, 50, 48, };
static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38,
37, 47, 46, 52, 45, 49, 50, 48, };
static const unsigned int nd_df_wp_pins[] = { 124, };
static const unsigned int nd_df_cs_pins[] = { 51, };
static const unsigned int ps_pins[] = { 120, 119, 121, };
static const unsigned int ps_no_dir_pins[] = { 119, };
static const unsigned int pwc_core_on_pins[] = { 8, };
static const unsigned int pwc_ext_on_pins[] = { 6, };
static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
@ -944,7 +949,7 @@ static const unsigned int sd2_cdb_pins0[] = { 124, };
static const unsigned int sd2_cdb_pins1[] = { 161, };
static const unsigned int sd2_wpb_pins0[] = { 123, };
static const unsigned int sd2_wpb_pins1[] = { 163, };
static const unsigned int sd3_pins[] = { 85, 86, 87, 88, 89, 90, };
static const unsigned int sd3_9_pins[] = { 85, 86, 87, 88, 89, 90, };
static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
@ -998,9 +1003,9 @@ static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
99, 100, };
static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
80, 81, };
static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 108, 103,
104, 105, 106, };
80, 81, 82, 83, 84, };
static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104,
105, 106, 107, 102, 97, 98, };
/* definition of pin group table */
struct atlas7_pin_group altas7_pin_groups[] = {
@ -1142,9 +1147,11 @@ struct atlas7_pin_group altas7_pin_groups[] = {
GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
GROUP("lvds_analog_grp", lvds_analog_pins),
GROUP("nd_df_grp", nd_df_pins),
GROUP("nd_df_nowp_grp", nd_df_nowp_pins),
GROUP("nd_df_basic_grp", nd_df_basic_pins),
GROUP("nd_df_wp_grp", nd_df_wp_pins),
GROUP("nd_df_cs_grp", nd_df_cs_pins),
GROUP("ps_grp", ps_pins),
GROUP("ps_no_dir_grp", ps_no_dir_pins),
GROUP("pwc_core_on_grp", pwc_core_on_pins),
GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
@ -1196,7 +1203,7 @@ struct atlas7_pin_group altas7_pin_groups[] = {
GROUP("sd2_cdb_grp1", sd2_cdb_pins1),
GROUP("sd2_wpb_grp0", sd2_wpb_pins0),
GROUP("sd2_wpb_grp1", sd2_wpb_pins1),
GROUP("sd3_grp", sd3_pins),
GROUP("sd3_9_grp", sd3_9_pins),
GROUP("sd5_grp", sd5_pins),
GROUP("sd6_grp0", sd6_pins0),
GROUP("sd6_grp1", sd6_pins1),
@ -1421,9 +1428,11 @@ static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
static const char * const nd_df_grp[] = { "nd_df_grp", };
static const char * const nd_df_nowp_grp[] = { "nd_df_nowp_grp", };
static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", };
static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", };
static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", };
static const char * const ps_grp[] = { "ps_grp", };
static const char * const ps_no_dir_grp[] = { "ps_no_dir_grp", };
static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
@ -1478,7 +1487,7 @@ static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", };
static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", };
static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", };
static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", };
static const char * const sd3_grp[] = { "sd3_grp", };
static const char * const sd3_9_grp[] = { "sd3_9_grp", };
static const char * const sd5_grp[] = { "sd5_grp", };
static const char * const sd6_grp0[] = { "sd6_grp0", };
static const char * const sd6_grp1[] = { "sd6_grp1", };
@ -3174,7 +3183,7 @@ static struct atlas7_grp_mux lvds_analog_grp_mux = {
.pad_mux_list = lvds_analog_grp_pad_mux,
};
static struct atlas7_pad_mux nd_df_grp_pad_mux[] = {
static struct atlas7_pad_mux nd_df_basic_grp_pad_mux[] = {
MUX(1, 44, 1, N, N, N, N),
MUX(1, 43, 1, N, N, N, N),
MUX(1, 42, 1, N, N, N, N),
@ -3186,41 +3195,33 @@ static struct atlas7_pad_mux nd_df_grp_pad_mux[] = {
MUX(1, 47, 1, N, N, N, N),
MUX(1, 46, 1, N, N, N, N),
MUX(1, 52, 1, N, N, N, N),
MUX(1, 51, 1, N, N, N, N),
MUX(1, 45, 1, N, N, N, N),
MUX(1, 49, 1, N, N, N, N),
MUX(1, 50, 1, N, N, N, N),
MUX(1, 48, 1, N, N, N, N),
};
static struct atlas7_grp_mux nd_df_basic_grp_mux = {
.pad_mux_count = ARRAY_SIZE(nd_df_basic_grp_pad_mux),
.pad_mux_list = nd_df_basic_grp_pad_mux,
};
static struct atlas7_pad_mux nd_df_wp_grp_pad_mux[] = {
MUX(1, 124, 4, N, N, N, N),
};
static struct atlas7_grp_mux nd_df_grp_mux = {
.pad_mux_count = ARRAY_SIZE(nd_df_grp_pad_mux),
.pad_mux_list = nd_df_grp_pad_mux,
static struct atlas7_grp_mux nd_df_wp_grp_mux = {
.pad_mux_count = ARRAY_SIZE(nd_df_wp_grp_pad_mux),
.pad_mux_list = nd_df_wp_grp_pad_mux,
};
static struct atlas7_pad_mux nd_df_nowp_grp_pad_mux[] = {
MUX(1, 44, 1, N, N, N, N),
MUX(1, 43, 1, N, N, N, N),
MUX(1, 42, 1, N, N, N, N),
MUX(1, 41, 1, N, N, N, N),
MUX(1, 40, 1, N, N, N, N),
MUX(1, 39, 1, N, N, N, N),
MUX(1, 38, 1, N, N, N, N),
MUX(1, 37, 1, N, N, N, N),
MUX(1, 47, 1, N, N, N, N),
MUX(1, 46, 1, N, N, N, N),
MUX(1, 52, 1, N, N, N, N),
static struct atlas7_pad_mux nd_df_cs_grp_pad_mux[] = {
MUX(1, 51, 1, N, N, N, N),
MUX(1, 45, 1, N, N, N, N),
MUX(1, 49, 1, N, N, N, N),
MUX(1, 50, 1, N, N, N, N),
MUX(1, 48, 1, N, N, N, N),
};
static struct atlas7_grp_mux nd_df_nowp_grp_mux = {
.pad_mux_count = ARRAY_SIZE(nd_df_nowp_grp_pad_mux),
.pad_mux_list = nd_df_nowp_grp_pad_mux,
static struct atlas7_grp_mux nd_df_cs_grp_mux = {
.pad_mux_count = ARRAY_SIZE(nd_df_cs_grp_pad_mux),
.pad_mux_list = nd_df_cs_grp_pad_mux,
};
static struct atlas7_pad_mux ps_grp_pad_mux[] = {
@ -3234,6 +3235,15 @@ static struct atlas7_grp_mux ps_grp_mux = {
.pad_mux_list = ps_grp_pad_mux,
};
static struct atlas7_pad_mux ps_no_dir_grp_pad_mux[] = {
MUX(1, 119, 2, N, N, N, N),
};
static struct atlas7_grp_mux ps_no_dir_grp_mux = {
.pad_mux_count = ARRAY_SIZE(ps_no_dir_grp_pad_mux),
.pad_mux_list = ps_no_dir_grp_pad_mux,
};
static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
MUX(0, 8, 1, N, N, N, N),
};
@ -3743,7 +3753,7 @@ static struct atlas7_grp_mux sd2_wpb_grp1_mux = {
.pad_mux_list = sd2_wpb_grp1_pad_mux,
};
static struct atlas7_pad_mux sd3_grp_pad_mux[] = {
static struct atlas7_pad_mux sd3_9_grp_pad_mux[] = {
MUX(1, 85, 1, N, N, N, N),
MUX(1, 86, 1, N, N, N, N),
MUX(1, 87, 1, N, N, N, N),
@ -3752,9 +3762,9 @@ static struct atlas7_pad_mux sd3_grp_pad_mux[] = {
MUX(1, 90, 1, N, N, N, N),
};
static struct atlas7_grp_mux sd3_grp_mux = {
.pad_mux_count = ARRAY_SIZE(sd3_grp_pad_mux),
.pad_mux_list = sd3_grp_pad_mux,
static struct atlas7_grp_mux sd3_9_grp_mux = {
.pad_mux_count = ARRAY_SIZE(sd3_9_grp_pad_mux),
.pad_mux_list = sd3_9_grp_pad_mux,
};
static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
@ -4296,6 +4306,9 @@ static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
MUX(1, 79, 1, N, N, N, N),
MUX(1, 80, 1, N, N, N, N),
MUX(1, 81, 1, N, N, N, N),
MUX(1, 82, 1, N, N, N, N),
MUX(1, 83, 1, N, N, N, N),
MUX(1, 84, 1, N, N, N, N),
};
static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
@ -4307,11 +4320,14 @@ static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
MUX(1, 82, 1, N, N, N, N),
MUX(1, 83, 1, N, N, N, N),
MUX(1, 84, 1, N, N, N, N),
MUX(1, 108, 2, N, N, N, N),
MUX(1, 103, 2, N, N, N, N),
MUX(1, 104, 2, N, N, N, N),
MUX(1, 105, 2, N, N, N, N),
MUX(1, 106, 2, N, N, N, N),
MUX(1, 107, 2, N, N, N, N),
MUX(1, 102, 2, N, N, N, N),
MUX(1, 97, 2, N, N, N, N),
MUX(1, 98, 2, N, N, N, N),
};
static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
@ -4598,9 +4614,11 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = {
FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
FUNCTION("nd_df", nd_df_grp, &nd_df_grp_mux),
FUNCTION("nd_df_nowp", nd_df_nowp_grp, &nd_df_nowp_grp_mux),
FUNCTION("nd_df_basic", nd_df_basic_grp, &nd_df_basic_grp_mux),
FUNCTION("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux),
FUNCTION("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux),
FUNCTION("ps", ps_grp, &ps_grp_mux),
FUNCTION("ps_no_dir", ps_no_dir_grp, &ps_no_dir_grp_mux),
FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
@ -4686,10 +4704,11 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = {
FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux),
FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux),
FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux),
FUNCTION("sd3", sd3_grp, &sd3_grp_mux),
FUNCTION("sd3", sd3_9_grp, &sd3_9_grp_mux),
FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
FUNCTION("sd9", sd3_9_grp, &sd3_9_grp_mux),
FUNCTION("sp0_ext_ldo_on",
sp0_ext_ldo_on_grp,
&sp0_ext_ldo_on_grp_mux),
@ -5097,6 +5116,14 @@ static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n",
pmx_func->name, pin_grp->name);
/* the sd3 and sd9 pin select by SYS2PCI_SDIO9SEL register */
if (pin_grp->pins == (unsigned int *)&sd3_9_pins) {
if (!strcmp(pmx_func->name, "sd9"))
writel(1, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
else
writel(0, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
}
grp_mux = pmx_func->grpmux;
for (idx = 0; idx < grp_mux->pad_mux_count; idx++) {
@ -5385,12 +5412,27 @@ static int atlas7_pinmux_probe(struct platform_device *pdev)
struct atlas7_pmx *pmx;
struct device_node *np = pdev->dev.of_node;
u32 banks = ATLAS7_PINCTRL_REG_BANKS;
struct device_node *sys2pci_np;
struct resource res;
/* Create state holders etc for this driver */
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
if (!pmx)
return -ENOMEM;
/* The sd3 and sd9 shared all pins, and the function select by
* SYS2PCI_SDIO9SEL register
*/
sys2pci_np = of_find_node_by_name(NULL, "sys2pci");
if (!sys2pci_np)
return -EINVAL;
ret = of_address_to_resource(sys2pci_np, 0, &res);
if (ret)
return ret;
pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res);
if (IS_ERR(pmx->sys2pci_base))
return -ENOMEM;
pmx->dev = &pdev->dev;
pmx->pctl_data = &atlas7_ioc_data;

8
drivers/pinctrl/sirf/pinctrl-sirf.c
View File

@ -85,12 +85,16 @@ static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
/* calculate number of maps required */
for_each_child_of_node(np_config, np) {
ret = of_property_read_string(np, "sirf,function", &function);
if (ret < 0)
if (ret < 0) {
of_node_put(np);
return ret;
}
ret = of_property_count_strings(np, "sirf,pins");
if (ret < 0)
if (ret < 0) {
of_node_put(np);
return ret;
}
count += ret;
}

2
drivers/pinctrl/spear/Makefile
View File

@ -1,7 +1,7 @@
# SPEAr pinmux support
obj-$(CONFIG_PINCTRL_SPEAR_PLGPIO) += pinctrl-plgpio.o
obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o
obj-y += pinctrl-spear.o
obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o
obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o
obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o

9
drivers/pinctrl/sunxi/Kconfig
View File

@ -51,8 +51,17 @@ config PINCTRL_SUN8I_A23_R
depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
config PINCTRL_SUN8I_H3
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
config PINCTRL_SUN9I_A80
def_bool MACH_SUN9I
select PINCTRL_SUNXI_COMMON
config PINCTRL_SUN9I_A80_R
def_bool MACH_SUN9I
depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
endif

2
drivers/pinctrl/sunxi/Makefile
View File

@ -13,4 +13,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o

515
drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c Normal file
View File

@ -0,0 +1,515 @@
/*
* Allwinner H3 SoCs pinctrl driver.
*
* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
*
* Based on pinctrl-sun8i-a23.c, which is:
* Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
* Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8i_h3_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION(0x3, "jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* RX */
SUNXI_FUNCTION(0x3, "pwm0"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* PWREN */
SUNXI_FUNCTION(0x3, "pwm1"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* DATA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* RST */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* DET */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x3, "di"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x3, "di"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
SUNXI_FUNCTION(0x3, "spi0")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RE */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXD3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXD2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXCTL/RXDV */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXD3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXD2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* CRS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXCTL/TXEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* CLKIN/COL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* MDC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* MDIO */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
SUNXI_FUNCTION(0x3, "ts")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
SUNXI_FUNCTION(0x3, "ts")), /* ERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x3, "ts")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x3, "ts")), /* DVLD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
SUNXI_FUNCTION(0x3, "ts")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
SUNXI_FUNCTION(0x3, "ts")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x3, "ts")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x3, "ts")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x3, "ts")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x3, "ts")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x3, "ts")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x3, "ts")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SCK */
SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SDA */
SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag")), /* MS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag")), /* DI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag")), /* DO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag")), /* CK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
};
static const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_data = {
.pins = sun8i_h3_pins,
.npins = ARRAY_SIZE(sun8i_h3_pins),
.irq_banks = 2,
};
static int sun8i_h3_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun8i_h3_pinctrl_data);
}
static const struct of_device_id sun8i_h3_pinctrl_match[] = {
{ .compatible = "allwinner,sun8i-h3-pinctrl", },
{}
};
static struct platform_driver sun8i_h3_pinctrl_driver = {
.probe = sun8i_h3_pinctrl_probe,
.driver = {
.name = "sun8i-h3-pinctrl",
.of_match_table = sun8i_h3_pinctrl_match,
},
};
builtin_platform_driver(sun8i_h3_pinctrl_driver);

181
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c Normal file
View File

@ -0,0 +1,181 @@
/*
* Allwinner A80 SoCs special pins pinctrl driver.
*
* Copyright (C) 2014 Maxime Ripard
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/reset.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun9i_a80_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_uart"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_uart"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_jtag"), /* TMS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_jtag"), /* TCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_jtag"), /* TDO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_jtag"), /* TDI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_cir_rx"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "1wire"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_ps2"), /* SCK1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_ps2"), /* SDA1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PM_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PM_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PM_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PM_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_i2s1"), /* LRCKR */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PM_EINT4 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PM_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PM_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2s0"), /* MCLK */
SUNXI_FUNCTION(0x3, "s_i2s1")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2s0"), /* BCLK */
SUNXI_FUNCTION(0x3, "s_i2s1")), /* BCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2s0"), /* LRCK */
SUNXI_FUNCTION(0x3, "s_i2s1")), /* LRCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2s0"), /* DIN */
SUNXI_FUNCTION(0x3, "s_i2s1")), /* DIN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2s0"), /* DOUT */
SUNXI_FUNCTION(0x3, "s_i2s1")), /* DOUT */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PM_EINT15 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c0"), /* SCK */
SUNXI_FUNCTION(0x3, "s_rsb")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c0"), /* SDA */
SUNXI_FUNCTION(0x3, "s_rsb")), /* SDA */
};
static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
.pins = sun9i_a80_r_pins,
.npins = ARRAY_SIZE(sun9i_a80_r_pins),
.pin_base = PL_BASE,
.irq_banks = 2,
};
static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun9i_a80_r_pinctrl_data);
}
static const struct of_device_id sun9i_a80_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun9i-a80-r-pinctrl", },
{}
};
MODULE_DEVICE_TABLE(of, sun9i_a80_r_pinctrl_match);
static struct platform_driver sun9i_a80_r_pinctrl_driver = {
.probe = sun9i_a80_r_pinctrl_probe,
.driver = {
.name = "sun9i-a80-r-pinctrl",
.owner = THIS_MODULE,
.of_match_table = sun9i_a80_r_pinctrl_match,
},
};
module_platform_driver(sun9i_a80_r_pinctrl_driver);
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
MODULE_DESCRIPTION("Allwinner A80 R_PIO pinctrl driver");
MODULE_LICENSE("GPL");

23
drivers/pinctrl/uniphier/Kconfig
View File

@ -1,32 +1,35 @@
if ARCH_UNIPHIER
config PINCTRL_UNIPHIER
bool
menuconfig PINCTRL_UNIPHIER
bool "UniPhier SoC pinctrl drivers"
depends on ARCH_UNIPHIER
depends on OF && MFD_SYSCON
default y
select PINMUX
select GENERIC_PINCONF
if PINCTRL_UNIPHIER
config PINCTRL_UNIPHIER_PH1_LD4
tristate "UniPhier PH1-LD4 SoC pinctrl driver"
select PINCTRL_UNIPHIER
default y
config PINCTRL_UNIPHIER_PH1_PRO4
tristate "UniPhier PH1-Pro4 SoC pinctrl driver"
select PINCTRL_UNIPHIER
default y
config PINCTRL_UNIPHIER_PH1_SLD8
tristate "UniPhier PH1-sLD8 SoC pinctrl driver"
select PINCTRL_UNIPHIER
default y
config PINCTRL_UNIPHIER_PH1_PRO5
tristate "UniPhier PH1-Pro5 SoC pinctrl driver"
select PINCTRL_UNIPHIER
default y
config PINCTRL_UNIPHIER_PROXSTREAM2
tristate "UniPhier ProXstream2 SoC pinctrl driver"
select PINCTRL_UNIPHIER
default y
config PINCTRL_UNIPHIER_PH1_LD6B
tristate "UniPhier PH1-LD6b SoC pinctrl driver"
select PINCTRL_UNIPHIER
default y
endif

1
include/linux/platform_device.h
View File

@ -51,6 +51,7 @@ extern void arch_setup_pdev_archdata(struct platform_device *);
extern struct resource *platform_get_resource(struct platform_device *,
unsigned int, unsigned int);
extern int platform_get_irq(struct platform_device *, unsigned int);
extern int platform_irq_count(struct platform_device *);
extern struct resource *platform_get_resource_byname(struct platform_device *,
unsigned int,
const char *);