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SoC platform removal 

There are a lot of platforms that have not seen any interesting code
 changes in the past five years or more.
 
 I made a list and asked around which ones are no longer in use [1], and
 received confirmation about six ARM platforms and the TI C6x architecture
 that have all reached the end of their life upstream, with no known
 users remaining:
 
  - efm32 -- added in 2011, first Cortex-M, no notable changes after 2013
  - picoxcell -- added in 2011, abandoned after 2012 acquisition
  - prima2 -- added in 20111, no notable changes since 2015
  - tango -- added in 2015, sporadic changes until 2017, but abandoned
  - u300 -- added in 2009, no notable changes since 2013
  - zx --added in 2015 for both 32, 2017 for 64 bit, no notable changes
  - arch/c6x -- added in 2011, but work stalled soon after that
 
 A number of other platforms on the original list turned out to still
 have users. In some cases there are out-of-tree patches and users
 that plan to contribute them in the future, in other cases the code
 is complete and works reliably.
 
 [1] https://lore.kernel.org/lkml/CAK8P3a2DZ8xQp7R=H=wewHnT2=a_=M53QsZOueMVEf7tOZLKNg@mail.gmail.com/
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-platform-removal-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC platform removals from Arnd Bergmann:
 "There are a lot of platforms that have not seen any interesting code
  changes in the past five years or more.

  I made a list and asked around which ones are no longer in use, and
  received confirmation about six ARM platforms and the TI C6x
  architecture that have all reached the end of their life upstream,
  with no known users remaining:

   - efm32 - added in 2011, first Cortex-M, no notable changes after 2013

   - picoxcell - added in 2011, abandoned after 2012 acquisition

   - prima2 - added in 20111, no notable changes since 2015

   - tango - added in 2015, sporadic changes until 2017, but abandoned

   - u300 - added in 2009, no notable changes since 2013

   - zx - added in 2015 for both 32, 2017 for 64 bit, no notable changes

   - arch/c6x - added in 2011, but work stalled soon after that

  A number of other platforms on the original list turned out to still
  have users. In some cases there are out-of-tree patches and users that
  plan to contribute them in the future, in other cases the code is
  complete and works reliably"

Link: https://lore.kernel.org/lkml/CAK8P3a2DZ8xQp7R=H=wewHnT2=a_=M53QsZOueMVEf7tOZLKNg@mail.gmail.com/

* tag 'arm-platform-removal-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  ARM: remove u300 platform
  ARM: remove tango platform
  ARM: remove zte zx platform
  ARM: remove sirf prima2/atlas platforms
  c6x: remove architecture
  MAINTAINERS: Remove deleted platform efm32
  ARM: drop efm32 platform
  ARM: Remove PicoXcell platform support
  ARM: dts: Remove PicoXcell platforms
This commit is contained in:
Linus Torvalds 2021-02-20 18:16:30 -08:00
parent 7ddfe9a6a3 ce1380c9f4
commit 584ce3c9b4
221 changed files with 11 additions and 21464 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
Documentation/devicetree/bindings/arm/sirf.yaml
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@ -1,30 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sirf.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CSR SiRFprimaII and SiRFmarco device tree bindings.
maintainers:
- Binghua Duan <binghua.duan@csr.com>
- Barry Song <Baohua.Song@csr.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- const: sirf,atlas6-cb
- const: sirf,atlas6
- items:
- const: sirf,atlas7-cb
- const: sirf,atlas7
- items:
- const: sirf,prima2-cb
- const: sirf,prima2
additionalProperties: true
...

46
Documentation/devicetree/bindings/arm/ste-u300.txt
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@ -1,46 +0,0 @@
ST-Ericsson U300 Device Tree Bindings
For various board the "board" node may contain specific properties
that pertain to this particular board, such as board-specific GPIOs
or board power regulator supplies.
Required root node property:
compatible="stericsson,u300";
Required node: syscon
This contains the system controller.
- compatible: must be "stericsson,u300-syscon".
- reg: the base address and size of the system controller.
Boards with the U300 SoC include:
S365 "Small Board U365":
Required node: s365
This contains the board-specific information.
- compatible: must be "stericsson,s365".
- vana15-supply: the regulator supplying the 1.5V to drive the
board.
- syscon: a pointer to the syscon node so we can access the
syscon registers to set the board as self-powered.
Example:
/ {
model = "ST-Ericsson U300";
compatible = "stericsson,u300";
#address-cells = <1>;
#size-cells = <1>;
s365 {
compatible = "stericsson,s365";
vana15-supply = <&ab3100_ldo_d_reg>;
syscon = <&syscon>;
};
syscon: syscon@c0011000 {
compatible = "stericsson,u300-syscon";
reg = <0xc0011000 0x1000>;
};
};

30
Documentation/devicetree/bindings/arm/zte,sysctrl.txt
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@ -1,30 +0,0 @@
ZTE sysctrl Registers
Registers for 'zte,zx296702' SoC:
System management required properties:
- compatible = "zte,sysctrl"
Low power management required properties:
- compatible = "zte,zx296702-pcu"
Bus matrix required properties:
- compatible = "zte,zx-bus-matrix"
Registers for 'zte,zx296718' SoC:
System management required properties:
- compatible = "zte,zx296718-aon-sysctrl"
- compatible = "zte,zx296718-sysctrl"
Example:
aon_sysctrl: aon-sysctrl@116000 {
compatible = "zte,zx296718-aon-sysctrl", "syscon";
reg = <0x116000 0x1000>;
};
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
};

28
Documentation/devicetree/bindings/arm/zte.yaml
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@ -1,28 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/zte.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ZTE platforms device tree bindings
maintainers:
- Jun Nie <jun.nie@linaro.org>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- zte,zx296702-ad1
- const: zte,zx296702
- items:
- enum:
- zte,zx296718-evb
- const: zte,zx296718
additionalProperties: true
...

40
Documentation/devicetree/bindings/c6x/clocks.txt
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@ -1,40 +0,0 @@
C6X PLL Clock Controllers
-------------------------
This is a first-cut support for the SoC clock controllers. This is still
under development and will probably change as the common device tree
clock support is added to the kernel.
Required properties:
- compatible: "ti,c64x+pll"
May also have SoC-specific value to support SoC-specific initialization
in the driver. One of:
"ti,c6455-pll"
"ti,c6457-pll"
"ti,c6472-pll"
"ti,c6474-pll"
- reg: base address and size of register area
- clock-frequency: input clock frequency in hz
Optional properties:
- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
- ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
- ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
Example:
clock-controller@29a0000 {
compatible = "ti,c6472-pll", "ti,c64x+pll";
reg = <0x029a0000 0x200>;
clock-frequency = <25000000>;
ti,c64x+pll-bypass-delay = <200>;
ti,c64x+pll-reset-delay = <12000>;
ti,c64x+pll-lock-delay = <80000>;
};

127
Documentation/devicetree/bindings/c6x/dscr.txt
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@ -1,127 +0,0 @@
Device State Configuration Registers
------------------------------------
TI C6X SoCs contain a region of miscellaneous registers which provide various
function for SoC control or status. Details vary considerably among from SoC
to SoC with no two being alike.
In general, the Device State Configuration Registers (DSCR) will provide one or
more configuration registers often protected by a lock register where one or
more key values must be written to a lock register in order to unlock the
configuration register for writes. These configuration register may be used to
enable (and disable in some cases) SoC pin drivers, select peripheral clock
sources (internal or pin), etc. In some cases, a configuration register is
write once or the individual bits are write once. In addition to device config,
the DSCR block may provide registers which are used to reset peripherals,
provide device ID information, provide ethernet MAC addresses, as well as other
miscellaneous functions.
For device state control (enable/disable), each device control is assigned an
id which is used by individual device drivers to control the state as needed.
Required properties:
- compatible: must be "ti,c64x+dscr"
- reg: register area base and size
Optional properties:
NOTE: These are optional in that not all SoCs will have all properties. For
SoCs which do support a given property, leaving the property out of the
device tree will result in reduced functionality or possibly driver
failure.
- ti,dscr-devstat
offset of the devstat register
- ti,dscr-silicon-rev
offset, start bit, and bitsize of silicon revision field
- ti,dscr-rmii-resets
offset and bitmask of RMII reset field. May have multiple tuples if more
than one ethernet port is available.
- ti,dscr-locked-regs
possibly multiple tuples describing registers which are write protected by
a lock register. Each tuple consists of the register offset, lock register
offsset, and the key value used to unlock the register.
- ti,dscr-kick-regs
offset and key values of two "kick" registers used to write protect other
registers in DSCR. On SoCs using kick registers, the first key must be
written to the first kick register and the second key must be written to
the second register before other registers in the area are write-enabled.
- ti,dscr-mac-fuse-regs
MAC addresses are contained in two registers. Each element of a MAC address
is contained in a single byte. This property has two tuples. Each tuple has
a register offset and four cells representing bytes in the register from
most significant to least. The value of these four cells is the MAC byte
index (1-6) of the byte within the register. A value of 0 means the byte
is unused in the MAC address.
- ti,dscr-devstate-ctl-regs
This property describes the bitfields used to control the state of devices.
Each tuple describes a range of identical bitfields used to control one or
more devices (one bitfield per device). The layout of each tuple is:
start_id num_ids reg enable disable start_bit nbits
Where:
start_id is device id for the first device control in the range
num_ids is the number of device controls in the range
reg is the offset of the register holding the control bits
enable is the value to enable a device
disable is the value to disable a device (0xffffffff if cannot disable)
start_bit is the bit number of the first bit in the range
nbits is the number of bits per device control
- ti,dscr-devstate-stat-regs
This property describes the bitfields used to provide device state status
for device states controlled by the DSCR. Each tuple describes a range of
identical bitfields used to provide status for one or more devices (one
bitfield per device). The layout of each tuple is:
start_id num_ids reg enable disable start_bit nbits
Where:
start_id is device id for the first device status in the range
num_ids is the number of devices covered by the range
reg is the offset of the register holding the status bits
enable is the value indicating device is enabled
disable is the value indicating device is disabled
start_bit is the bit number of the first bit in the range
nbits is the number of bits per device status
- ti,dscr-privperm
Offset and default value for register used to set access privilege for
some SoC devices.
Example:
device-state-config-regs@2a80000 {
compatible = "ti,c64x+dscr";
reg = <0x02a80000 0x41000>;
ti,dscr-devstat = <0>;
ti,dscr-silicon-rev = <8 28 0xf>;
ti,dscr-rmii-resets = <0x40020 0x00040000>;
ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
ti,dscr-devstate-ctl-regs =
<0 12 0x40008 1 0 0 2
12 1 0x40008 3 0 30 2
13 2 0x4002c 1 0xffffffff 0 1>;
ti,dscr-devstate-stat-regs =
<0 10 0x40014 1 0 0 3
10 2 0x40018 1 0 0 3>;
ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
0x704 5 6 0 0>;
ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
ti,dscr-kick-regs = <0x38 0x83E70B13
0x3c 0x95A4F1E0>;
};

62
Documentation/devicetree/bindings/c6x/emifa.txt
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@ -1,62 +0,0 @@
External Memory Interface
-------------------------
The emifa node describes a simple external bus controller found on some C6X
SoCs. This interface provides external busses with a number of chip selects.
Required properties:
- compatible: must be "ti,c64x+emifa", "simple-bus"
- reg: register area base and size
- #address-cells: must be 2 (chip-select + offset)
- #size-cells: must be 1
- ranges: mapping from EMIFA space to parent space
Optional properties:
- ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
- ti,emifa-burst-priority:
Number of memory transfers after which the EMIF will elevate the priority
of the oldest command in the command FIFO. Setting this field to 255
disables this feature, thereby allowing old commands to stay in the FIFO
indefinitely.
- ti,emifa-ce-config:
Configuration values for each of the supported chip selects.
Example:
emifa@70000000 {
compatible = "ti,c64x+emifa", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x70000000 0x100>;
ranges = <0x2 0x0 0xa0000000 0x00000008
0x3 0x0 0xb0000000 0x00400000
0x4 0x0 0xc0000000 0x10000000
0x5 0x0 0xD0000000 0x10000000>;
ti,dscr-dev-enable = <13>;
ti,emifa-burst-priority = <255>;
ti,emifa-ce-config = <0x00240120
0x00240120
0x00240122
0x00240122>;
flash@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x3 0x0 0x400000>;
bank-width = <1>;
device-width = <1>;
partition@0 {
reg = <0x0 0x400000>;
label = "NOR";
};
};
};
This shows a flash chip attached to chip select 3.

28
Documentation/devicetree/bindings/c6x/soc.txt
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@ -1,28 +0,0 @@
C6X System-on-Chip
------------------
Required properties:
- compatible: "simple-bus"
- #address-cells: must be 1
- #size-cells: must be 1
- ranges
Optional properties:
- model: specific SoC model
- nodes for IP blocks within SoC
Example:
soc {
compatible = "simple-bus";
model = "tms320c6455";
#address-cells = <1>;
#size-cells = <1>;
ranges;
...
};

103
Documentation/devicetree/bindings/interrupt-controller/ti,c64x+megamod-pic.txt
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@ -1,103 +0,0 @@
C6X Interrupt Chips
-------------------
* C64X+ Core Interrupt Controller
The core interrupt controller provides 16 prioritized interrupts to the
C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
sources coming from outside the core.
Required properties:
--------------------
- compatible: Should be "ti,c64x+core-pic";
- #interrupt-cells: <1>
Interrupt Specifier Definition
------------------------------
Single cell specifying the core interrupt priority level (4-15) where
4 is highest priority and 15 is lowest priority.
Example
-------
core_pic: interrupt-controller@0 {
interrupt-controller;
#interrupt-cells = <1>;
compatible = "ti,c64x+core-pic";
};
* C64x+ Megamodule Interrupt Controller
The megamodule PIC consists of four interrupt mupliplexers each of which
combine up to 32 interrupt inputs into a single interrupt output which
may be cascaded into the core interrupt controller. The megamodule PIC
has a total of 12 outputs cascading into the core interrupt controller.
One for each core interrupt priority level. In addition to the combined
interrupt sources, individual megamodule interrupts may be cascaded to
the core interrupt controller. When an individual interrupt is cascaded,
it is no longer handled through a megamodule interrupt combiner and is
considered to have the core interrupt controller as the parent.
Required properties:
--------------------
- compatible: "ti,c64x+megamod-pic"
- interrupt-controller
- #interrupt-cells: <1>
- reg: base address and size of register area
- interrupts: This should have four cells; one for each interrupt combiner.
The cells contain the core priority interrupt to which the
corresponding combiner output is wired.
Optional properties:
--------------------
- ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
priority interrupts. The first cell corresponds to
core priority 4 and the last cell corresponds to
core priority 15. The value of each cell is the
megamodule interrupt source which is MUXed to
the core interrupt corresponding to the cell
position. Allowed values are 4 - 127. Mapping for
interrupts 0 - 3 (combined interrupt sources) are
ignored.
Interrupt Specifier Definition
------------------------------
Single cell specifying the megamodule interrupt source (4-127). Note that
interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
use the core interrupt controller as their parent and the specifier will
be the core priority level, not the megamodule interrupt number.
Examples
--------
megamod_pic: interrupt-controller@1800000 {
compatible = "ti,c64x+megamod-pic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x1800000 0x1000>;
interrupt-parent = <&core_pic>;
interrupts = < 12 13 14 15 >;
};
This is a minimal example where all individual interrupts go through a
combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
to interrupt 13, etc.
megamod_pic: interrupt-controller@1800000 {
compatible = "ti,c64x+megamod-pic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x1800000 0x1000>;
interrupt-parent = <&core_pic>;
interrupts = < 12 13 14 15 >;
ti,c64x+megamod-pic-mux = < 0 0 0 0
32 0 0 0
0 0 0 0 >;
};
This the same as the first example except that megamodule interrupt 32 is
mapped directly to core priority interrupt 8. The node using this interrupt
must set the core controller as its interrupt parent and use 8 in the
interrupt specifier value.

42
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@ -1,42 +0,0 @@
CSR SiRFSoC Reset Controller
======================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc"
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below
example:
rstc: reset-controller@88010000 {
compatible = "sirf,prima2-rstc";
reg = <0x88010000 0x1000>;
#reset-cells = <1>;
};
Specifying reset lines connected to IP modules
==============================================
The reset controller(rstc) manages various reset sources. This module provides
reset signals for most blocks in system. Those device nodes should specify the
reset line on the rstc in their resets property, containing a phandle to the
rstc device node and a RESET_INDEX specifying which module to reset, as described
in reset.txt.
For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers.
For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose
rest_bit is in SW_RST1, its RESET_INDEX is 32~63.
example:
vpp@90020000 {
compatible = "sirf,prima2-vpp";
reg = <0x90020000 0x10000>;
interrupts = <31>;
clocks = <&clks 35>;
resets = <&rstc 6>;
};

20
Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
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@ -1,20 +0,0 @@
ZTE zx2967 SoCs Reset Controller
=======================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: should be one of the following.
* zte,zx296718-reset
- reg: physical base address of the controller and length of memory mapped
region.
- #reset-cells: must be 1.
example:
reset: reset-controller@1461060 {
compatible = "zte,zx296718-reset";
reg = <0x01461060 0x8>;
#reset-cells = <1>;
};

2
Documentation/devicetree/bindings/serial/pl011.yaml
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@ -19,7 +19,6 @@ select:
contains:
enum:
- arm,pl011
- zte,zx296702-uart
required:
- compatible
@ -30,7 +29,6 @@ properties:
- const: arm,pl011
- const: arm,primecell
- items:
- const: zte,zx296702-uart
- const: arm,primecell
reg:

19
Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt
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@ -1,19 +0,0 @@
* ZTE zx2967 family Power Domains
zx2967 family includes support for multiple power domains which are used
to gate power to one or more peripherals on the processor.
Required Properties:
- compatible: should be one of the following.
* zte,zx296718-pcu - for zx296718 power domain.
- reg: physical base address of the controller and length of memory mapped
region.
- #power-domain-cells: Must be 1.
Example:
pcu_domain: pcu@117000 {
compatible = "zte,zx296718-pcu";
reg = <0x00117000 0x1000>;
#power-domain-cells = <1>;
};

25
Documentation/devicetree/bindings/timer/ti,c64x+timer64.txt
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@ -1,25 +0,0 @@
Timer64
-------
The timer64 node describes C6X event timers.
Required properties:
- compatible: must be "ti,c64x+timer64"
- reg: base address and size of register region
- interrupts: interrupt id
Optional properties:
- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
Example:
timer0: timer@25e0000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x01 >;
reg = <0x25e0000 0x40>;
interrupt-parent = <&megamod_pic>;
interrupts = < 16 >;
};

100
MAINTAINERS
View File

@ -1778,19 +1778,6 @@ F: drivers/net/ethernet/cortina/
F: drivers/pinctrl/pinctrl-gemini.c
F: drivers/rtc/rtc-ftrtc010.c
ARM/CSR SIRFPRIMA2 MACHINE SUPPORT
M: Barry Song <baohua@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux.git
F: arch/arm/boot/dts/prima2*
F: arch/arm/mach-prima2/
F: drivers/clk/sirf/
F: drivers/clocksource/timer-atlas7.c
F: drivers/clocksource/timer-prima2.c
X: drivers/gnss
N: [^a-z]sirf
ARM/CZ.NIC TURRIS MOX SUPPORT
M: Marek Behun <marek.behun@nic.cz>
S: Maintained
@ -1806,13 +1793,6 @@ F: drivers/firmware/turris-mox-rwtm.c
F: drivers/gpio/gpio-moxtet.c
F: include/linux/moxtet.h
ARM/ENERGY MICRO (SILICON LABS) EFM32 SUPPORT
M: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
R: Pengutronix Kernel Team <kernel@pengutronix.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
N: efm32
ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
M: Robert Jarzmik <robert.jarzmik@free.fr>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -2155,7 +2135,7 @@ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT
M: Michael Petchkovsky <mkpetch@internode.on.net>
S: Maintained
ARM/NOMADIK/U300/Ux500 ARCHITECTURES
ARM/NOMADIK/Ux500 ARCHITECTURES
M: Linus Walleij <linus.walleij@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
@ -2164,35 +2144,23 @@ F: Documentation/devicetree/bindings/arm/ste-*
F: Documentation/devicetree/bindings/arm/ux500.yaml
F: Documentation/devicetree/bindings/arm/ux500/
F: Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
F: Documentation/devicetree/bindings/i2c/i2c-stu300.txt
F: arch/arm/boot/dts/ste-*
F: arch/arm/mach-nomadik/
F: arch/arm/mach-u300/
F: arch/arm/mach-ux500/
F: drivers/clk/clk-nomadik.c
F: drivers/clk/clk-u300.c
F: drivers/clocksource/clksrc-dbx500-prcmu.c
F: drivers/clocksource/timer-u300.c
F: drivers/dma/coh901318*
F: drivers/dma/ste_dma40*
F: drivers/hwspinlock/u8500_hsem.c
F: drivers/i2c/busses/i2c-nomadik.c
F: drivers/i2c/busses/i2c-stu300.c
F: drivers/iio/adc/ab8500-gpadc.c
F: drivers/mfd/ab3100*
F: drivers/mfd/ab8500*
F: drivers/mfd/abx500*
F: drivers/mfd/db8500*
F: drivers/mfd/dbx500*
F: drivers/pinctrl/nomadik/
F: drivers/pinctrl/pinctrl-coh901*
F: drivers/pinctrl/pinctrl-u300.c
F: drivers/rtc/rtc-ab3100.c
F: drivers/rtc/rtc-ab8500.c
F: drivers/rtc/rtc-coh901331.c
F: drivers/rtc/rtc-pl031.c
F: drivers/soc/ux500/
F: drivers/watchdog/coh901327_wdt.c
ARM/NUVOTON NPCM ARCHITECTURE
M: Avi Fishman <avifishman70@gmail.com>
@ -2557,13 +2525,6 @@ F: arch/arm/boot/dts/berlin*
F: arch/arm/mach-berlin/
F: arch/arm64/boot/dts/synaptics/
ARM/TANGO ARCHITECTURE
M: Marc Gonzalez <marc.w.gonzalez@free.fr>
M: Mans Rullgard <mans@mansr.com>
L: linux-arm-kernel@lists.infradead.org
S: Odd Fixes
N: tango
ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -2725,40 +2686,6 @@ S: Maintained
F: arch/arm/mach-pxa/include/mach/z2.h
F: arch/arm/mach-pxa/z2.c
ARM/ZTE ARCHITECTURE
M: Jun Nie <jun.nie@linaro.org>
M: Shawn Guo <shawnguo@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/zte.yaml
F: Documentation/devicetree/bindings/clock/zx2967*.txt
F: Documentation/devicetree/bindings/dma/zxdma.txt
F: Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
F: Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
F: Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
F: Documentation/devicetree/bindings/soc/zte/
F: Documentation/devicetree/bindings/sound/zte,*.txt
F: Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
F: Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
F: arch/arm/boot/dts/zx2967*
F: arch/arm/mach-zx/
F: arch/arm64/boot/dts/zte/
F: drivers/clk/zte/
F: drivers/dma/zx_dma.c
F: drivers/gpio/gpio-zx.c
F: drivers/i2c/busses/i2c-zx2967.c
F: drivers/mmc/host/dw_mmc-zx.*
F: drivers/pinctrl/zte/
F: drivers/soc/zte/
F: drivers/thermal/zx2967_thermal.c
F: drivers/watchdog/zx2967_wdt.c
F: include/dt-bindings/clock/zx2967*.h
F: include/dt-bindings/soc/zte,*.h
F: sound/soc/codecs/zx_aud96p22.c
F: sound/soc/zte/
ARM/ZYNQ ARCHITECTURE
M: Michal Simek <michal.simek@xilinx.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -3874,14 +3801,6 @@ F: drivers/irqchip/irq-csky-*
N: csky
K: csky
C6X ARCHITECTURE
M: Mark Salter <msalter@redhat.com>
M: Aurelien Jacquiot <jacquiot.aurelien@gmail.com>
L: linux-c6x-dev@linux-c6x.org
S: Maintained
W: http://www.linux-c6x.org/wiki/index.php/Main_Page
F: arch/c6x/
CA8210 IEEE-802.15.4 RADIO DRIVER
M: Harry Morris <h.morris@cascoda.com>
L: linux-wpan@vger.kernel.org
@ -6089,14 +6008,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/xlnx/
F: drivers/gpu/drm/xlnx/
DRM DRIVERS FOR ZTE ZX
M: Shawn Guo <shawnguo@kernel.org>
L: dri-devel@lists.freedesktop.org
S: Maintained
T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/zte,vou.txt
F: drivers/gpu/drm/zte/
DRM PANEL DRIVERS
M: Thierry Reding <thierry.reding@gmail.com>
R: Sam Ravnborg <sam@ravnborg.org>
@ -14022,15 +13933,6 @@ L: linux-input@vger.kernel.org
S: Maintained
F: drivers/hid/hid-picolcd*
PICOXCELL SUPPORT
M: Jamie Iles <jamie@jamieiles.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
T: git git://github.com/jamieiles/linux-2.6-ji.git
F: arch/arm/boot/dts/picoxcell*
F: arch/arm/mach-picoxcell/
F: drivers/crypto/picoxcell*
PIDFD API
M: Christian Brauner <christian@brauner.io>
L: linux-kernel@vger.kernel.org

20
arch/arm/Kconfig
View File

@ -671,10 +671,6 @@ source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/mach-oxnas/Kconfig"
source "arch/arm/mach-picoxcell/Kconfig"
source "arch/arm/mach-prima2/Kconfig"
source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/plat-pxa/Kconfig"
@ -706,12 +702,8 @@ source "arch/arm/mach-stm32/Kconfig"
source "arch/arm/mach-sunxi/Kconfig"
source "arch/arm/mach-tango/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-u300/Kconfig"
source "arch/arm/mach-uniphier/Kconfig"
source "arch/arm/mach-ux500/Kconfig"
@ -722,19 +714,9 @@ source "arch/arm/mach-vexpress/Kconfig"
source "arch/arm/mach-vt8500/Kconfig"
source "arch/arm/mach-zx/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
# ARMv7-M architecture
config ARCH_EFM32
bool "Energy Micro efm32"
depends on ARM_SINGLE_ARMV7M
select GPIOLIB
help
Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
processors.
config ARCH_LPC18XX
bool "NXP LPC18xx/LPC43xx"
depends on ARM_SINGLE_ARMV7M
@ -1552,7 +1534,7 @@ config ARM_MODULE_PLTS
config FORCE_MAX_ZONEORDER
int "Maximum zone order"
default "12" if SOC_AM33XX
default "9" if SA1111 || ARCH_EFM32
default "9" if SA1111
default "11"
help
The kernel memory allocator divides physically contiguous memory

95
arch/arm/Kconfig.debug
View File

@ -770,14 +770,6 @@ choice
depends on ARCH_OMAP2PLUS
select DEBUG_OMAP2PLUS_UART
config DEBUG_PICOXCELL_UART
depends on ARCH_PICOXCELL
bool "Use PicoXcell UART for low-level debug"
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on PicoXcell based platforms.
config DEBUG_PXA_UART1
depends on ARCH_PXA
bool "Use PXA UART1 for low-level debug"
@ -1150,32 +1142,6 @@ choice
Say Y here if you want kernel low-level debugging support
on Allwinner A31/A23 based platforms on the R_UART.
config DEBUG_SIRFPRIMA2_UART1
bool "Kernel low-level debugging messages via SiRFprimaII UART1"
depends on ARCH_PRIMA2
select DEBUG_SIRFSOC_UART
help
Say Y here if you want the debug print routines to direct
their output to the uart1 port on SiRFprimaII devices.
config DEBUG_SIRFATLAS7_UART0
bool "Kernel low-level debugging messages via SiRFatlas7 UART0"
depends on ARCH_ATLAS7
select DEBUG_SIRFSOC_UART
help
Say Y here if you want the debug print routines to direct
their output to the uart0 port on SiRFATLAS7 devices.The uart0
is used on SiRFATLAS7 as a extra debug port.sometimes an extra
debug port can be very useful.
config DEBUG_SIRFATLAS7_UART1
bool "Kernel low-level debugging messages via SiRFatlas7 UART1"
depends on ARCH_ATLAS7
select DEBUG_SIRFSOC_UART
help
Say Y here if you want the debug print routines to direct
their output to the uart1 port on SiRFATLAS7 devices.
config DEBUG_SPEAR3XX
bool "Kernel low-level debugging messages via ST SPEAr 3xx/6xx UART"
depends on ARCH_SPEAR3XX || ARCH_SPEAR6XX
@ -1314,14 +1280,6 @@ choice
Say Y here if you want kernel low-level debugging support
on Tegra based platforms.
config DEBUG_U300_UART
bool "Kernel low-level debugging messages via U300 UART0"
depends on ARCH_U300
select DEBUG_UART_PL01X
help
Say Y here if you want the debug print routines to direct
their output to the uart port on U300 devices.
config DEBUG_UX500_UART
depends on ARCH_U8500
bool "Use Ux500 UART for low-level debug"
@ -1387,18 +1345,6 @@ choice
This option selects UART0 on VIA/Wondermedia System-on-a-chip
devices, including VT8500, WM8505, WM8650 and WM8850.
config DEBUG_ZTE_ZX
bool "Use ZTE ZX UART"
select DEBUG_UART_PL01X
depends on ARCH_ZX
help
Say Y here if you are enabling ZTE ZX296702 SOC and need
debug uart support.
This option is preferred over the platform specific
options; the platform specific options are deprecated
and will be soon removed.
config DEBUG_ZYNQ_UART0
bool "Kernel low-level debugging on Xilinx Zynq using UART0"
depends on ARCH_ZYNQ
@ -1456,20 +1402,6 @@ choice
options; the platform specific options are deprecated
and will be soon removed.
config DEBUG_LL_UART_EFM32
bool "Kernel low-level debugging via efm32 UART"
depends on ARCH_EFM32
help
Say Y here if you want the debug print routines to direct
their output to an UART or USART port on efm32 based
machines. Use the following addresses for DEBUG_UART_PHYS:
0x4000c000 | USART0
0x4000c400 | USART1
0x4000c800 | USART2
0x4000e000 | UART0
0x4000e400 | UART1
config DEBUG_LL_UART_PL01X
bool "Kernel low-level debugging via ARM Ltd PL01x Primecell UART"
help
@ -1560,10 +1492,6 @@ config DEBUG_STM32_UART
bool
depends on ARCH_STM32
config DEBUG_SIRFSOC_UART
bool
depends on ARCH_SIRF
config DEBUG_UART_FLOW_CONTROL
bool "Enable flow control (CTS) for the debug UART"
depends on DEBUG_LL
@ -1587,7 +1515,6 @@ config DEBUG_LL_INCLUDE
default "debug/meson.S" if DEBUG_MESON_UARTAO
default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X
default "debug/exynos.S" if DEBUG_EXYNOS_UART
default "debug/efm32.S" if DEBUG_LL_UART_EFM32
default "debug/icedcc.S" if DEBUG_ICEDCC
default "debug/imx.S" if DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
@ -1619,7 +1546,6 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART || DEBUG_S3C64XX_UART
default "debug/s5pv210.S" if DEBUG_S5PV210_UART
default "debug/sirf.S" if DEBUG_SIRFSOC_UART
default "debug/sti.S" if DEBUG_STI_UART
default "debug/stm32.S" if DEBUG_STM32_UART
default "debug/tegra.S" if DEBUG_TEGRA_UART
@ -1653,7 +1579,6 @@ config DEBUG_UART_PHYS
default 0x02531000 if DEBUG_KEYSTONE_UART1
default 0x03010fe0 if ARCH_RPC
default 0x07000000 if DEBUG_SUN9I_UART0
default 0x09405000 if DEBUG_ZTE_ZX
default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \
DEBUG_VEXPRESS_UART0_CA9
default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
@ -1671,8 +1596,6 @@ config DEBUG_UART_PHYS
default 0x1600d000 if DEBUG_SD5203_UART
default 0x18000300 if DEBUG_BCM_5301X
default 0x18000400 if DEBUG_BCM_HR2
default 0x18010000 if DEBUG_SIRFATLAS7_UART0
default 0x18020000 if DEBUG_SIRFATLAS7_UART1
default 0x18023000 if DEBUG_BCM_IPROC_UART3
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
default 0x20001000 if DEBUG_HIP01_UART
@ -1682,7 +1605,6 @@ config DEBUG_UART_PHYS
default 0x20201000 if DEBUG_BCM2835
default 0x3e000000 if DEBUG_BCM_KONA_UART
default 0x3f201000 if DEBUG_BCM2836
default 0x4000e400 if DEBUG_LL_UART_EFM32
default 0x40010000 if STM32MP1_DEBUG_UART
default 0x40011000 if STM32F4_DEBUG_UART || STM32F7_DEBUG_UART || \
STM32H7_DEBUG_UART
@ -1717,12 +1639,9 @@ config DEBUG_UART_PHYS
default 0x80010000 if DEBUG_ASM9260_UART
default 0x80070000 if DEBUG_IMX23_UART
default 0x80074000 if DEBUG_IMX28_UART
default 0x80230000 if DEBUG_PICOXCELL_UART
default 0x808c0000 if DEBUG_EP93XX || ARCH_EP93XX
default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
default 0xb0060000 if DEBUG_SIRFPRIMA2_UART1
default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX
default 0xc0013000 if DEBUG_U300_UART
default 0xc8000000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
default 0xd0000000 if DEBUG_SPEAR3XX
@ -1768,7 +1687,6 @@ config DEBUG_UART_PHYS
default 0xfffff200 if DEBUG_AT91_RM9200_DBGU
depends on ARCH_EP93XX || \
DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_LL_UART_EFM32 || \
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
DEBUG_R7S9210_SCIF2 || DEBUG_R7S9210_SCIF4 || \
@ -1780,7 +1698,7 @@ config DEBUG_UART_PHYS
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \
DEBUG_DIGICOLOR_UA0 || \
DEBUG_AT91_UART || DEBUG_STM32_UART
config DEBUG_UART_VIRT
@ -1842,7 +1760,6 @@ config DEBUG_UART_VIRT
default 0xfb020000 if DEBUG_OMAP3UART3
default 0xfb042000 if DEBUG_OMAP3UART4
default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
default 0xfc705000 if DEBUG_ZTE_ZX
default 0xfcfe8600 if DEBUG_BCM63XX_UART
default 0xfd000000 if DEBUG_SPEAR3XX || DEBUG_SPEAR13XX
default 0xfd883000 if DEBUG_ALPINE_UART0
@ -1850,7 +1767,6 @@ config DEBUG_UART_VIRT
default 0xfe017000 if DEBUG_MMP_UART2
default 0xfe018000 if DEBUG_MMP_UART3
default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART
default 0xfe230000 if DEBUG_PICOXCELL_UART
default 0xfe300000 if DEBUG_BCM_KONA_UART
default 0xfe800000 if ARCH_IOP32X
default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART
@ -1863,10 +1779,7 @@ config DEBUG_UART_VIRT
default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xfec10000 if DEBUG_SIRFATLAS7_UART0
default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
default 0xfec20000 if DEBUG_SIRFATLAS7_UART1
default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1
default 0xfec90000 if DEBUG_RK32_UART2
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART
@ -1882,7 +1795,6 @@ config DEBUG_UART_VIRT
default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
default 0xff003000 if DEBUG_U300_UART
default 0xffd01000 if DEBUG_HIP01_UART
default DEBUG_UART_PHYS if !MMU
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
@ -1890,7 +1802,7 @@ config DEBUG_UART_VIRT
DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \
DEBUG_DIGICOLOR_UA0 || \
DEBUG_AT91_UART || DEBUG_STM32_UART
config DEBUG_UART_8250_SHIFT
@ -1905,8 +1817,7 @@ config DEBUG_UART_8250_WORD
bool "Use 32-bit accesses for 8250 UART"
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
depends on DEBUG_UART_8250_SHIFT >= 2
default y if DEBUG_PICOXCELL_UART || \
DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \
default y if DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \
DEBUG_SOCFPGA_CYCLONE5_UART1 || DEBUG_KEYSTONE_UART0 || \
DEBUG_KEYSTONE_UART1 || DEBUG_ALPINE_UART0 || \
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \

6
arch/arm/Makefile
View File

@ -168,7 +168,6 @@ machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor
machine-$(CONFIG_ARCH_DOVE) += dove
machine-$(CONFIG_ARCH_EFM32) += efm32
machine-$(CONFIG_ARCH_EP93XX) += ep93xx
machine-$(CONFIG_ARCH_EXYNOS) += exynos
machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge
@ -199,7 +198,6 @@ machine-$(CONFIG_ARCH_OXNAS) += oxnas
machine-$(CONFIG_ARCH_OMAP1) += omap1
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x
machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell
machine-$(CONFIG_ARCH_PXA) += pxa
machine-$(CONFIG_ARCH_QCOM) += qcom
machine-$(CONFIG_ARCH_RDA) += rda
@ -211,19 +209,15 @@ machine-$(CONFIG_PLAT_SAMSUNG) += s3c
machine-$(CONFIG_ARCH_S5PV210) += s5pv210
machine-$(CONFIG_ARCH_SA1100) += sa1100
machine-$(CONFIG_ARCH_RENESAS) += shmobile
machine-$(CONFIG_ARCH_SIRF) += prima2
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STI) += sti
machine-$(CONFIG_ARCH_STM32) += stm32
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_TANGO) += tango
machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U300) += u300
machine-$(CONFIG_ARCH_U8500) += ux500
machine-$(CONFIG_ARCH_VERSATILE) += versatile
machine-$(CONFIG_ARCH_VEXPRESS) += vexpress
machine-$(CONFIG_ARCH_VT8500) += vt8500
machine-$(CONFIG_ARCH_ZX) += zx
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_PLAT_SPEAR) += spear

16
arch/arm/boot/dts/Makefile
View File

@ -74,10 +74,6 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
at91-sama5d4_xplained.dtb \
at91-sama5d4ek.dtb \
at91-vinco.dtb
dtb-$(CONFIG_ARCH_ATLAS6) += \
atlas6-evb.dtb
dtb-$(CONFIG_ARCH_ATLAS7) += \
atlas7-evb.dtb
dtb-$(CONFIG_ARCH_AXXIA) += \
axm5516-amarillo.dtb
dtb-$(CONFIG_ARCH_BCM2835) += \
@ -177,8 +173,6 @@ dtb-$(CONFIG_ARCH_DAVINCI) += \
da850-lego-ev3.dtb
dtb-$(CONFIG_ARCH_DIGICOLOR) += \
cx92755_equinox.dtb
dtb-$(CONFIG_ARCH_EFM32) += \
efm32gg-dk3750.dtb
dtb-$(CONFIG_ARCH_EXYNOS3) += \
exynos3250-artik5-eval.dtb \
exynos3250-monk.dtb \
@ -888,11 +882,6 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \
owl-s500-labrador-base-m.dtb \
owl-s500-roseapplepi.dtb \
owl-s500-sparky.dtb
dtb-$(CONFIG_ARCH_PICOXCELL) += \
picoxcell-pc7302-pc3x2.dtb \
picoxcell-pc7302-pc3x3.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
dtb-$(CONFIG_ARCH_PXA) += \
pxa300-raumfeld-connector.dtb \
pxa300-raumfeld-controller.dtb \
@ -1232,8 +1221,6 @@ dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-cubieboard4.dtb
dtb-$(CONFIG_MACH_SUNIV) += \
suniv-f1c100s-licheepi-nano.dtb
dtb-$(CONFIG_ARCH_TANGO) += \
tango4-vantage-1172.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-acer-a500-picasso.dtb \
tegra20-harmony.dtb \
@ -1268,8 +1255,6 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
tegra124-nyan-big.dtb \
tegra124-nyan-blaze.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ARCH_U300) += \
ste-u300.dtb
dtb-$(CONFIG_ARCH_U8500) += \
ste-snowball.dtb \
ste-hrefprev60-stuib.dtb \
@ -1398,7 +1383,6 @@ dtb-$(CONFIG_ARCH_MSTARV7) += \
mstar-infinity2m-ssd202d-ssd201htv2.dtb \
mstar-infinity3-msc313e-breadbee.dtb \
mstar-mercury5-ssc8336n-midrived08.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-ast2600-evb.dtb \

78
arch/arm/boot/dts/atlas6-evb.dts
View File

@ -1,78 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DTS file for CSR SiRFatlas6 Evaluation Board
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
/dts-v1/;
/include/ "atlas6.dtsi"
/ {
model = "CSR SiRFatlas6 Evaluation Board";
compatible = "sirf,atlas6-cb", "sirf,atlas6";
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>;
};
axi {
peri-iobg {
uart@b0060000 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>;
};
spi@b00d0000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_a>;
spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
spi@b0170000 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
};
i2c0: i2c@b00e0000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
lcd@40 {
compatible = "sirf,lcd";
reg = <0x40>;
};
};
};
disp-iobg {
lcd@90010000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&lcd_24pins_a>;
};
};
};
display: display@0 {
panels {
panel0: panel@0 {
panel-name = "Innolux TFT";
hactive = <800>;
vactive = <480>;
left_margin = <20>;
right_margin = <234>;
upper_margin = <3>;
lower_margin = <41>;
hsync_len = <3>;
vsync_len = <2>;
pixclock = <33264000>;
sync = <3>;
timing = <0x88>;
};
};
};
};

800
arch/arm/boot/dts/atlas6.dtsi
View File

@ -1,800 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DTS file for CSR SiRFatlas6 SoC
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
/ {
compatible = "sirf,atlas6";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
/* from bootloader */
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
clocks = <&clks 12>;
operating-points = <
/* kHz uV */
200000 1025000
400000 1025000
600000 1050000
800000 1100000
>;
clock-latency = <150000>;
};
};
arm-pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <29>;
};
axi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x40000000 0x40000000 0x80000000>;
intc: interrupt-controller@80020000 {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "sirf,prima2-intc";
reg = <0x80020000 0x1000>;
};
sys-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x88000000 0x88000000 0x40000>;
clks: clock-controller@88000000 {
compatible = "sirf,atlas6-clkc";
reg = <0x88000000 0x1000>;
interrupts = <3>;
#clock-cells = <1>;
};
rstc: reset-controller@88010000 {
compatible = "sirf,prima2-rstc";
reg = <0x88010000 0x1000>;
#reset-cells = <1>;
};
rsc-controller@88020000 {
compatible = "sirf,prima2-rsc";
reg = <0x88020000 0x1000>;
};
cphifbg@88030000 {
compatible = "sirf,prima2-cphifbg";
reg = <0x88030000 0x1000>;
clocks = <&clks 42>;
};
};
mem-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x90000000 0x90000000 0x10000>;
memory-controller@90000000 {
compatible = "sirf,prima2-memc";
reg = <0x90000000 0x2000>;
interrupts = <27>;
clocks = <&clks 5>;
};
memc-monitor {
compatible = "sirf,prima2-memcmon";
reg = <0x90002000 0x200>;
interrupts = <4>;
clocks = <&clks 32>;
};
};
disp-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x90010000 0x90010000 0x30000>;
lcd@90010000 {
compatible = "sirf,prima2-lcd";
reg = <0x90010000 0x20000>;
interrupts = <30>;
clocks = <&clks 34>;
display=<&display>;
/* later transfer to pwm */
bl-gpio = <&gpio 7 0>;
default-panel = <&panel0>;
};
vpp@90020000 {
compatible = "sirf,prima2-vpp";
reg = <0x90020000 0x10000>;
interrupts = <31>;
clocks = <&clks 35>;
resets = <&rstc 6>;
};
};
graphics-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x98000000 0x98000000 0x8000000>;
graphics@98000000 {
compatible = "powervr,sgx510";
reg = <0x98000000 0x8000000>;
interrupts = <6>;
clocks = <&clks 32>;
};
};
graphics2d-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xa0000000 0xa0000000 0x8000000>;
ble@a0000000 {
compatible = "sirf,atlas6-ble";
reg = <0xa0000000 0x2000>;
interrupts = <5>;
clocks = <&clks 33>;
};
};
dsp-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xa8000000 0xa8000000 0x2000000>;
dspif@a8000000 {
compatible = "sirf,prima2-dspif";
reg = <0xa8000000 0x10000>;
interrupts = <9>;
resets = <&rstc 1>;
};
gps@a8010000 {
compatible = "sirf,prima2-gps";
reg = <0xa8010000 0x10000>;
interrupts = <7>;
clocks = <&clks 9>;
resets = <&rstc 2>;
};
dsp@a9000000 {
compatible = "sirf,prima2-dsp";
reg = <0xa9000000 0x1000000>;
interrupts = <8>;
clocks = <&clks 8>;
resets = <&rstc 0>;
};
};
peri-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xb0000000 0xb0000000 0x180000>,
<0x56000000 0x56000000 0x1b00000>;
timer@b0020000 {
compatible = "sirf,prima2-tick";
reg = <0xb0020000 0x1000>;
interrupts = <0>;
clocks = <&clks 11>;
};
nand@b0030000 {
compatible = "sirf,prima2-nand";
reg = <0xb0030000 0x10000>;
interrupts = <41>;
clocks = <&clks 26>;
};
audio@b0040000 {
compatible = "sirf,prima2-audio";
reg = <0xb0040000 0x10000>;
interrupts = <35>;
clocks = <&clks 27>;
};
uart0: uart@b0050000 {
cell-index = <0>;
compatible = "sirf,prima2-uart";
reg = <0xb0050000 0x1000>;
interrupts = <17>;
fifosize = <128>;
clocks = <&clks 13>;
dmas = <&dmac1 5>, <&dmac0 2>;
dma-names = "rx", "tx";
};
uart1: uart@b0060000 {
cell-index = <1>;
compatible = "sirf,prima2-uart";
reg = <0xb0060000 0x1000>;
interrupts = <18>;
fifosize = <32>;
clocks = <&clks 14>;
dma-names = "no-rx", "no-tx";
};
uart2: uart@b0070000 {
cell-index = <2>;
compatible = "sirf,prima2-uart";
reg = <0xb0070000 0x1000>;
interrupts = <19>;
fifosize = <128>;
clocks = <&clks 15>;
dmas = <&dmac0 6>, <&dmac0 7>;
dma-names = "rx", "tx";
};
usp0: usp@b0080000 {
cell-index = <0>;
compatible = "sirf,prima2-usp";
reg = <0xb0080000 0x10000>;
interrupts = <20>;
fifosize = <128>;
clocks = <&clks 28>;
dmas = <&dmac1 1>, <&dmac1 2>;
dma-names = "rx", "tx";
};
usp1: usp@b0090000 {
cell-index = <1>;
compatible = "sirf,prima2-usp";
reg = <0xb0090000 0x10000>;
interrupts = <21>;
fifosize = <128>;
clocks = <&clks 29>;
dmas = <&dmac0 14>, <&dmac0 15>;
dma-names = "rx", "tx";
};
dmac0: dma-controller@b00b0000 {
cell-index = <0>;
compatible = "sirf,prima2-dmac";
reg = <0xb00b0000 0x10000>;
interrupts = <12>;
clocks = <&clks 24>;
#dma-cells = <1>;
};
dmac1: dma-controller@b0160000 {
cell-index = <1>;
compatible = "sirf,prima2-dmac";
reg = <0xb0160000 0x10000>;
interrupts = <13>;
clocks = <&clks 25>;
#dma-cells = <1>;
};
vip@b00C0000 {
compatible = "sirf,prima2-vip";
reg = <0xb00C0000 0x10000>;
clocks = <&clks 31>;
interrupts = <14>;
sirf,vip-dma-rx-channel = <16>;
};
spi0: spi@b00d0000 {
cell-index = <0>;
compatible = "sirf,prima2-spi";
reg = <0xb00d0000 0x10000>;
interrupts = <15>;
sirf,spi-num-chipselects = <1>;
dmas = <&dmac1 9>,
<&dmac1 4>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 19>;
resets = <&rstc 26>;
status = "disabled";
};
spi1: spi@b0170000 {
cell-index = <1>;
compatible = "sirf,prima2-spi";
reg = <0xb0170000 0x10000>;
interrupts = <16>;
sirf,spi-num-chipselects = <1>;
dmas = <&dmac0 12>,
<&dmac0 13>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 20>;
resets = <&rstc 27>;
status = "disabled";
};
i2c0: i2c@b00e0000 {
cell-index = <0>;
compatible = "sirf,prima2-i2c";
reg = <0xb00e0000 0x10000>;
interrupts = <24>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 17>;
};
i2c1: i2c@b00f0000 {
cell-index = <1>;
compatible = "sirf,prima2-i2c";
reg = <0xb00f0000 0x10000>;
interrupts = <25>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 18>;
};
tsc@b0110000 {
compatible = "sirf,prima2-tsc";
reg = <0xb0110000 0x10000>;
interrupts = <33>;
clocks = <&clks 16>;
};
gpio: pinctrl@b0120000 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "sirf,atlas6-pinctrl";
reg = <0xb0120000 0x10000>;
interrupts = <43 44 45 46 47>;
gpio-controller;
interrupt-controller;
lcd_16pins_a: lcd0@0 {
lcd {
sirf,pins = "lcd_16bitsgrp";
sirf,function = "lcd_16bits";
};
};
lcd_18pins_a: lcd0@1 {
lcd {
sirf,pins = "lcd_18bitsgrp";
sirf,function = "lcd_18bits";
};
};
lcd_24pins_a: lcd0@2 {
lcd {
sirf,pins = "lcd_24bitsgrp";
sirf,function = "lcd_24bits";
};
};
lcdrom_pins_a: lcdrom0@0 {
lcd {
sirf,pins = "lcdromgrp";
sirf,function = "lcdrom";
};
};
uart0_pins_a: uart0@0 {
uart {
sirf,pins = "uart0grp";
sirf,function = "uart0";
};
};
uart0_noflow_pins_a: uart0@1 {
uart {
sirf,pins = "uart0_nostreamctrlgrp";
sirf,function = "uart0_nostreamctrl";
};
};
uart1_pins_a: uart1@0 {
uart {
sirf,pins = "uart1grp";
sirf,function = "uart1";
};
};
uart2_pins_a: uart2@0 {
uart {
sirf,pins = "uart2grp";
sirf,function = "uart2";
};
};
uart2_noflow_pins_a: uart2@1 {
uart {
sirf,pins = "uart2_nostreamctrlgrp";
sirf,function = "uart2_nostreamctrl";
};
};
spi0_pins_a: spi0@0 {
spi {
sirf,pins = "spi0grp";
sirf,function = "spi0";
};
};
spi1_pins_a: spi1@0 {
spi {
sirf,pins = "spi1grp";
sirf,function = "spi1";
};
};
i2c0_pins_a: i2c0@0 {
i2c {
sirf,pins = "i2c0grp";
sirf,function = "i2c0";
};
};
i2c1_pins_a: i2c1@0 {
i2c {
sirf,pins = "i2c1grp";
sirf,function = "i2c1";
};
};
pwm0_pins_a: pwm0@0 {
pwm {
sirf,pins = "pwm0grp";
sirf,function = "pwm0";
};
};
pwm1_pins_a: pwm1@0 {
pwm {
sirf,pins = "pwm1grp";
sirf,function = "pwm1";
};
};
pwm2_pins_a: pwm2@0 {
pwm {
sirf,pins = "pwm2grp";
sirf,function = "pwm2";
};
};
pwm3_pins_a: pwm3@0 {
pwm {
sirf,pins = "pwm3grp";
sirf,function = "pwm3";
};
};
pwm4_pins_a: pwm4@0 {
pwm {
sirf,pins = "pwm4grp";
sirf,function = "pwm4";
};
};
gps_pins_a: gps@0 {
gps {
sirf,pins = "gpsgrp";
sirf,function = "gps";
};
};
vip_pins_a: vip@0 {
vip {
sirf,pins = "vipgrp";
sirf,function = "vip";
};
};
sdmmc0_pins_a: sdmmc0@0 {
sdmmc0 {
sirf,pins = "sdmmc0grp";
sirf,function = "sdmmc0";
};
};
sdmmc1_pins_a: sdmmc1@0 {
sdmmc1 {
sirf,pins = "sdmmc1grp";
sirf,function = "sdmmc1";
};
};
sdmmc2_pins_a: sdmmc2@0 {
sdmmc2 {
sirf,pins = "sdmmc2grp";
sirf,function = "sdmmc2";
};
};
sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
sdmmc2_nowp {
sirf,pins = "sdmmc2_nowpgrp";
sirf,function = "sdmmc2_nowp";
};
};
sdmmc3_pins_a: sdmmc3@0 {
sdmmc3 {
sirf,pins = "sdmmc3grp";
sirf,function = "sdmmc3";
};
};
sdmmc5_pins_a: sdmmc5@0 {
sdmmc5 {
sirf,pins = "sdmmc5grp";
sirf,function = "sdmmc5";
};
};
i2s_mclk_pins_a: i2s_mclk@0 {
i2s_mclk {
sirf,pins = "i2smclkgrp";
sirf,function = "i2s_mclk";
};
};
i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
i2s_ext_clk_input {
sirf,pins = "i2s_ext_clk_inputgrp";
sirf,function = "i2s_ext_clk_input";
};
};
i2s_pins_a: i2s@0 {
i2s {
sirf,pins = "i2sgrp";
sirf,function = "i2s";
};
};
i2s_no_din_pins_a: i2s_no_din@0 {
i2s_no_din {
sirf,pins = "i2s_no_dingrp";
sirf,function = "i2s_no_din";
};
};
i2s_6chn_pins_a: i2s_6chn@0 {
i2s_6chn {
sirf,pins = "i2s_6chngrp";
sirf,function = "i2s_6chn";
};
};
ac97_pins_a: ac97@0 {
ac97 {
sirf,pins = "ac97grp";
sirf,function = "ac97";
};
};
nand_pins_a: nand@0 {
nand {
sirf,pins = "nandgrp";
sirf,function = "nand";
};
};
usp0_pins_a: usp0@0 {
usp0 {
sirf,pins = "usp0grp";
sirf,function = "usp0";
};
};
usp0_uart_nostreamctrl_pins_a: usp0@1 {
usp0 {
sirf,pins = "usp0_uart_nostreamctrl_grp";
sirf,function = "usp0_uart_nostreamctrl";
};
};
usp0_only_utfs_pins_a: usp0@2 {
usp0 {
sirf,pins = "usp0_only_utfs_grp";
sirf,function = "usp0_only_utfs";
};
};
usp0_only_urfs_pins_a: usp0@3 {
usp0 {
sirf,pins = "usp0_only_urfs_grp";
sirf,function = "usp0_only_urfs";
};
};
usp1_pins_a: usp1@0 {
usp1 {
sirf,pins = "usp1grp";
sirf,function = "usp1";
};
};
usp1_uart_nostreamctrl_pins_a: usp1@1 {
usp1 {
sirf,pins = "usp1_uart_nostreamctrl_grp";
sirf,function = "usp1_uart_nostreamctrl";
};
};
usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
usb0_upli_drvbus {
sirf,pins = "usb0_upli_drvbusgrp";
sirf,function = "usb0_upli_drvbus";
};
};
usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
usb1_utmi_drvbus {
sirf,pins = "usb1_utmi_drvbusgrp";
sirf,function = "usb1_utmi_drvbus";
};
};
usb1_dp_dn_pins_a: usb1_dp_dn@0 {
usb1_dp_dn {
sirf,pins = "usb1_dp_dngrp";
sirf,function = "usb1_dp_dn";
};
};
uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
uart1_route_io_usb1 {
sirf,pins = "uart1_route_io_usb1grp";
sirf,function = "uart1_route_io_usb1";
};
};
warm_rst_pins_a: warm_rst@0 {
warm_rst {
sirf,pins = "warm_rstgrp";
sirf,function = "warm_rst";
};
};
pulse_count_pins_a: pulse_count@0 {
pulse_count {
sirf,pins = "pulse_countgrp";
sirf,function = "pulse_count";
};
};
cko0_pins_a: cko0@0 {
cko0 {
sirf,pins = "cko0grp";
sirf,function = "cko0";
};
};
cko1_pins_a: cko1@0 {
cko1 {
sirf,pins = "cko1grp";
sirf,function = "cko1";
};
};
};
pwm@b0130000 {
compatible = "sirf,prima2-pwm";
reg = <0xb0130000 0x10000>;
clocks = <&clks 21>;
};
efusesys@b0140000 {
compatible = "sirf,prima2-efuse";
reg = <0xb0140000 0x10000>;
clocks = <&clks 22>;
};
pulsec@b0150000 {
compatible = "sirf,prima2-pulsec";
reg = <0xb0150000 0x10000>;
interrupts = <48>;
clocks = <&clks 23>;
};
pci-iobg {
compatible = "sirf,prima2-pciiobg", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x56000000 0x56000000 0x1b00000>;
sd0: sdhci@56000000 {
cell-index = <0>;
compatible = "sirf,prima2-sdhc";
reg = <0x56000000 0x100000>;
interrupts = <38>;
bus-width = <8>;
clocks = <&clks 36>;
};
sd1: sdhci@56100000 {
cell-index = <1>;
compatible = "sirf,prima2-sdhc";
reg = <0x56100000 0x100000>;
interrupts = <38>;
status = "disabled";
bus-width = <4>;
clocks = <&clks 36>;
};
sd2: sdhci@56200000 {
cell-index = <2>;
compatible = "sirf,prima2-sdhc";
reg = <0x56200000 0x100000>;
interrupts = <23>;
status = "disabled";
bus-width = <4>;
clocks = <&clks 37>;
};
sd3: sdhci@56300000 {
cell-index = <3>;
compatible = "sirf,prima2-sdhc";
reg = <0x56300000 0x100000>;
interrupts = <23>;
status = "disabled";
bus-width = <4>;
clocks = <&clks 37>;
};
sd5: sdhci@56500000 {
cell-index = <5>;
compatible = "sirf,prima2-sdhc";
reg = <0x56500000 0x100000>;
interrupts = <39>;
status = "disabled";
bus-width = <4>;
clocks = <&clks 38>;
};
pci-copy@57900000 {
compatible = "sirf,prima2-pcicp";
reg = <0x57900000 0x100000>;
interrupts = <40>;
};
rom-interface@57a00000 {
compatible = "sirf,prima2-romif";
reg = <0x57a00000 0x100000>;
};
};
};
rtc-iobg {
compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80030000 0x10000>;
gpsrtc@1000 {
compatible = "sirf,prima2-gpsrtc";
reg = <0x1000 0x1000>;
interrupts = <55 56 57>;
};
sysrtc@2000 {
compatible = "sirf,prima2-sysrtc";
reg = <0x2000 0x1000>;
interrupts = <52 53 54>;
};
minigpsrtc@2000 {
compatible = "sirf,prima2-minigpsrtc";
reg = <0x2000 0x1000>;
interrupts = <54>;
};
pwrc@3000 {
compatible = "sirf,prima2-pwrc";
reg = <0x3000 0x1000>;
interrupts = <32>;
};
};
uus-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xb8000000 0xb8000000 0x40000>;
usb0: usb@b00e0000 {
compatible = "chipidea,ci13611a-prima2";
reg = <0xb8000000 0x10000>;
interrupts = <10>;
clocks = <&clks 40>;
};
usb1: usb@b00f0000 {
compatible = "chipidea,ci13611a-prima2";
reg = <0xb8010000 0x10000>;
interrupts = <11>;
clocks = <&clks 41>;
};
security@b00f0000 {
compatible = "sirf,prima2-security";
reg = <0xb8030000 0x10000>;
interrupts = <42>;
clocks = <&clks 7>;
};
};
};
};

127
arch/arm/boot/dts/atlas7-evb.dts
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DTS file for CSR SiRFatlas7 Evaluation Board
*
* Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
/dts-v1/;
/include/ "atlas7.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "CSR SiRFatlas7 Evaluation Board";
compatible = "sirf,atlas7-cb", "sirf,atlas7";
chosen {
bootargs = "console=ttySiRF1,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
vpp_reserved: vpp_mem@5e800000 {
compatible = "sirf,reserved-memory";
reg = <0x5e800000 0x800000>;
};
nanddisk_reserved: nanddisk@46000000 {
reg = <0x46000000 0x200000>;
no-map;
};
};
noc {
mediam {
nand@17050000 {
memory-region = <&nanddisk_reserved>;
};
};
gnssm {
spi1: spi@18200000 {
status = "okay";
spiflash: macronix@0{
status = "okay";
compatible = "macronix,mx25l6405d";
reg = <0>;
spi-max-frequency = <37500000>;
spi-cpha;
spi-cpol;
#address-cells = <1>;
#size-cells = <1>;
partitions@0 {
label = "myspiboot";
reg = <0x0 0x800000>;
};
};
};
};
btm {
uart6: uart@11000000 {
status = "okay";
uart-has-rtscts;
};
};
disp-iobg {
vpp@13110000 {
memory-region = <&vpp_reserved>;
};
};
display0: display@0 {
compatible = "lvds-panel";
source = "lvds.0";
bl-gpios = <&gpio_1 63 0>;
data-lines = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <60000000>;
hactive = <1024>;
vactive = <600>;
hfront-porch = <220>;
hback-porch = <100>;
hsync-len = <1>;
vback-porch = <10>;
vfront-porch = <25>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
gpio_keys {
compatible = "gpio-keys";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
rearview_key {
label = "rearview key";
linux,code = <KEY_CAMERA>;
gpios = <&gpio_1 3 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
};
};
};

1955
arch/arm/boot/dts/atlas7.dtsi
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88
arch/arm/boot/dts/efm32gg-dk3750.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Device tree for EFM32GG-DK3750 development board.
*
* Documentation available from
* http://www.silabs.com/Support%20Documents/TechnicalDocs/efm32gg-dk3750-ug.pdf
*/
/dts-v1/;
#include "efm32gg.dtsi"
/ {
model = "Energy Micro Giant Gecko Development Kit";
compatible = "efm32,dk3750";
chosen {
bootargs = "console=ttyefm4,115200 init=/linuxrc ignore_loglevel ihash_entries=64 dhash_entries=64 earlyprintk uclinux.physaddr=0x8c400000 root=/dev/mtdblock0";
};
memory@88000000 {
device_type = "memory";
reg = <0x88000000 0x400000>;
};
soc {
adc@40002000 {
status = "ok";
};
i2c@4000a000 {
energymicro,location = <3>;
status = "ok";
temp@48 {
compatible = "st,stds75";
reg = <0x48>;
};
eeprom@50 {
compatible = "microchip,24c02", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
spi0: spi@4000c000 { /* USART0 */
cs-gpios = <&gpio 68 1>; // E4
energymicro,location = <1>;
status = "ok";
microsd@0 {
compatible = "mmc-spi-slot";
spi-max-frequency = <100000>;
voltage-ranges = <3200 3400>;
broken-cd;
reg = <0>;
};
};
spi1: spi@4000c400 { /* USART1 */
cs-gpios = <&gpio 51 1>; // D3
energymicro,location = <1>;
status = "ok";
ks8851@0 {
compatible = "ks8851";
spi-max-frequency = <6000000>;
reg = <0>;
interrupt-parent = <&boardfpga>;
interrupts = <4>;
};
};
uart4: uart@4000e400 { /* UART1 */
energymicro,location = <2>;
status = "ok";
};
boardfpga: boardfpga@80000000 {
compatible = "efm32board";
reg = <0x80000000 0x400>;
irq-gpios = <&gpio 64 1>;
interrupt-controller;
#interrupt-cells = <1>;
status = "ok";
};
};
};

177
arch/arm/boot/dts/efm32gg.dtsi
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// SPDX-License-Identifier: GPL-2.0
/*
* Device tree for Energy Micro EFM32 Giant Gecko SoC.
*
* Documentation available from
* http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf
*/
#include "armv7-m.dtsi"
#include "dt-bindings/clock/efm32-cmu.h"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
};
soc {
adc: adc@40002000 {
compatible = "energymicro,efm32-adc";
reg = <0x40002000 0x400>;
interrupts = <7>;
clocks = <&cmu clk_HFPERCLKADC0>;
status = "disabled";
};
gpio: gpio@40006000 {
compatible = "energymicro,efm32-gpio";
reg = <0x40006000 0x1000>;
interrupts = <1 11>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&cmu clk_HFPERCLKGPIO>;
status = "ok";
};
i2c0: i2c@4000a000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "energymicro,efm32-i2c";
reg = <0x4000a000 0x400>;
interrupts = <9>;
clocks = <&cmu clk_HFPERCLKI2C0>;
clock-frequency = <100000>;
status = "disabled";
};
i2c1: i2c@4000a400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "energymicro,efm32-i2c";
reg = <0x4000a400 0x400>;
interrupts = <10>;
clocks = <&cmu clk_HFPERCLKI2C1>;
clock-frequency = <100000>;
status = "disabled";
};
spi0: spi@4000c000 { /* USART0 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "energymicro,efm32-spi";
reg = <0x4000c000 0x400>;
interrupts = <3 4>;
clocks = <&cmu clk_HFPERCLKUSART0>;
status = "disabled";
};
spi1: spi@4000c400 { /* USART1 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "energymicro,efm32-spi";
reg = <0x4000c400 0x400>;
interrupts = <15 16>;
clocks = <&cmu clk_HFPERCLKUSART1>;
status = "disabled";
};
spi2: spi@4000c800 { /* USART2 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "energymicro,efm32-spi";
reg = <0x4000c800 0x400>;
interrupts = <18 19>;
clocks = <&cmu clk_HFPERCLKUSART2>;
status = "disabled";
};
uart0: uart@4000c000 { /* USART0 */
compatible = "energymicro,efm32-uart";
reg = <0x4000c000 0x400>;
interrupts = <3 4>;
clocks = <&cmu clk_HFPERCLKUSART0>;
status = "disabled";
};
uart1: uart@4000c400 { /* USART1 */
compatible = "energymicro,efm32-uart";
reg = <0x4000c400 0x400>;
interrupts = <15 16>;
clocks = <&cmu clk_HFPERCLKUSART1>;
status = "disabled";
};
uart2: uart@4000c800 { /* USART2 */
compatible = "energymicro,efm32-uart";
reg = <0x4000c800 0x400>;
interrupts = <18 19>;
clocks = <&cmu clk_HFPERCLKUSART2>;
status = "disabled";
};
uart3: uart@4000e000 { /* UART0 */
compatible = "energymicro,efm32-uart";
reg = <0x4000e000 0x400>;
interrupts = <20 21>;
clocks = <&cmu clk_HFPERCLKUART0>;
status = "disabled";
};
uart4: uart@4000e400 { /* UART1 */
compatible = "energymicro,efm32-uart";
reg = <0x4000e400 0x400>;
interrupts = <22 23>;
clocks = <&cmu clk_HFPERCLKUART1>;
status = "disabled";
};
timer0: timer@40010000 {
compatible = "energymicro,efm32-timer";
reg = <0x40010000 0x400>;
interrupts = <2>;
clocks = <&cmu clk_HFPERCLKTIMER0>;
};
timer1: timer@40010400 {
compatible = "energymicro,efm32-timer";
reg = <0x40010400 0x400>;
interrupts = <12>;
clocks = <&cmu clk_HFPERCLKTIMER1>;
};
timer2: timer@40010800 {
compatible = "energymicro,efm32-timer";
reg = <0x40010800 0x400>;
interrupts = <13>;
clocks = <&cmu clk_HFPERCLKTIMER2>;
};
timer3: timer@40010c00 {
compatible = "energymicro,efm32-timer";
reg = <0x40010c00 0x400>;
interrupts = <14>;
clocks = <&cmu clk_HFPERCLKTIMER3>;
};
cmu: cmu@400c8000 {
compatible = "efm32gg,cmu";
reg = <0x400c8000 0x400>;
interrupts = <32>;
#clock-cells = <1>;
};
};
};

243
arch/arm/boot/dts/picoxcell-pc3x2.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Picochip, Jamie Iles
*/
/ {
model = "Picochip picoXcell PC3X2";
compatible = "picochip,pc3x2";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <0>;
#size-cells = <0>;
cpu {
compatible = "arm,arm1176jz-s";
device_type = "cpu";
clock-frequency = <400000000>;
d-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-line-size = <32>;
i-cache-size = <32768>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
pclk: clock@0 {
compatible = "fixed-clock";
clock-outputs = "bus", "pclk";
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
};
paxi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x80000000 0x400000>;
emac: gem@30000 {
compatible = "cadence,gem";
reg = <0x30000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <31>;
};
dmac1: dmac@40000 {
compatible = "snps,dw-dmac";
reg = <0x40000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <25>;
};
dmac2: dmac@50000 {
compatible = "snps,dw-dmac";
reg = <0x50000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <26>;
};
vic0: interrupt-controller@60000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0x60000 0x1000>;
#interrupt-cells = <1>;
};
vic1: interrupt-controller@64000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0x64000 0x1000>;
#interrupt-cells = <1>;
};
fuse: picoxcell-fuse@80000 {
compatible = "picoxcell,fuse-pc3x2";
reg = <0x80000 0x10000>;
};
ssi: picoxcell-spi@90000 {
compatible = "picoxcell,spi";
reg = <0x90000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <10>;
};
ipsec: spacc@100000 {
compatible = "picochip,spacc-ipsec";
reg = <0x100000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <24>;
ref-clock = <&pclk>, "ref";
};
srtp: spacc@140000 {
compatible = "picochip,spacc-srtp";
reg = <0x140000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <23>;
};
l2_engine: spacc@180000 {
compatible = "picochip,spacc-l2";
reg = <0x180000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <22>;
ref-clock = <&pclk>, "ref";
};
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x200000 0x80000>;
rtc0: rtc@0 {
compatible = "picochip,pc3x2-rtc";
clock-freq = <200000000>;
reg = <0x00000 0xf>;
interrupt-parent = <&vic1>;
interrupts = <8>;
};
timer0: timer@10000 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <4>;
clock-freq = <200000000>;
reg = <0x10000 0x14>;
};
timer1: timer@10014 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <5>;
clock-freq = <200000000>;
reg = <0x10014 0x14>;
};
timer2: timer@10028 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <6>;
clock-freq = <200000000>;
reg = <0x10028 0x14>;
};
timer3: timer@1003c {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <7>;
clock-freq = <200000000>;
reg = <0x1003c 0x14>;
};
gpio: gpio@20000 {
compatible = "snps,dw-apb-gpio";
reg = <0x20000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
banka: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
gpio-generic,nr-gpio = <8>;
regoffset-dat = <0x50>;
regoffset-set = <0x00>;
regoffset-dirout = <0x04>;
};
bankb: gpio-controller@1 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
gpio-generic,nr-gpio = <8>;
regoffset-dat = <0x54>;
regoffset-set = <0x0c>;
regoffset-dirout = <0x10>;
};
};
uart0: uart@30000 {
compatible = "snps,dw-apb-uart";
reg = <0x30000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <10>;
clock-frequency = <3686400>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart1: uart@40000 {
compatible = "snps,dw-apb-uart";
reg = <0x40000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <9>;
clock-frequency = <3686400>;
reg-shift = <2>;
reg-io-width = <4>;
};
wdog: watchdog@50000 {
compatible = "snps,dw-apb-wdg";
reg = <0x50000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <11>;
bus-clock = <&pclk>, "bus";
};
};
};
rwid-axi {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
ebi@50000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x40000000 0x08000000
1 0 0x48000000 0x08000000
2 0 0x50000000 0x08000000
3 0 0x58000000 0x08000000>;
};
axi2pico@c0000000 {
compatible = "picochip,axi2pico-pc3x2";
reg = <0xc0000000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <13 14 15 16 17 18 19 20 21>;
};
};
};

355
arch/arm/boot/dts/picoxcell-pc3x3.dtsi
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Picochip, Jamie Iles
*/
/ {
model = "Picochip picoXcell PC3X3";
compatible = "picochip,pc3x3";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <0>;
#size-cells = <0>;
cpu {
compatible = "arm,arm1176jz-s";
device_type = "cpu";
cpu-clock = <&arm_clk>, "cpu";
d-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-line-size = <32>;
i-cache-size = <32768>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
clkgate: clkgate@800a0048 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x800a0048 4>;
compatible = "picochip,pc3x3-clk-gate";
tzprot_clk: clock@0 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <0>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
spi_clk: clock@1 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <1>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
dmac0_clk: clock@2 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <2>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
dmac1_clk: clock@3 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <3>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
ebi_clk: clock@4 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <4>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
ipsec_clk: clock@5 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <5>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
l2_clk: clock@6 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <6>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
trng_clk: clock@7 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <7>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
fuse_clk: clock@8 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <8>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
otp_clk: clock@9 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <9>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
};
arm_clk: clock@11 {
compatible = "picochip,pc3x3-pll";
reg = <0x800a0050 0x8>;
picochip,min-freq = <140000000>;
picochip,max-freq = <700000000>;
ref-clock = <&ref_clk>, "ref";
clock-outputs = "cpu";
};
pclk: clock@12 {
compatible = "fixed-clock";
clock-outputs = "bus", "pclk";
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
};
paxi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x80000000 0x400000>;
emac: gem@30000 {
compatible = "cadence,gem";
reg = <0x30000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <31>;
};
dmac1: dmac@40000 {
compatible = "snps,dw-dmac";
reg = <0x40000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <25>;
};
dmac2: dmac@50000 {
compatible = "snps,dw-dmac";
reg = <0x50000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <26>;
};
vic0: interrupt-controller@60000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0x60000 0x1000>;
#interrupt-cells = <1>;
};
vic1: interrupt-controller@64000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0x64000 0x1000>;
#interrupt-cells = <1>;
};
fuse: picoxcell-fuse@80000 {
compatible = "picoxcell,fuse-pc3x3";
reg = <0x80000 0x10000>;
};
ssi: picoxcell-spi@90000 {
compatible = "picoxcell,spi";
reg = <0x90000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <10>;
};
ipsec: spacc@100000 {
compatible = "picochip,spacc-ipsec";
reg = <0x100000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <24>;
ref-clock = <&ipsec_clk>, "ref";
};
srtp: spacc@140000 {
compatible = "picochip,spacc-srtp";
reg = <0x140000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <23>;
};
l2_engine: spacc@180000 {
compatible = "picochip,spacc-l2";
reg = <0x180000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <22>;
ref-clock = <&l2_clk>, "ref";
};
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x200000 0x80000>;
rtc0: rtc@0 {
compatible = "picochip,pc3x2-rtc";
clock-freq = <200000000>;
reg = <0x00000 0xf>;
interrupt-parent = <&vic0>;
interrupts = <8>;
};
timer0: timer@10000 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <4>;
clock-freq = <200000000>;
reg = <0x10000 0x14>;
};
timer1: timer@10014 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <5>;
clock-freq = <200000000>;
reg = <0x10014 0x14>;
};
gpio: gpio@20000 {
compatible = "snps,dw-apb-gpio";
reg = <0x20000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
banka: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
gpio-generic,nr-gpio = <8>;
regoffset-dat = <0x50>;
regoffset-set = <0x00>;
regoffset-dirout = <0x04>;
};
bankb: gpio-controller@1 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
gpio-generic,nr-gpio = <16>;
regoffset-dat = <0x54>;
regoffset-set = <0x0c>;
regoffset-dirout = <0x10>;
};
bankd: gpio-controller@2 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
gpio-generic,nr-gpio = <30>;
regoffset-dat = <0x5c>;
regoffset-set = <0x24>;
regoffset-dirout = <0x28>;
};
};
uart0: uart@30000 {
compatible = "snps,dw-apb-uart";
reg = <0x30000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <10>;
clock-frequency = <3686400>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart1: uart@40000 {
compatible = "snps,dw-apb-uart";
reg = <0x40000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <9>;
clock-frequency = <3686400>;
reg-shift = <2>;
reg-io-width = <4>;
};
wdog: watchdog@50000 {
compatible = "snps,dw-apb-wdg";
reg = <0x50000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <11>;
bus-clock = <&pclk>, "bus";
};
timer2: timer@60000 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <6>;
clock-freq = <200000000>;
reg = <0x60000 0x14>;
};
timer3: timer@60014 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <7>;
clock-freq = <200000000>;
reg = <0x60014 0x14>;
};
};
};
rwid-axi {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
ebi@50000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x40000000 0x08000000
1 0 0x48000000 0x08000000
2 0 0x50000000 0x08000000
3 0 0x58000000 0x08000000>;
};
axi2pico@c0000000 {
compatible = "picochip,axi2pico-pc3x3";
reg = <0xc0000000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <13 14 15 16 17 18 19 20 21>;
};
otp@ffff8000 {
compatible = "picochip,otp-pc3x3";
reg = <0xffff8000 0x8000>;
};
};
};

78
arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
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@ -1,78 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Picochip, Jamie Iles
*/
/dts-v1/;
/include/ "picoxcell-pc3x2.dtsi"
/ {
model = "Picochip PC7302 (PC3X2)";
compatible = "picochip,pc7302-pc3x2", "picochip,pc3x2";
memory {
device_type = "memory";
reg = <0x0 0x08000000>;
};
chosen {
stdout-path = &uart0;
};
clocks {
ref_clk: clock@1 {
compatible = "fixed-clock";
clock-outputs = "ref";
clock-frequency = <20000000>;
};
};
rwid-axi {
ebi@50000000 {
nand: gpio-nand@2,0 {
compatible = "gpio-control-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <2 0x0000 0x1000>;
bus-clock = <&pclk>, "bus";
gpio-control-nand,io-sync-reg =
<0x00000000 0x80220000>;
gpios = <&banka 1 0 /* rdy */
&banka 2 0 /* nce */
&banka 3 0 /* ale */
&banka 4 0 /* cle */
0 /* nwp */>;
boot@100000 {
label = "Boot";
reg = <0x100000 0x80000>;
};
redundant-boot@200000 {
label = "Redundant Boot";
reg = <0x200000 0x80000>;
};
boot-env@300000 {
label = "Boot Evironment";
reg = <0x300000 0x20000>;
};
redundant-boot-env@320000 {
label = "Redundant Boot Environment";
reg = <0x300000 0x20000>;
};
kernel@380000 {
label = "Kernel";
reg = <0x380000 0x800000>;
};
fs@b80000 {
label = "File System";
reg = <0xb80000 0xf480000>;
};
};
};
};
};

84
arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
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@ -1,84 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Picochip, Jamie Iles
*/
/dts-v1/;
/include/ "picoxcell-pc3x3.dtsi"
/ {
model = "Picochip PC7302 (PC3X3)";
compatible = "picochip,pc7302-pc3x3", "picochip,pc3x3";
memory {
device_type = "memory";
reg = <0x0 0x08000000>;
};
chosen {
stdout-path = &uart0;
};
clocks {
ref_clk: clock@10 {
compatible = "fixed-clock";
clock-outputs = "ref";
clock-frequency = <20000000>;
};
clkgate: clkgate@800a0048 {
clock@4 {
picochip,clk-no-disable;
};
};
};
rwid-axi {
ebi@50000000 {
nand: gpio-nand@2,0 {
compatible = "gpio-control-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <2 0x0000 0x1000>;
bus-clock = <&ebi_clk>, "bus";
gpio-control-nand,io-sync-reg =
<0x00000000 0x80220000>;
gpios = <&banka 1 0 /* rdy */
&banka 2 0 /* nce */
&banka 3 0 /* ale */
&banka 4 0 /* cle */
0 /* nwp */>;
boot@100000 {
label = "Boot";
reg = <0x100000 0x80000>;
};
redundant-boot@200000 {
label = "Redundant Boot";
reg = <0x200000 0x80000>;
};
boot-env@300000 {
label = "Boot Evironment";
reg = <0x300000 0x20000>;
};
redundant-boot-env@320000 {
label = "Redundant Boot Environment";
reg = <0x300000 0x20000>;
};
kernel@380000 {
label = "Kernel";
reg = <0x380000 0x800000>;
};
fs@b80000 {
label = "File System";
reg = <0xb80000 0xf480000>;
};
};
};
};
};

37
arch/arm/boot/dts/prima2-evb.dts
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@ -1,37 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DTS file for CSR SiRFprimaII Evaluation Board
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
/dts-v1/;
/include/ "prima2.dtsi"
/ {
model = "CSR SiRFprimaII Evaluation Board";
compatible = "sirf,prima2", "sirf,prima2-cb";
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>;
};
axi {
peri-iobg {
uart@b0060000 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>;
};
spi@b00d0000 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_a>;
};
spi@b0170000 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
};
};
};
};

838
arch/arm/boot/dts/prima2.dtsi
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@ -1,838 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DTS file for CSR SiRFprimaII SoC
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
/ {
compatible = "sirf,prima2";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
/* from bootloader */
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
clocks = <&clks 12>;
operating-points = <
/* kHz uV */
200000 1025000
400000 1025000
664000 1050000
800000 1100000
>;
clock-latency = <150000>;
};
};
arm-pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <29>;
};
axi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x40000000 0x40000000 0x80000000>;
cache-controller@80040000 {
compatible = "arm,pl310-cache";
reg = <0x80040000 0x1000>;
interrupts = <59>;
arm,tag-latency = <1 1 1>;
arm,data-latency = <1 1 1>;
arm,filter-ranges = <0 0x40000000>;
};
intc: interrupt-controller@80020000 {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "sirf,prima2-intc";
reg = <0x80020000 0x1000>;
};
sys-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x88000000 0x88000000 0x40000>;
clks: clock-controller@88000000 {
compatible = "sirf,prima2-clkc";
reg = <0x88000000 0x1000>;
interrupts = <3>;
#clock-cells = <1>;
};
rstc: reset-controller@88010000 {
compatible = "sirf,prima2-rstc";
reg = <0x88010000 0x1000>;
#reset-cells = <1>;
};
rsc-controller@88020000 {
compatible = "sirf,prima2-rsc";
reg = <0x88020000 0x1000>;
};
cphifbg@88030000 {
compatible = "sirf,prima2-cphifbg";
reg = <0x88030000 0x1000>;
clocks = <&clks 42>;
};
};
mem-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x90000000 0x90000000 0x10000>;
memory-controller@90000000 {
compatible = "sirf,prima2-memc";
reg = <0x90000000 0x2000>;
interrupts = <27>;
clocks = <&clks 5>;
};
memc-monitor {
compatible = "sirf,prima2-memcmon";
reg = <0x90002000 0x200>;
interrupts = <4>;
clocks = <&clks 32>;
};
};
disp-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x90010000 0x90010000 0x30000>;
display@90010000 {
compatible = "sirf,prima2-lcd";
reg = <0x90010000 0x20000>;
interrupts = <30>;
};
vpp@90020000 {
compatible = "sirf,prima2-vpp";
reg = <0x90020000 0x10000>;
interrupts = <31>;
clocks = <&clks 35>;
resets = <&rstc 6>;
};
};
graphics-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x98000000 0x98000000 0x8000000>;
graphics@98000000 {
compatible = "powervr,sgx531";
reg = <0x98000000 0x8000000>;
interrupts = <6>;
clocks = <&clks 32>;
};
};
multimedia-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xa0000000 0xa0000000 0x8000000>;
multimedia@a0000000 {
compatible = "sirf,prima2-video-codec";
reg = <0xa0000000 0x8000000>;
interrupts = <5>;
clocks = <&clks 33>;
};
};
dsp-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xa8000000 0xa8000000 0x2000000>;
dspif@a8000000 {
compatible = "sirf,prima2-dspif";
reg = <0xa8000000 0x10000>;
interrupts = <9>;
resets = <&rstc 1>;
};
gps@a8010000 {
compatible = "sirf,prima2-gps";
reg = <0xa8010000 0x10000>;
interrupts = <7>;
clocks = <&clks 9>;
resets = <&rstc 2>;
};
dsp@a9000000 {
compatible = "sirf,prima2-dsp";
reg = <0xa9000000 0x1000000>;
interrupts = <8>;
clocks = <&clks 8>;
resets = <&rstc 0>;
};
};
peri-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xb0000000 0xb0000000 0x180000>,
<0x56000000 0x56000000 0x1b00000>;
timer@b0020000 {
compatible = "sirf,prima2-tick";
reg = <0xb0020000 0x1000>;
interrupts = <0>;
clocks = <&clks 11>;
};
nand@b0030000 {
compatible = "sirf,prima2-nand";
reg = <0xb0030000 0x10000>;
interrupts = <41>;
clocks = <&clks 26>;
};
audio@b0040000 {
compatible = "sirf,prima2-audio";
reg = <0xb0040000 0x10000>;
interrupts = <35>;
clocks = <&clks 27>;
};
uart0: uart@b0050000 {
cell-index = <0>;
compatible = "sirf,prima2-uart";
reg = <0xb0050000 0x1000>;
interrupts = <17>;
fifosize = <128>;
clocks = <&clks 13>;
dmas = <&dmac1 5>, <&dmac0 2>;
dma-names = "rx", "tx";
};
uart1: uart@b0060000 {
cell-index = <1>;
compatible = "sirf,prima2-uart";
reg = <0xb0060000 0x1000>;
interrupts = <18>;
fifosize = <32>;
clocks = <&clks 14>;
};
uart2: uart@b0070000 {
cell-index = <2>;
compatible = "sirf,prima2-uart";
reg = <0xb0070000 0x1000>;
interrupts = <19>;
fifosize = <128>;
clocks = <&clks 15>;
dmas = <&dmac0 6>, <&dmac0 7>;
dma-names = "rx", "tx";
};
usp0: usp@b0080000 {
cell-index = <0>;
compatible = "sirf,prima2-usp";
reg = <0xb0080000 0x10000>;
interrupts = <20>;
fifosize = <128>;
clocks = <&clks 28>;
dmas = <&dmac1 1>, <&dmac1 2>;
dma-names = "rx", "tx";
};
usp1: usp@b0090000 {
cell-index = <1>;
compatible = "sirf,prima2-usp";
reg = <0xb0090000 0x10000>;
interrupts = <21>;
fifosize = <128>;
clocks = <&clks 29>;
dmas = <&dmac0 14>, <&dmac0 15>;
dma-names = "rx", "tx";
};
usp2: usp@b00a0000 {
cell-index = <2>;
compatible = "sirf,prima2-usp";
reg = <0xb00a0000 0x10000>;
interrupts = <22>;
fifosize = <128>;
clocks = <&clks 30>;
dmas = <&dmac0 10>, <&dmac0 11>;
dma-names = "rx", "tx";
};
dmac0: dma-controller@b00b0000 {
cell-index = <0>;
compatible = "sirf,prima2-dmac";
reg = <0xb00b0000 0x10000>;
interrupts = <12>;
clocks = <&clks 24>;
#dma-cells = <1>;
};
dmac1: dma-controller@b0160000 {
cell-index = <1>;
compatible = "sirf,prima2-dmac";
reg = <0xb0160000 0x10000>;
interrupts = <13>;
clocks = <&clks 25>;
#dma-cells = <1>;
};
vip@b00C0000 {
compatible = "sirf,prima2-vip";
reg = <0xb00C0000 0x10000>;
clocks = <&clks 31>;
interrupts = <14>;
sirf,vip-dma-rx-channel = <16>;
};
spi0: spi@b00d0000 {
cell-index = <0>;
compatible = "sirf,prima2-spi";
reg = <0xb00d0000 0x10000>;
interrupts = <15>;
sirf,spi-num-chipselects = <1>;
dmas = <&dmac1 9>,
<&dmac1 4>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 19>;
status = "disabled";
};
spi1: spi@b0170000 {
cell-index = <1>;
compatible = "sirf,prima2-spi";
reg = <0xb0170000 0x10000>;
interrupts = <16>;
sirf,spi-num-chipselects = <1>;
dmas = <&dmac0 12>,
<&dmac0 13>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 20>;
status = "disabled";
};
i2c0: i2c@b00e0000 {
cell-index = <0>;
compatible = "sirf,prima2-i2c";
reg = <0xb00e0000 0x10000>;
interrupts = <24>;
clocks = <&clks 17>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@b00f0000 {
cell-index = <1>;
compatible = "sirf,prima2-i2c";
reg = <0xb00f0000 0x10000>;
interrupts = <25>;
clocks = <&clks 18>;
#address-cells = <1>;
#size-cells = <0>;
};
tsc@b0110000 {
compatible = "sirf,prima2-tsc";
reg = <0xb0110000 0x10000>;
interrupts = <33>;
clocks = <&clks 16>;
};
gpio: pinctrl@b0120000 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "sirf,prima2-pinctrl";
reg = <0xb0120000 0x10000>;
interrupts = <43 44 45 46 47>;
gpio-controller;
interrupt-controller;
lcd_16pins_a: lcd0@0 {
lcd {
sirf,pins = "lcd_16bitsgrp";
sirf,function = "lcd_16bits";
};
};
lcd_18pins_a: lcd0@1 {
lcd {
sirf,pins = "lcd_18bitsgrp";
sirf,function = "lcd_18bits";
};
};
lcd_24pins_a: lcd0@2 {
lcd {
sirf,pins = "lcd_24bitsgrp";
sirf,function = "lcd_24bits";
};
};
lcdrom_pins_a: lcdrom0@0 {
lcd {
sirf,pins = "lcdromgrp";
sirf,function = "lcdrom";
};
};
uart0_pins_a: uart0@0 {
uart {
sirf,pins = "uart0grp";
sirf,function = "uart0";
};
};
uart0_noflow_pins_a: uart0@1 {
uart {
sirf,pins = "uart0_nostreamctrlgrp";
sirf,function = "uart0_nostreamctrl";
};
};
uart1_pins_a: uart1@0 {
uart {
sirf,pins = "uart1grp";
sirf,function = "uart1";
};
};
uart2_pins_a: uart2@0 {
uart {
sirf,pins = "uart2grp";
sirf,function = "uart2";
};
};
uart2_noflow_pins_a: uart2@1 {
uart {
sirf,pins = "uart2_nostreamctrlgrp";
sirf,function = "uart2_nostreamctrl";
};
};
spi0_pins_a: spi0@0 {
spi {
sirf,pins = "spi0grp";
sirf,function = "spi0";
};
};
spi1_pins_a: spi1@0 {
spi {
sirf,pins = "spi1grp";
sirf,function = "spi1";
};
};
i2c0_pins_a: i2c0@0 {
i2c {
sirf,pins = "i2c0grp";
sirf,function = "i2c0";
};
};
i2c1_pins_a: i2c1@0 {
i2c {
sirf,pins = "i2c1grp";
sirf,function = "i2c1";
};
};
pwm0_pins_a: pwm0@0 {
pwm {
sirf,pins = "pwm0grp";
sirf,function = "pwm0";
};
};
pwm1_pins_a: pwm1@0 {
pwm {
sirf,pins = "pwm1grp";
sirf,function = "pwm1";
};
};
pwm2_pins_a: pwm2@0 {
pwm {
sirf,pins = "pwm2grp";
sirf,function = "pwm2";
};
};
pwm3_pins_a: pwm3@0 {
pwm {
sirf,pins = "pwm3grp";
sirf,function = "pwm3";
};
};
gps_pins_a: gps@0 {
gps {
sirf,pins = "gpsgrp";
sirf,function = "gps";
};
};
vip_pins_a: vip@0 {
vip {
sirf,pins = "vipgrp";
sirf,function = "vip";
};
};
sdmmc0_pins_a: sdmmc0@0 {
sdmmc0 {
sirf,pins = "sdmmc0grp";
sirf,function = "sdmmc0";
};
};
sdmmc1_pins_a: sdmmc1@0 {
sdmmc1 {
sirf,pins = "sdmmc1grp";
sirf,function = "sdmmc1";
};
};
sdmmc2_pins_a: sdmmc2@0 {
sdmmc2 {
sirf,pins = "sdmmc2grp";
sirf,function = "sdmmc2";
};
};
sdmmc3_pins_a: sdmmc3@0 {
sdmmc3 {
sirf,pins = "sdmmc3grp";
sirf,function = "sdmmc3";
};
};
sdmmc4_pins_a: sdmmc4@0 {
sdmmc4 {
sirf,pins = "sdmmc4grp";
sirf,function = "sdmmc4";
};
};
sdmmc5_pins_a: sdmmc5@0 {
sdmmc5 {
sirf,pins = "sdmmc5grp";
sirf,function = "sdmmc5";
};
};
i2s_mclk_pins_a: i2s_mclk@0 {
i2s_mclk {
sirf,pins = "i2smclkgrp";
sirf,function = "i2s_mclk";
};
};
i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
i2s_ext_clk_input {
sirf,pins = "i2s_ext_clk_inputgrp";
sirf,function = "i2s_ext_clk_input";
};
};
i2s_pins_a: i2s@0 {
i2s {
sirf,pins = "i2sgrp";
sirf,function = "i2s";
};
};
i2s_no_din_pins_a: i2s_no_din@0 {
i2s_no_din {
sirf,pins = "i2s_no_dingrp";
sirf,function = "i2s_no_din";
};
};
i2s_6chn_pins_a: i2s_6chn@0 {
i2s_6chn {
sirf,pins = "i2s_6chngrp";
sirf,function = "i2s_6chn";
};
};
ac97_pins_a: ac97@0 {
ac97 {
sirf,pins = "ac97grp";
sirf,function = "ac97";
};
};
nand_pins_a: nand@0 {
nand {
sirf,pins = "nandgrp";
sirf,function = "nand";
};
};
usp0_pins_a: usp0@0 {
usp0 {
sirf,pins = "usp0grp";
sirf,function = "usp0";
};
};
usp0_uart_nostreamctrl_pins_a: usp0@1 {
usp0 {
sirf,pins =
"usp0_uart_nostreamctrl_grp";
sirf,function =
"usp0_uart_nostreamctrl";
};
};
usp0_only_utfs_pins_a: usp0@2 {
usp0 {
sirf,pins = "usp0_only_utfs_grp";
sirf,function = "usp0_only_utfs";
};
};
usp0_only_urfs_pins_a: usp0@3 {
usp0 {
sirf,pins = "usp0_only_urfs_grp";
sirf,function = "usp0_only_urfs";
};
};
usp1_pins_a: usp1@0 {
usp1 {
sirf,pins = "usp1grp";
sirf,function = "usp1";
};
};
usp1_uart_nostreamctrl_pins_a: usp1@1 {
usp1 {
sirf,pins =
"usp1_uart_nostreamctrl_grp";
sirf,function =
"usp1_uart_nostreamctrl";
};
};
usp2_pins_a: usp2@0 {
usp2 {
sirf,pins = "usp2grp";
sirf,function = "usp2";
};
};
usp2_uart_nostreamctrl_pins_a: usp2@1 {
usp2 {
sirf,pins =
"usp2_uart_nostreamctrl_grp";
sirf,function =
"usp2_uart_nostreamctrl";
};
};
usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
usb0_utmi_drvbus {
sirf,pins = "usb0_utmi_drvbusgrp";
sirf,function = "usb0_utmi_drvbus";
};
};
usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
usb1_utmi_drvbus {
sirf,pins = "usb1_utmi_drvbusgrp";
sirf,function = "usb1_utmi_drvbus";
};
};
usb1_dp_dn_pins_a: usb1_dp_dn@0 {
usb1_dp_dn {
sirf,pins = "usb1_dp_dngrp";
sirf,function = "usb1_dp_dn";
};
};
uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
uart1_route_io_usb1 {
sirf,pins = "uart1_route_io_usb1grp";
sirf,function = "uart1_route_io_usb1";
};
};
warm_rst_pins_a: warm_rst@0 {
warm_rst {
sirf,pins = "warm_rstgrp";
sirf,function = "warm_rst";
};
};
pulse_count_pins_a: pulse_count@0 {
pulse_count {
sirf,pins = "pulse_countgrp";
sirf,function = "pulse_count";
};
};
cko0_pins_a: cko0@0 {
cko0 {
sirf,pins = "cko0grp";
sirf,function = "cko0";
};
};
cko1_pins_a: cko1@0 {
cko1 {
sirf,pins = "cko1grp";
sirf,function = "cko1";
};
};
};
pwm@b0130000 {
compatible = "sirf,prima2-pwm";
reg = <0xb0130000 0x10000>;
clocks = <&clks 21>;
};
efusesys@b0140000 {
compatible = "sirf,prima2-efuse";
reg = <0xb0140000 0x10000>;
clocks = <&clks 22>;
};
pulsec@b0150000 {
compatible = "sirf,prima2-pulsec";
reg = <0xb0150000 0x10000>;
interrupts = <48>;
clocks = <&clks 23>;
};
pci-iobg {
compatible = "sirf,prima2-pciiobg", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x56000000 0x56000000 0x1b00000>;
sd0: sdhci@56000000 {
cell-index = <0>;
compatible = "sirf,prima2-sdhc";
reg = <0x56000000 0x100000>;
interrupts = <38>;
status = "disabled";
bus-width = <8>;
clocks = <&clks 36>;
};
sd1: sdhci@56100000 {
cell-index = <1>;
compatible = "sirf,prima2-sdhc";
reg = <0x56100000 0x100000>;
interrupts = <38>;
status = "disabled";
bus-width = <4>;
clocks = <&clks 36>;
};
sd2: sdhci@56200000 {
cell-index = <2>;
compatible = "sirf,prima2-sdhc";
reg = <0x56200000 0x100000>;
interrupts = <23>;
status = "disabled";
clocks = <&clks 37>;
};
sd3: sdhci@56300000 {
cell-index = <3>;
compatible = "sirf,prima2-sdhc";
reg = <0x56300000 0x100000>;
interrupts = <23>;
status = "disabled";
clocks = <&clks 37>;
};
sd4: sdhci@56400000 {
cell-index = <4>;
compatible = "sirf,prima2-sdhc";
reg = <0x56400000 0x100000>;
interrupts = <39>;
status = "disabled";
clocks = <&clks 38>;
};
sd5: sdhci@56500000 {
cell-index = <5>;
compatible = "sirf,prima2-sdhc";
reg = <0x56500000 0x100000>;
interrupts = <39>;
clocks = <&clks 38>;
};
pci-copy@57900000 {
compatible = "sirf,prima2-pcicp";
reg = <0x57900000 0x100000>;
interrupts = <40>;
};
rom-interface@57a00000 {
compatible = "sirf,prima2-romif";
reg = <0x57a00000 0x100000>;
};
};
};
rtc-iobg {
compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80030000 0x10000>;
gpsrtc@1000 {
compatible = "sirf,prima2-gpsrtc";
reg = <0x1000 0x1000>;
interrupts = <55 56 57>;
};
sysrtc@2000 {
compatible = "sirf,prima2-sysrtc";
reg = <0x2000 0x1000>;
interrupts = <52 53 54>;
};
minigpsrtc@2000 {
compatible = "sirf,prima2-minigpsrtc";
reg = <0x2000 0x1000>;
interrupts = <54>;
};
pwrc@3000 {
compatible = "sirf,prima2-pwrc";
reg = <0x3000 0x1000>;
interrupts = <32>;
};
};
uus-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xb8000000 0xb8000000 0x40000>;
usb0: usb@b00e0000 {
compatible = "chipidea,ci13611a-prima2";
reg = <0xb8000000 0x10000>;
interrupts = <10>;
clocks = <&clks 40>;
};
usb1: usb@b00f0000 {
compatible = "chipidea,ci13611a-prima2";
reg = <0xb8010000 0x10000>;
interrupts = <11>;
clocks = <&clks 41>;
};
sata@b00f0000 {
compatible = "synopsys,dwc-ahsata";
reg = <0xb8020000 0x10000>;
interrupts = <37>;
};
security@b00f0000 {
compatible = "sirf,prima2-security";
reg = <0xb8030000 0x10000>;
interrupts = <42>;
clocks = <&clks 7>;
};
};
};
};

464
arch/arm/boot/dts/ste-u300.dts
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@ -1,464 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree for the ST-Ericsson U300 Machine and SoC
*/
/dts-v1/;
/ {
model = "ST-Ericsson U300";
compatible = "stericsson,u300";
#address-cells = <1>;
#size-cells = <1>;
chosen {
bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk";
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
memory {
device_type = "memory";
reg = <0x48000000 0x03c00000>;
};
s365 {
compatible = "stericsson,s365";
vana15-supply = <&ab3100_ldo_d_reg>;
syscon = <&syscon>;
};
syscon: syscon@c0011000 {
compatible = "stericsson,u300-syscon", "syscon";
reg = <0xc0011000 0x1000>;
clk32: app_32_clk@32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
pll13: pll13@13M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <13000000>;
};
/* Slow bridge clocks under PLL13 */
slow_clk: slow_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <0>;
clocks = <&pll13>;
};
uart0_clk: uart0_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <1>;
clocks = <&slow_clk>;
};
gpio_clk: gpio_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <4>;
clocks = <&slow_clk>;
};
rtc_clk: rtc_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <6>;
clocks = <&slow_clk>;
};
apptimer_clk: app_tmr_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <7>;
clocks = <&slow_clk>;
};
acc_tmr_clk@13M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <0>; /* Slow */
clock-id = <8>;
clocks = <&slow_clk>;
};
pll208: pll208@208M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <208000000>;
};
app208: app_208_clk@208M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&pll208>;
};
cpu_clk@208M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <3>;
clocks = <&app208>;
};
app104: app_104_clk@104M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
clock-mult = <1>;
clocks = <&pll208>;
};
semi_clk@104M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <9>;
clocks = <&app104>;
};
app52: app_52_clk@52M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <4>;
clock-mult = <1>;
clocks = <&pll208>;
};
/* AHB subsystem clocks */
ahb_clk: ahb_subsys_clk@52M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <10>;
clocks = <&app52>;
};
intcon_clk@52M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <12>;
clocks = <&ahb_clk>;
};
emif_clk@52M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <5>;
clocks = <&ahb_clk>;
};
dmac_clk: dmac_clk@52M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <4>;
clocks = <&app52>;
};
fsmc_clk: fsmc_clk@52M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <6>;
clocks = <&app52>;
};
xgam_clk: xgam_clk@52M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <2>; /* Rest */
clock-id = <8>;
clocks = <&app52>;
};
app26: app_26_clk@26M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
clock-mult = <1>;
clocks = <&app52>;
};
/* Fast bridge clocks */
fast_clk: fast_clk@26M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <1>; /* Fast */
clock-id = <0>;
clocks = <&app26>;
};
i2c0_clk: i2c0_clk@26M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <1>; /* Fast */
clock-id = <1>;
clocks = <&fast_clk>;
};
i2c1_clk: i2c1_clk@26M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <1>; /* Fast */
clock-id = <2>;
clocks = <&fast_clk>;
};
mmc_pclk: mmc_p_clk@26M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <1>; /* Fast */
clock-id = <5>;
clocks = <&fast_clk>;
};
mmc_mclk: mmc_mclk {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-mclk";
clocks = <&mmc_pclk>;
};
spi_clk: spi_p_clk@26M {
#clock-cells = <0>;
compatible = "stericsson,u300-syscon-clk";
clock-type = <1>; /* Fast */
clock-id = <6>;
clocks = <&fast_clk>;
};
};
timer: timer@c0014000 {
compatible = "stericsson,u300-apptimer";
reg = <0xc0014000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <24 25 26 27>;
clocks = <&apptimer_clk>;
};
gpio: gpio@c0016000 {
compatible = "stericsson,gpio-coh901";
reg = <0xc0016000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <0 1 2 18 21 22 23>;
clocks = <&gpio_clk>;
interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
"gpio4", "gpio5", "gpio6";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
pinctrl: pinctrl@c0011000 {
compatible = "stericsson,pinctrl-u300";
reg = <0xc0011000 0x1000>;
};
watchdog: watchdog@c0012000 {
compatible = "stericsson,coh901327";
reg = <0xc0012000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <3>;
clocks = <&clk32>;
};
rtc: rtc@c0017000 {
compatible = "stericsson,coh901331";
reg = <0xc0017000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <10>;
clocks = <&rtc_clk>;
};
dmac: dma-controller@c00020000 {
compatible = "stericsson,coh901318";
reg = <0xc0020000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <2>;
#dma-cells = <1>;
dma-channels = <40>;
clocks = <&dmac_clk>;
};
/* A NAND flash of 128 MiB */
fsmc: flash@40000000 {
compatible = "stericsson,fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x9f800000 0x1000>, /* FSMC Register*/
<0x80000000 0x4000>, /* NAND Base DATA */
<0x80020000 0x4000>, /* NAND Base ADDR */
<0x80010000 0x4000>; /* NAND Base CMD */
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
nand-skip-bbtscan;
clocks = <&fsmc_clk>;
partition@0 {
label = "boot records";
reg = <0x0 0x20000>;
};
partition@20000 {
label = "free";
reg = <0x20000 0x7e0000>;
};
partition@800000 {
label = "platform";
reg = <0x800000 0xf800000>;
};
};
i2c0: i2c@c0004000 {
compatible = "st,ddci2c";
reg = <0xc0004000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <8>;
clocks = <&i2c0_clk>;
#address-cells = <1>;
#size-cells = <0>;
ab3100: ab3100@48 {
compatible = "stericsson,ab3100";
reg = <0x48>;
interrupt-parent = <&vica>;
interrupts = <0>; /* EXT0 IRQ */
ab3100-regulators {
compatible = "stericsson,ab3100-regulators";
ab3100_ldo_a_reg: ab3100_ldo_a {
startup-delay-us = <200>;
regulator-always-on;
regulator-boot-on;
};
ab3100_ldo_c_reg: ab3100_ldo_c {
startup-delay-us = <200>;
};
ab3100_ldo_d_reg: ab3100_ldo_d {
startup-delay-us = <200>;
};
ab3100_ldo_e_reg: ab3100_ldo_e {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <200>;
regulator-always-on;
regulator-boot-on;
};
ab3100_ldo_f_reg: ab3100_ldo_f {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
startup-delay-us = <600>;
regulator-always-on;
regulator-boot-on;
};
ab3100_ldo_g_reg: ab3100_ldo_g {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2850000>;
startup-delay-us = <400>;
};
ab3100_ldo_h_reg: ab3100_ldo_h {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2750000>;
startup-delay-us = <200>;
};
ab3100_ldo_k_reg: ab3100_ldo_k {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2750000>;
startup-delay-us = <200>;
};
ab3100_ext_reg: ab3100_ext {
};
ab3100_buck_reg: ab3100_buck {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <1000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
i2c1: i2c@c0005000 {
compatible = "st,ddci2c";
reg = <0xc0005000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <9>;
clocks = <&i2c1_clk>;
#address-cells = <1>;
#size-cells = <0>;
fwcam0: fwcam@10 {
reg = <0x10>;
};
fwcam1: fwcam@5d {
reg = <0x5d>;
};
};
amba {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
vica: interrupt-controller@a0001000 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xa0001000 0x20>;
};
vicb: interrupt-controller@a0002000 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xa0002000 0x20>;
};
uart0: serial@c0013000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xc0013000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <22>;
clocks = <&uart0_clk>, <&uart0_clk>;
clock-names = "apb_pclk", "uart0_clk";
dmas = <&dmac 17 &dmac 18>;
dma-names = "tx", "rx";
};
uart1: serial@c0007000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xc0007000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <20>;
dmas = <&dmac 38 &dmac 39>;
dma-names = "tx", "rx";
};
mmcsd: mmcsd@c0001000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0xc0001000 0x1000>;
interrupt-parent = <&vicb>;
interrupts = <6 7>;
clocks = <&mmc_pclk>, <&mmc_mclk>;
clock-names = "apb_pclk", "mclk";
max-frequency = <24000000>;
bus-width = <4>; // SD-card slot
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio 12 0x4>;
cd-inverted;
vmmc-supply = <&ab3100_ldo_g_reg>;
dmas = <&dmac 14>;
dma-names = "rx";
};
spi: spi@c0006000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xc0006000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <23>;
clocks = <&spi_clk>, <&spi_clk>;
clock-names = "SSPCLK", "apb_pclk";
dmas = <&dmac 27 &dmac 28>;
dma-names = "tx", "rx";
num-cs = <3>;
#address-cells = <1>;
#size-cells = <0>;
spi-dummy@1 {
compatible = "arm,pl022-dummy";
reg = <1>;
spi-max-frequency = <20000000>;
};
};
};
};

184
arch/arm/boot/dts/tango4-common.dtsi
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@ -1,184 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Based on Mans Rullgard's Tango3 DT
* https://github.com/mansr/linux-tangox
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#define CPU_CLK 0
#define SYS_CLK 1
#define USB_CLK 2
#define SDIO_CLK 3
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
periph_clk: periph_clk {
compatible = "fixed-factor-clock";
clocks = <&clkgen CPU_CLK>;
clock-mult = <1>;
clock-div = <2>;
#clock-cells = <0>;
};
mpcore {
compatible = "simple-bus";
ranges = <0x00000000 0x20000000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
scu@0 {
compatible = "arm,cortex-a9-scu";
reg = <0x0 0x100>;
};
twd@600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x600 0x10>;
interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
clocks = <&periph_clk>;
always-on;
};
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>, <0x100 0x100>;
};
};
l2cc: cache-controller@20100000 {
compatible = "arm,pl310-cache";
reg = <0x20100000 0x1000>;
cache-level = <2>;
cache-unified;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&irq0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
xtal: xtal {
compatible = "fixed-clock";
clock-frequency = <27000000>;
#clock-cells = <0>;
};
clkgen: clkgen@10000 {
compatible = "sigma,tango4-clkgen";
reg = <0x10000 0x100>;
clocks = <&xtal>;
#clock-cells = <1>;
};
tick-counter@10048 {
compatible = "sigma,tick-counter";
reg = <0x10048 0x4>;
clocks = <&xtal>;
};
uart: serial@10700 {
compatible = "ralink,rt2880-uart", "ns16550a";
reg = <0x10700 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <7372800>;
reg-shift = <2>;
};
watchdog@1fd00 {
compatible = "sigma,smp8759-wdt";
reg = <0x1fd00 8>;
clocks = <&xtal>;
};
mmc0: mmc@21000 {
compatible = "arasan,sdhci-8.9a";
reg = <0x21000 0x200>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkgen SDIO_CLK>, <&clkgen SYS_CLK>;
interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
};
mmc1: mmc@21200 {
compatible = "arasan,sdhci-8.9a";
reg = <0x21200 0x200>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkgen SDIO_CLK>, <&clkgen SYS_CLK>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
};
usb0: usb@21400 {
compatible = "chipidea,usb2";
reg = <0x21400 0x200>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb0_phy>;
phy-names = "usb-phy";
};
usb0_phy: phy@21700 {
compatible = "sigma,smp8642-usb-phy";
reg = <0x21700 0x100>;
#phy-cells = <0>;
clocks = <&clkgen USB_CLK>;
};
usb1: usb@25400 {
compatible = "chipidea,usb2";
reg = <0x25400 0x200>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb1_phy>;
phy-names = "usb-phy";
};
usb1_phy: phy@25700 {
compatible = "sigma,smp8642-usb-phy";
reg = <0x25700 0x100>;
#phy-cells = <0>;
clocks = <&clkgen USB_CLK>;
};
eth0: ethernet@26000 {
compatible = "sigma,smp8734-ethernet";
reg = <0x26000 0x800>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkgen SYS_CLK>;
};
intc: interrupt-controller@6e000 {
compatible = "sigma,smp8642-intc";
reg = <0x6e000 0x400>;
ranges = <0 0x6e000 0x400>;
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
irq0: irq0@0 {
reg = <0x000 0x100>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
};
irq1: irq1@100 {
reg = <0x100 0x100>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
irq2: irq2@300 {
reg = <0x300 0x100>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};

57
arch/arm/boot/dts/tango4-smp8758.dtsi
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@ -1,57 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include "tango4-common.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "sigma,tango4-smp";
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
next-level-cache = <&l2cc>;
device_type = "cpu";
reg = <0>;
clocks = <&clkgen CPU_CLK>;
clock-latency = <1>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a9";
next-level-cache = <&l2cc>;
device_type = "cpu";
reg = <1>;
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-affinity = <&cpu0>, <&cpu1>;
interrupts =
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
cpu_temp: thermal@920100 {
#thermal-sensor-cells = <0>;
compatible = "sigma,smp8758-thermal";
reg = <0x920100 12>;
};
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay = <997>; /* milliseconds */
polling-delay-passive = <499>; /* milliseconds */
thermal-sensors = <&cpu_temp>;
trips {
cpu_critical {
temperature = <120000>;
hysteresis = <2500>;
type = "critical";
};
};
};
};
};

42
arch/arm/boot/dts/tango4-vantage-1172.dts
View File

@ -1,42 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tango4-smp8758.dtsi"
/ {
model = "Sigma Designs SMP8758 Vantage-1172 Rev E1";
compatible = "sigma,vantage-1172", "sigma,smp8758", "sigma,tango4";
aliases {
serial = &uart;
eth0 = &eth0;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>; /* 2 GB */
};
chosen {
stdout-path = "serial:115200n8";
};
};
&eth0 {
phy-connection-type = "rgmii-id";
phy-handle = <&eth0_phy>;
#address-cells = <1>;
#size-cells = <0>;
/* Atheros AR8035 */
eth0_phy: ethernet-phy@4 {
compatible = "ethernet-phy-id004d.d072",
"ethernet-phy-ieee802.3-c22";
interrupts = <37 IRQ_TYPE_EDGE_RISING>;
reg = <4>;
};
};
&mmc1 {
non-removable; /* eMMC */
};

48
arch/arm/boot/dts/zx296702-ad1.dts
View File

@ -1,48 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "zx296702.dtsi"
/ {
model = "ZTE ZX296702 AD1 Board";
compatible = "zte,zx296702-ad1", "zte,zx296702";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
memory {
device_type = "memory";
reg = <0x50000000 0x20000000>;
};
};
&mmc0 {
supports-highspeed;
non-removable;
disable-wp;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
&mmc1 {
supports-highspeed;
non-removable;
disable-wp;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <8>;
};
};
&uart0 {
status = "okay";
};

142
arch/arm/boot/dts/zx296702.dtsi
View File

@ -1,142 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/zx296702-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "zte,zx296702-smp";
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2cc>;
reg = <0>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2cc>;
reg = <1>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
matrix: bus-matrix@400000 {
compatible = "zte,zx-bus-matrix";
reg = <0x00400000 0x1000>;
};
intc: interrupt-controller@801000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
reg = <0x00801000 0x1000>,
<0x00800100 0x100>;
};
global_timer: timer@8000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x00800200 0x20>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
clocks = <&topclk ZX296702_A9_PERIPHCLK>;
};
l2cc: cache-controller@c00000 {
compatible = "arm,pl310-cache";
reg = <0x00c00000 0x1000>;
cache-unified;
cache-level = <2>;
arm,data-latency = <1 1 1>;
arm,tag-latency = <1 1 1>;
arm,double-linefill = <1>;
arm,double-linefill-incr = <0>;
};
pcu: pcu@a0008000 {
compatible = "zte,zx296702-pcu";
reg = <0xa0008000 0x1000>;
};
topclk: topclk@9800000 {
compatible = "zte,zx296702-topcrm-clk";
reg = <0x09800000 0x1000>;
#clock-cells = <1>;
};
lsp1clk: lsp1clk@9400000 {
compatible = "zte,zx296702-lsp1crpm-clk";
reg = <0x09400000 0x1000>;
#clock-cells = <1>;
};
lsp0clk: lsp0clk@b000000 {
compatible = "zte,zx296702-lsp0crpm-clk";
reg = <0x0b000000 0x1000>;
#clock-cells = <1>;
};
uart0: serial@9405000 {
compatible = "zte,zx296702-uart";
reg = <0x09405000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lsp1clk ZX296702_UART0_WCLK>;
status = "disabled";
};
uart1: serial@9406000 {
compatible = "zte,zx296702-uart";
reg = <0x09406000 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lsp1clk ZX296702_UART1_WCLK>;
status = "disabled";
};
mmc0: mmc@9408000 {
compatible = "snps,dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x09408000 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <32>;
clocks = <&lsp1clk ZX296702_SDMMC0_PCLK>,
<&lsp1clk ZX296702_SDMMC0_WCLK>;
clock-names = "biu", "ciu";
status = "disabled";
};
mmc1: mmc@b003000 {
compatible = "snps,dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0b003000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <32>;
clocks = <&lsp0clk ZX296702_SDMMC1_PCLK>,
<&lsp0clk ZX296702_SDMMC1_WCLK>;
clock-names = "biu", "ciu";
status = "disabled";
};
sysctrl: sysctrl@a0007000 {
compatible = "zte,sysctrl", "syscon";
reg = <0xa0007000 0x1000>;
};
};
};

98
arch/arm/configs/efm32_defconfig
View File

@ -1,98 +0,0 @@
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=12
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_UID16 is not set
# CONFIG_BASE_FULL is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_MMU is not set
CONFIG_ARM_SINGLE_ARMV7M=y
CONFIG_ARCH_EFM32=y
CONFIG_SET_MEM_PARAM=y
CONFIG_DRAM_BASE=0x88000000
CONFIG_DRAM_SIZE=0x00400000
CONFIG_FLASH_MEM_BASE=0x8c000000
CONFIG_FLASH_SIZE=0x01000000
CONFIG_PREEMPT=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_XIP_KERNEL=y
CONFIG_XIP_PHYS_ADDR=0x8c000000
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_SHARED_FLAT=y
# CONFIG_COREDUMP is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK_RO=y
CONFIG_MTD_ROM=y
CONFIG_MTD_UCLINUX=y
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
CONFIG_KS8851=y
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_UNIX98_PTYS is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_EFM32_UART=y
CONFIG_SERIAL_EFM32_UART_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_EFM32=y
CONFIG_SPI=y
CONFIG_SPI_EFM32=y
CONFIG_GPIO_SYSFS=y
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_SPI=y
CONFIG_EXT2_FS=y
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_MTD=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_FTRACE is not set

72
arch/arm/configs/prima2_defconfig
View File

@ -1,72 +0,0 @@
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_ARCH_SIRF=y
CONFIG_SMP=y
CONFIG_SCHED_MC=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_KEXEC=y
CONFIG_BINFMT_MISC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_INPUT_MISC=y
CONFIG_SERIAL_SIRFSOC=y
CONFIG_SERIAL_SIRFSOC_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_SIRF=y
CONFIG_SPI=y
CONFIG_SPI_SIRF=y
CONFIG_SPI_SPIDEV=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_USB_GADGET=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_SIRF=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_SIRFSOC=y
CONFIG_DMADEVICES=y
CONFIG_DMADEVICES_DEBUG=y
CONFIG_DMADEVICES_VDEBUG=y
CONFIG_SIRF_DMA=y
CONFIG_HWSPINLOCK_SIRF=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_CRC_CCITT=y

93
arch/arm/configs/tango4_defconfig
View File

@ -1,93 +0,0 @@
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_ARCH_TANGO=y
# CONFIG_ARM_ERRATA_643719 is not set
CONFIG_SMP=y
CONFIG_PREEMPT=y
CONFIG_HZ_300=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
# CONFIG_ATAGS is not set
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPUFREQ_DT=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_TANGO=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_NET_VENDOR_AURORA=y
CONFIG_AURORA_NB8800=y
CONFIG_AT803X_PHY=y
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_RT288X=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_XLR=y
CONFIG_GPIOLIB=y
CONFIG_THERMAL=y
CONFIG_CPU_THERMAL=y
CONFIG_TANGO_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_TANGOX_WATCHDOG=y
CONFIG_FB=y
# CONFIG_HID is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_DMADEVICES=y
CONFIG_EXT4_FS=y
CONFIG_FUSE_FS=m
CONFIG_VFAT_FS=m
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
# CONFIG_NFS_V2 is not set
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_UTF8=m
CONFIG_PRINTK_TIME=y
# CONFIG_CRYPTO_ECHAINIV is not set

65
arch/arm/configs/u300_defconfig
View File

@ -1,65 +0,0 @@
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
# CONFIG_AIO is not set
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_U300=y
CONFIG_MACH_U300_SPIDUMMY=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=/dev/ram0 rw rootfstype=rootfs console=ttyAMA0,115200n8 lpj=515072"
CONFIG_CPU_IDLE=y
# CONFIG_SUSPEND is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSMC=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_FB=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
CONFIG_RTC_DRV_COH901331=y
CONFIG_DMADEVICES=y
CONFIG_COH901318=y
# CONFIG_DNOTIFY is not set
CONFIG_FUSE_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_PREEMPT is not set

122
arch/arm/configs/zx_defconfig
View File

@ -1,122 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_CGROUP_DEBUG=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_ZX=y
CONFIG_SOC_ZX296702=y
# CONFIG_SWP_EMULATE is not set
CONFIG_ARM_ERRATA_754322=y
CONFIG_ARM_ERRATA_775420=y
CONFIG_SMP=y
CONFIG_VMSPLIT_2G=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_KSM=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_HIBERNATION=y
CONFIG_PM_RUNTIME=y
CONFIG_PM_DEBUG=y
CONFIG_SUSPEND_TIME=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyAMA0,115200 debug earlyprintk root=/dev/ram rw rootwait"
#CONFIG_NET is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=192
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_UID_STAT=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_CHR_DEV_SCH=y
CONFIG_SCSI_MULTI_LUN=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_NETDEVICES=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO=y
CONFIG_SERIO_LIBPS2=y
CONFIG_SPI=y
CONFIG_LOGO=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_CONSOLE_POLL=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_BLOCK_MINORS=16
CONFIG_MMC_DW=y
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_DEBUG=y
CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=936
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
#CONFIG_NFS_FS is not set
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_INFO=y
CONFIG_FRAME_WARN=4096
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_PANIC_TIMEOUT=5
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_RCU_CPU_STALL_TIMEOUT=60
# CONFIG_FTRACE is not set
CONFIG_KGDB=y
CONFIG_KGDB_KDB=y
# CONFIG_ARM_UNWIND is not set
CONFIG_DEBUG_PREEMPT=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_STACKTRACE=y
CONFIG_DEBUG_ZTE_ZX=y
CONFIG_EARLY_PRINTK=y
CONFIG_CRYPTO_LZO=y
CONFIG_GPIOLIB=y

45
arch/arm/include/debug/efm32.S
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@ -1,45 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2013 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*/
#define UARTn_CMD 0x000c
#define UARTn_CMD_TXEN 0x0004
#define UARTn_STATUS 0x0010
#define UARTn_STATUS_TXC 0x0020
#define UARTn_STATUS_TXBL 0x0040
#define UARTn_TXDATA 0x0034
.macro addruart, rx, tmp, tmp2
ldr \rx, =(CONFIG_DEBUG_UART_PHYS)
/*
* enable TX. The driver might disable it to save energy. We
* don't care about disabling at the end as during debug power
* consumption isn't that important.
*/
ldr \tmp, =(UARTn_CMD_TXEN)
str \tmp, [\rx, #UARTn_CMD]
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #UARTn_TXDATA]
.endm
.macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #UARTn_STATUS]
tst \rd, #UARTn_STATUS_TXBL
beq 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, UARTn_STATUS]
tst \rd, #UARTn_STATUS_TXC
bne 1001b
.endm

40
arch/arm/include/debug/sirf.S
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@ -1,40 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* arch/arm/mach-prima2/include/mach/debug-macro.S
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#define SIRF_LLUART_TXFIFO_STATUS 0x0114
#define SIRF_LLUART_TXFIFO_DATA 0x0118
#define SIRF_LLUART_TXFIFO_FULL (1 << 5)
#ifdef CONFIG_DEBUG_SIRFATLAS7_UART0
#define SIRF_LLUART_TXFIFO_EMPTY (1 << 8)
#else
#define SIRF_LLUART_TXFIFO_EMPTY (1 << 6)
#endif
.macro addruart, rp, rv, tmp
ldr \rp, =CONFIG_DEBUG_UART_PHYS @ physical
ldr \rv, =CONFIG_DEBUG_UART_VIRT @ virtual
.endm
.macro senduart,rd,rx
str \rd, [\rx, #SIRF_LLUART_TXFIFO_DATA]
.endm
.macro busyuart,rd,rx
.endm
.macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS]
tst \rd, #SIRF_LLUART_TXFIFO_EMPTY
beq 1001b
.endm

2
arch/arm/mach-efm32/Makefile
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@ -1,2 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += dtmachine.o

4
arch/arm/mach-efm32/Makefile.boot
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@ -1,4 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
# Empty file waiting for deletion once Makefile.boot isn't needed any more.
# Patch waits for application at
# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 .

16
arch/arm/mach-efm32/dtmachine.c
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@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/kernel.h>
#include <asm/v7m.h>
#include <asm/mach/arch.h>
static const char *const efm32gg_compat[] __initconst = {
"efm32,dk3750",
NULL
};
DT_MACHINE_START(EFM32DT, "EFM32 (Device Tree Support)")
.dt_compat = efm32gg_compat,
.restart = armv7m_restart,
MACHINE_END

9
arch/arm/mach-picoxcell/Kconfig
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@ -1,9 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
config ARCH_PICOXCELL
bool "Picochip PicoXcell"
depends on ARCH_MULTI_V6
select ARM_VIC
select DW_APB_TIMER_OF
select GPIOLIB
select HAVE_TCM
select NO_IOPORT_MAP

2
arch/arm/mach-picoxcell/Makefile
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@ -1,2 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y := common.o

81
arch/arm/mach-picoxcell/common.c
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@ -1,81 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2011 Picochip Ltd., Jamie Iles
*
* All enquiries to support@picochip.com
*/
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/reboot.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#define PHYS_TO_IO(x) (((x) & 0x00ffffff) | 0xfe000000)
#define PICOXCELL_PERIPH_BASE 0x80000000
#define PICOXCELL_PERIPH_LENGTH SZ_4M
#define WDT_CTRL_REG_EN_MASK (1 << 0)
#define WDT_CTRL_REG_OFFS (0x00)
#define WDT_TIMEOUT_REG_OFFS (0x04)
static void __iomem *wdt_regs;
/*
* The machine restart method can be called from an atomic context so we won't
* be able to ioremap the regs then.
*/
static void picoxcell_setup_restart(void)
{
struct device_node *np = of_find_compatible_node(NULL, NULL,
"snps,dw-apb-wdg");
if (WARN(!np, "unable to setup watchdog restart"))
return;
wdt_regs = of_iomap(np, 0);
WARN(!wdt_regs, "failed to remap watchdog regs");
}
static struct map_desc io_map __initdata = {
.virtual = PHYS_TO_IO(PICOXCELL_PERIPH_BASE),
.pfn = __phys_to_pfn(PICOXCELL_PERIPH_BASE),
.length = PICOXCELL_PERIPH_LENGTH,
.type = MT_DEVICE,
};
static void __init picoxcell_map_io(void)
{
iotable_init(&io_map, 1);
}
static void __init picoxcell_init_machine(void)
{
picoxcell_setup_restart();
}
static const char *picoxcell_dt_match[] = {
"picochip,pc3x2",
"picochip,pc3x3",
NULL
};
static void picoxcell_wdt_restart(enum reboot_mode mode, const char *cmd)
{
/*
* Configure the watchdog to reset with the shortest possible timeout
* and give it chance to do the reset.
*/
if (wdt_regs) {
writel_relaxed(WDT_CTRL_REG_EN_MASK, wdt_regs + WDT_CTRL_REG_OFFS);
writel_relaxed(0, wdt_regs + WDT_TIMEOUT_REG_OFFS);
/* No sleeping, possibly atomic. */
mdelay(500);
}
}
DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
.map_io = picoxcell_map_io,
.init_machine = picoxcell_init_machine,
.dt_compat = picoxcell_dt_match,
.restart = picoxcell_wdt_restart,
MACHINE_END

48
arch/arm/mach-prima2/Kconfig
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@ -1,48 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_SIRF
bool "CSR SiRF"
depends on ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
select RESET_CONTROLLER
select GENERIC_IRQ_CHIP
select GPIOLIB
select NO_IOPORT_MAP
select REGMAP
select PINCTRL
select PINCTRL_SIRF
help
Support for CSR SiRFprimaII/Marco/Polo platforms
if ARCH_SIRF
comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features"
config ARCH_ATLAS6
bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
default y
select SIRF_IRQ
help
Support for CSR SiRFSoC ARM Cortex A9 Platform
config ARCH_ATLAS7
bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
default y
select ARM_GIC
select ATLAS7_TIMER
select HAVE_ARM_SCU if SMP
help
Support for CSR SiRFSoC ARM Cortex A7 Platform
config ARCH_PRIMA2
bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
default y
select SIRF_IRQ
select ZONE_DMA
select PRIMA2_TIMER
help
Support for CSR SiRFSoC ARM Cortex A9 Platform
config SIRF_IRQ
bool
endif

9
arch/arm/mach-prima2/Makefile
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@ -1,9 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += rstc.o
obj-y += common.o
obj-y += rtciobrg.o
obj-$(CONFIG_SUSPEND) += pm.o sleep.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
CFLAGS_hotplug.o += -march=armv7-a

64
arch/arm/mach-prima2/common.c
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@ -1,64 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Defines machines for CSR SiRFprimaII
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sizes.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include "common.h"
static void __init __maybe_unused sirfsoc_init_late(void)
{
sirfsoc_pm_init();
}
#ifdef CONFIG_ARCH_ATLAS6
static const char *const atlas6_dt_match[] __initconst = {
"sirf,atlas6",
NULL
};
DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.init_late = sirfsoc_init_late,
.dt_compat = atlas6_dt_match,
MACHINE_END
#endif
#ifdef CONFIG_ARCH_PRIMA2
static const char *const prima2_dt_match[] __initconst = {
"sirf,prima2",
NULL
};
DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.dma_zone_size = SZ_256M,
.init_late = sirfsoc_init_late,
.dt_compat = prima2_dt_match,
MACHINE_END
#endif
#ifdef CONFIG_ARCH_ATLAS7
static const char *const atlas7_dt_match[] __initconst = {
"sirf,atlas7",
NULL
};
DT_MACHINE_START(ATLAS7_DT, "Generic ATLAS7 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.smp = smp_ops(sirfsoc_smp_ops),
.dt_compat = atlas7_dt_match,
MACHINE_END
#endif

32
arch/arm/mach-prima2/common.h
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@ -1,32 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* This file contains common function prototypes to avoid externs in the c files.
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#ifndef __MACH_PRIMA2_COMMON_H__
#define __MACH_PRIMA2_COMMON_H__
#include <linux/init.h>
#include <linux/reboot.h>
#include <asm/mach/time.h>
#include <asm/exception.h>
extern volatile int prima2_pen_release;
extern const struct smp_operations sirfsoc_smp_ops;
extern void sirfsoc_secondary_startup(void);
extern void sirfsoc_cpu_die(unsigned int cpu);
extern void __init sirfsoc_of_irq_init(void);
extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
#ifdef CONFIG_SUSPEND
extern int sirfsoc_pm_init(void);
#else
static inline int sirfsoc_pm_init(void) { return 0; }
#endif
#endif

36
arch/arm/mach-prima2/headsmp.S
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@ -1,36 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Entry of the second core for CSR Marco dual-core SMP SoCs
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/linkage.h>
#include <linux/init.h>
/*
* SIRFSOC specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
* ready for them to initialise.
*/
ENTRY(sirfsoc_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
adr r4, 1f
ldmia r4, {r5, r6}
sub r4, r4, r5
add r6, r6, r4
pen: ldr r7, [r6]
cmp r7, r0
bne pen
/*
* we've been released from the holding pen: secondary_stack
* should now contain the SVC stack for this core
*/
b secondary_startup
ENDPROC(sirfsoc_secondary_startup)
.align
1: .long .
.long prima2_pen_release

38
arch/arm/mach-prima2/hotplug.c
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@ -1,38 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* CPU hotplug support for CSR Marco dual-core SMP SoCs
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>
#include <asm/smp_plat.h>
#include "common.h"
static inline void platform_do_lowpower(unsigned int cpu)
{
/* we put the platform to just WFI */
for (;;) {
__asm__ __volatile__("dsb\n\t" "wfi\n\t"
: : : "memory");
if (prima2_pen_release == cpu_logical_map(cpu)) {
/*
* OK, proper wakeup, we're done
*/
break;
}
}
}
/*
* platform-specific code to shutdown a CPU
*
* Called with IRQs disabled
*/
void sirfsoc_cpu_die(unsigned int cpu)
{
platform_do_lowpower(cpu);
}

123
arch/arm/mach-prima2/platsmp.c
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@ -1,123 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* plat smp support for CSR Marco dual-core SMP SoCs
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include "common.h"
static void __iomem *clk_base;
static DEFINE_SPINLOCK(boot_lock);
/* XXX prima2_pen_release is cargo culted code - DO NOT COPY XXX */
volatile int prima2_pen_release = -1;
static void sirfsoc_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
prima2_pen_release = -1;
smp_wmb();
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
static const struct of_device_id clk_ids[] = {
{ .compatible = "sirf,atlas7-clkc" },
{},
};
static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
struct device_node *np;
np = of_find_matching_node(NULL, clk_ids);
if (!np)
return -ENODEV;
clk_base = of_iomap(np, 0);
if (!clk_base)
return -ENOMEM;
/*
* write the address of secondary startup into the clkc register
* at offset 0x2bC, then write the magic number 0x3CAF5D62 to the
* clkc register at offset 0x2b8, which is what boot rom code is
* waiting for. This would wake up the secondary core from WFE
*/
#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2bc
__raw_writel(__pa_symbol(sirfsoc_secondary_startup),
clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x2b8
__raw_writel(0x3CAF5D62,
clk_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
/* make sure write buffer is drained */
mb();
spin_lock(&boot_lock);
/*
* The secondary processor is waiting to be released from
* the holding pen - release it, then wait for it to flag
* that it has been released by resetting prima2_pen_release.
*
* Note that "prima2_pen_release" is the hardware CPU ID, whereas
* "cpu" is Linux's internal ID.
*/
prima2_pen_release = cpu_logical_map(cpu);
sync_cache_w(&prima2_pen_release);
/*
* Send the secondary CPU SEV, thereby causing the boot monitor to read
* the JUMPADDR and WAKEMAGIC, and branch to the address found there.
*/
dsb_sev();
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
if (prima2_pen_release == -1)
break;
udelay(10);
}
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
spin_unlock(&boot_lock);
return prima2_pen_release != -1 ? -ENOSYS : 0;
}
const struct smp_operations sirfsoc_smp_ops __initconst = {
.smp_secondary_init = sirfsoc_secondary_init,
.smp_boot_secondary = sirfsoc_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = sirfsoc_cpu_die,
#endif
};

153
arch/arm/mach-prima2/pm.c
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@ -1,153 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* power management entry for CSR SiRFprimaII
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/kernel.h>
#include <linux/suspend.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/rtc/sirfsoc_rtciobrg.h>
#include <asm/outercache.h>
#include <asm/suspend.h>
#include <asm/hardware/cache-l2x0.h>
#include "pm.h"
/*
* suspend asm codes will access these to make DRAM become self-refresh and
* system sleep
*/
u32 sirfsoc_pwrc_base;
void __iomem *sirfsoc_memc_base;
static void sirfsoc_set_wakeup_source(void)
{
u32 pwr_trigger_en_reg;
pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
SIRFSOC_PWRC_TRIGGER_EN);
#define X_ON_KEY_B (1 << 0)
#define RTC_ALARM0_B (1 << 2)
#define RTC_ALARM1_B (1 << 3)
sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B |
RTC_ALARM0_B | RTC_ALARM1_B,
sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN);
}
static void sirfsoc_set_sleep_mode(u32 mode)
{
u32 sleep_mode = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
SIRFSOC_PWRC_PDN_CTRL);
sleep_mode &= ~(SIRFSOC_SLEEP_MODE_MASK << 1);
sleep_mode |= mode << 1;
sirfsoc_rtc_iobrg_writel(sleep_mode, sirfsoc_pwrc_base +
SIRFSOC_PWRC_PDN_CTRL);
}
static int sirfsoc_pre_suspend_power_off(void)
{
u32 wakeup_entry = __pa_symbol(cpu_resume);
sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base +
SIRFSOC_PWRC_SCRATCH_PAD1);
sirfsoc_set_wakeup_source();
sirfsoc_set_sleep_mode(SIRFSOC_DEEP_SLEEP_MODE);
return 0;
}
static int sirfsoc_pm_enter(suspend_state_t state)
{
switch (state) {
case PM_SUSPEND_MEM:
sirfsoc_pre_suspend_power_off();
outer_disable();
/* go zzz */
cpu_suspend(0, sirfsoc_finish_suspend);
outer_resume();
break;
default:
return -EINVAL;
}
return 0;
}
static const struct platform_suspend_ops sirfsoc_pm_ops = {
.enter = sirfsoc_pm_enter,
.valid = suspend_valid_only_mem,
};
static const struct of_device_id pwrc_ids[] = {
{ .compatible = "sirf,prima2-pwrc" },
{}
};
static int __init sirfsoc_of_pwrc_init(void)
{
struct device_node *np;
np = of_find_matching_node(NULL, pwrc_ids);
if (!np) {
pr_err("unable to find compatible sirf pwrc node in dtb\n");
return -ENOENT;
}
/*
* pwrc behind rtciobrg is not located in memory space
* though the property is named reg. reg only means base
* offset for pwrc. then of_iomap is not suitable here.
*/
if (of_property_read_u32(np, "reg", &sirfsoc_pwrc_base))
panic("unable to find base address of pwrc node in dtb\n");
of_node_put(np);
return 0;
}
static const struct of_device_id memc_ids[] = {
{ .compatible = "sirf,prima2-memc" },
{}
};
static int sirfsoc_memc_probe(struct platform_device *op)
{
struct device_node *np = op->dev.of_node;
sirfsoc_memc_base = of_iomap(np, 0);
if (!sirfsoc_memc_base)
panic("unable to map memc registers\n");
return 0;
}
static struct platform_driver sirfsoc_memc_driver = {
.probe = sirfsoc_memc_probe,
.driver = {
.name = "sirfsoc-memc",
.of_match_table = memc_ids,
},
};
static int __init sirfsoc_memc_init(void)
{
return platform_driver_register(&sirfsoc_memc_driver);
}
int __init sirfsoc_pm_init(void)
{
sirfsoc_of_pwrc_init();
sirfsoc_memc_init();
suspend_set_ops(&sirfsoc_pm_ops);
return 0;
}

28
arch/arm/mach-prima2/pm.h
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@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* arch/arm/mach-prima2/pm.h
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#ifndef _MACH_PRIMA2_PM_H_
#define _MACH_PRIMA2_PM_H_
#define SIRFSOC_PWR_SLEEPFORCE 0x01
#define SIRFSOC_SLEEP_MODE_MASK 0x3
#define SIRFSOC_DEEP_SLEEP_MODE 0x1
#define SIRFSOC_PWRC_PDN_CTRL 0x0
#define SIRFSOC_PWRC_PON_OFF 0x4
#define SIRFSOC_PWRC_TRIGGER_EN 0x8
#define SIRFSOC_PWRC_PIN_STATUS 0x14
#define SIRFSOC_PWRC_SCRATCH_PAD1 0x18
#define SIRFSOC_PWRC_SCRATCH_PAD2 0x1C
#ifndef __ASSEMBLY__
extern int sirfsoc_finish_suspend(unsigned long);
#endif
#endif

107
arch/arm/mach-prima2/rstc.c
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@ -1,107 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* reset controller for CSR SiRFprimaII
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/reset-controller.h>
#include <asm/system_misc.h>
#define SIRFSOC_RSTBIT_NUM 64
static void __iomem *sirfsoc_rstc_base;
static DEFINE_MUTEX(rstc_lock);
static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
unsigned long sw_reset_idx)
{
u32 reset_bit = sw_reset_idx;
if (reset_bit >= SIRFSOC_RSTBIT_NUM)
return -EINVAL;
mutex_lock(&rstc_lock);
/*
* Writing 1 to this bit resets corresponding block.
* Writing 0 to this bit de-asserts reset signal of the
* corresponding block. datasheet doesn't require explicit
* delay between the set and clear of reset bit. it could
* be shorter if tests pass.
*/
writel(readl(sirfsoc_rstc_base +
(reset_bit / 32) * 4) | (1 << reset_bit),
sirfsoc_rstc_base + (reset_bit / 32) * 4);
msleep(20);
writel(readl(sirfsoc_rstc_base +
(reset_bit / 32) * 4) & ~(1 << reset_bit),
sirfsoc_rstc_base + (reset_bit / 32) * 4);
mutex_unlock(&rstc_lock);
return 0;
}
static struct reset_control_ops sirfsoc_rstc_ops = {
.reset = sirfsoc_reset_module,
};
static struct reset_controller_dev sirfsoc_reset_controller = {
.ops = &sirfsoc_rstc_ops,
.nr_resets = SIRFSOC_RSTBIT_NUM,
};
#define SIRFSOC_SYS_RST_BIT BIT(31)
static void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
{
writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
}
static int sirfsoc_rstc_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
sirfsoc_rstc_base = of_iomap(np, 0);
if (!sirfsoc_rstc_base) {
dev_err(&pdev->dev, "unable to map rstc cpu registers\n");
return -ENOMEM;
}
sirfsoc_reset_controller.of_node = np;
arm_pm_restart = sirfsoc_restart;
if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
reset_controller_register(&sirfsoc_reset_controller);
return 0;
}
static const struct of_device_id rstc_ids[] = {
{ .compatible = "sirf,prima2-rstc" },
{},
};
static struct platform_driver sirfsoc_rstc_driver = {
.probe = sirfsoc_rstc_probe,
.driver = {
.name = "sirfsoc_rstc",
.of_match_table = rstc_ids,
},
};
static int __init sirfsoc_rstc_init(void)
{
return platform_driver_register(&sirfsoc_rstc_driver);
}
subsys_initcall(sirfsoc_rstc_init);

179
arch/arm/mach-prima2/rtciobrg.c
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@ -1,179 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* RTC I/O Bridge interfaces for CSR SiRFprimaII/atlas7
* ARM access the registers of SYSRTC, GPSRTC and PWRC through this module
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#define SIRFSOC_CPUIOBRG_CTRL 0x00
#define SIRFSOC_CPUIOBRG_WRBE 0x04
#define SIRFSOC_CPUIOBRG_ADDR 0x08
#define SIRFSOC_CPUIOBRG_DATA 0x0c
/*
* suspend asm codes will access this address to make system deepsleep
* after DRAM becomes self-refresh
*/
void __iomem *sirfsoc_rtciobrg_base;
static DEFINE_SPINLOCK(rtciobrg_lock);
/*
* symbols without lock are only used by suspend asm codes
* and these symbols are not exported too
*/
void sirfsoc_rtc_iobrg_wait_sync(void)
{
while (readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL))
cpu_relax();
}
void sirfsoc_rtc_iobrg_besyncing(void)
{
unsigned long flags;
spin_lock_irqsave(&rtciobrg_lock, flags);
sirfsoc_rtc_iobrg_wait_sync();
spin_unlock_irqrestore(&rtciobrg_lock, flags);
}
EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_besyncing);
u32 __sirfsoc_rtc_iobrg_readl(u32 addr)
{
sirfsoc_rtc_iobrg_wait_sync();
writel_relaxed(0x00, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE);
writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR);
writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL);
sirfsoc_rtc_iobrg_wait_sync();
return readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA);
}
u32 sirfsoc_rtc_iobrg_readl(u32 addr)
{
unsigned long flags, val;
/* TODO: add hwspinlock to sync with M3 */
spin_lock_irqsave(&rtciobrg_lock, flags);
val = __sirfsoc_rtc_iobrg_readl(addr);
spin_unlock_irqrestore(&rtciobrg_lock, flags);
return val;
}
EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_readl);
void sirfsoc_rtc_iobrg_pre_writel(u32 val, u32 addr)
{
sirfsoc_rtc_iobrg_wait_sync();
writel_relaxed(0xf1, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE);
writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR);
writel_relaxed(val, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA);
}
void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr)
{
unsigned long flags;
/* TODO: add hwspinlock to sync with M3 */
spin_lock_irqsave(&rtciobrg_lock, flags);
sirfsoc_rtc_iobrg_pre_writel(val, addr);
writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL);
sirfsoc_rtc_iobrg_wait_sync();
spin_unlock_irqrestore(&rtciobrg_lock, flags);
}
EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);
static int regmap_iobg_regwrite(void *context, unsigned int reg,
unsigned int val)
{
sirfsoc_rtc_iobrg_writel(val, reg);
return 0;
}
static int regmap_iobg_regread(void *context, unsigned int reg,
unsigned int *val)
{
*val = (u32)sirfsoc_rtc_iobrg_readl(reg);
return 0;
}
static struct regmap_bus regmap_iobg = {
.reg_write = regmap_iobg_regwrite,
.reg_read = regmap_iobg_regread,
};
/**
* devm_regmap_init_iobg(): Initialise managed register map
*
* @iobg: Device that will be interacted with
* @config: Configuration for register map
*
* The return value will be an ERR_PTR() on error or a valid pointer
* to a struct regmap. The regmap will be automatically freed by the
* device management code.
*/
struct regmap *devm_regmap_init_iobg(struct device *dev,
const struct regmap_config *config)
{
const struct regmap_bus *bus = &regmap_iobg;
return devm_regmap_init(dev, bus, dev, config);
}
EXPORT_SYMBOL_GPL(devm_regmap_init_iobg);
static const struct of_device_id rtciobrg_ids[] = {
{ .compatible = "sirf,prima2-rtciobg" },
{}
};
static int sirfsoc_rtciobrg_probe(struct platform_device *op)
{
struct device_node *np = op->dev.of_node;
sirfsoc_rtciobrg_base = of_iomap(np, 0);
if (!sirfsoc_rtciobrg_base)
panic("unable to map rtc iobrg registers\n");
return 0;
}
static struct platform_driver sirfsoc_rtciobrg_driver = {
.probe = sirfsoc_rtciobrg_probe,
.driver = {
.name = "sirfsoc-rtciobrg",
.of_match_table = rtciobrg_ids,
},
};
static int __init sirfsoc_rtciobrg_init(void)
{
return platform_driver_register(&sirfsoc_rtciobrg_driver);
}
postcore_initcall(sirfsoc_rtciobrg_init);
MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>");
MODULE_AUTHOR("Barry Song <baohua.song@csr.com>");
MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge");
MODULE_LICENSE("GPL v2");

63
arch/arm/mach-prima2/sleep.S
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@ -1,63 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* sleep mode for CSR SiRFprimaII
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/linkage.h>
#include <asm/ptrace.h>
#include <asm/assembler.h>
#include "pm.h"
#define DENALI_CTL_22_OFF 0x58
#define DENALI_CTL_112_OFF 0x1c0
.text
ENTRY(sirfsoc_finish_suspend)
@ r5: mem controller
ldr r0, =sirfsoc_memc_base
ldr r5, [r0]
@ r6: pwrc base offset
ldr r0, =sirfsoc_pwrc_base
ldr r6, [r0]
@ r7: rtc iobrg controller
ldr r0, =sirfsoc_rtciobrg_base
ldr r7, [r0]
@ Read the power control register and set the
@ sleep force bit.
add r0, r6, #SIRFSOC_PWRC_PDN_CTRL
bl __sirfsoc_rtc_iobrg_readl
orr r0,r0,#SIRFSOC_PWR_SLEEPFORCE
add r1, r6, #SIRFSOC_PWRC_PDN_CTRL
bl sirfsoc_rtc_iobrg_pre_writel
mov r1, #0x1
@ read the MEM ctl register and set the self
@ refresh bit
ldr r2, [r5, #DENALI_CTL_22_OFF]
orr r2, r2, #0x1
@ Following code has to run from cache since
@ the RAM is going to self refresh mode
.align 5
str r2, [r5, #DENALI_CTL_22_OFF]
1:
ldr r4, [r5, #DENALI_CTL_112_OFF]
tst r4, #0x1
bne 1b
@ write SLEEPFORCE through rtc iobridge
str r1, [r7]
@ wait rtc io bridge sync
1:
ldr r3, [r7]
tst r3, #0x01
bne 1b
b .

13
arch/arm/mach-tango/Kconfig
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@ -1,13 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
config ARCH_TANGO
bool "Sigma Designs Tango4 (SMP87xx)"
depends on ARCH_MULTI_V7
# Cortex-A9 MPCore r3p0, PL310 r3p2
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420
select ARM_GIC
select CLKSRC_TANGO_XTAL
select HAVE_ARM_SCU
select HAVE_ARM_TWD
select TANGO_IRQ

4
arch/arm/mach-tango/Makefile
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@ -1,4 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += setup.o smc.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_SUSPEND) += pm.o

52
arch/arm/mach-tango/platsmp.c
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@ -1,52 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/smp.h>
#include "smc.h"
static int tango_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
tango_set_aux_boot_addr(__pa_symbol(secondary_startup));
tango_start_aux_core(cpu);
return 0;
}
#ifdef CONFIG_HOTPLUG_CPU
/*
* cpu_kill() and cpu_die() run concurrently on different cores.
* Firmware will only "kill" a core once it has properly "died".
* Try a few times to kill a core before giving up, and sleep
* between tries to give that core enough time to die.
*/
static int tango_cpu_kill(unsigned int cpu)
{
int i, err;
for (i = 0; i < 10; ++i) {
msleep(10);
err = tango_aux_core_kill(cpu);
if (!err)
return true;
}
return false;
}
static void tango_cpu_die(unsigned int cpu)
{
while (tango_aux_core_die(cpu) < 0)
cpu_relax();
panic("cpu %d failed to die\n", cpu);
}
#endif
static const struct smp_operations tango_smp_ops __initconst = {
.smp_boot_secondary = tango_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = tango_cpu_kill,
.cpu_die = tango_cpu_die,
#endif
};
CPU_METHOD_OF_DECLARE(tango4_smp, "sigma,tango4-smp", &tango_smp_ops);

31
arch/arm/mach-tango/pm.c
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@ -1,31 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/init.h>
#include <linux/suspend.h>
#include <asm/suspend.h>
#include "smc.h"
#include "pm.h"
static int tango_pm_powerdown(unsigned long arg)
{
tango_suspend(__pa_symbol(cpu_resume));
return -EIO; /* tango_suspend has failed */
}
static int tango_pm_enter(suspend_state_t state)
{
if (state == PM_SUSPEND_MEM)
return cpu_suspend(0, tango_pm_powerdown);
return -EINVAL;
}
static const struct platform_suspend_ops tango_pm_ops = {
.enter = tango_pm_enter,
.valid = suspend_valid_only_mem,
};
void __init tango_pm_init(void)
{
suspend_set_ops(&tango_pm_ops);
}

7
arch/arm/mach-tango/pm.h
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@ -1,7 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifdef CONFIG_SUSPEND
void __init tango_pm_init(void);
#else
#define tango_pm_init NULL
#endif

20
arch/arm/mach-tango/setup.c
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@ -1,20 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include <asm/mach/arch.h>
#include <asm/hardware/cache-l2x0.h>
#include "smc.h"
#include "pm.h"
static void tango_l2c_write(unsigned long val, unsigned int reg)
{
if (reg == L2X0_CTRL)
tango_set_l2_control(val);
}
static const char *const tango_dt_compat[] = { "sigma,tango4", NULL };
DT_MACHINE_START(TANGO_DT, "Sigma Tango DT")
.dt_compat = tango_dt_compat,
.l2c_aux_mask = ~0,
.l2c_write_sec = tango_l2c_write,
.init_late = tango_pm_init,
MACHINE_END

12
arch/arm/mach-tango/smc.S
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@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/linkage.h>
.arch armv7-a
.arch_extension sec
ENTRY(tango_smc)
push {lr}
mov ip, r1
dsb /* This barrier is probably unnecessary */
smc #0
pop {pc}
ENDPROC(tango_smc)

9
arch/arm/mach-tango/smc.h
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@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
extern int tango_smc(unsigned int val, unsigned int service);
#define tango_set_l2_control(val) tango_smc(val, 0x102)
#define tango_start_aux_core(val) tango_smc(val, 0x104)
#define tango_set_aux_boot_addr(val) tango_smc(val, 0x105)
#define tango_suspend(val) tango_smc(val, 0x120)
#define tango_aux_core_die(val) tango_smc(val, 0x121)
#define tango_aux_core_kill(val) tango_smc(val, 0x122)

32
arch/arm/mach-u300/Kconfig
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@ -1,32 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
menuconfig ARCH_U300
bool "ST-Ericsson U300 Series"
depends on ARCH_MULTI_V5 && MMU
select ARM_AMBA
select ARM_VIC
select U300_TIMER
select CPU_ARM926T
select GPIOLIB
select HAVE_TCM
select PINCTRL
select PINCTRL_COH901
select PINCTRL_U300
select MFD_SYSCON
help
Support for ST-Ericsson U300 series mobile platforms.
if ARCH_U300
config MACH_U300
depends on ARCH_U300
bool "U300"
default y
config U300_DEBUG
depends on ARCH_U300
bool "Debug support for U300"
depends on PM
help
Debug support for U300 in sysfs, procfs etc.
endif

8
arch/arm/mach-u300/Makefile
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@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for the linux kernel, U300 machine.
#
obj-y := core.o
obj-$(CONFIG_REGULATOR_AB3100) += regulator.o

413
arch/arm/mach-u300/core.c
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@ -1,413 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* arch/arm/mach-u300/core.c
*
* Copyright (C) 2007-2012 ST-Ericsson SA
* Core platform support, IRQ handling and device definitions.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <linux/kernel.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_data/clk-u300.h>
#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/clocksource.h>
#include <linux/clk.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
/*
* These are the large blocks of memory allocated for I/O.
* the defines are used for setting up the I/O memory mapping.
*/
/* NAND Flash CS0 */
#define U300_NAND_CS0_PHYS_BASE 0x80000000
/* NFIF */
#define U300_NAND_IF_PHYS_BASE 0x9f800000
/* ALE, CLE offset for FSMC NAND */
#define PLAT_NAND_CLE (1 << 16)
#define PLAT_NAND_ALE (1 << 17)
/* AHB Peripherals */
#define U300_AHB_PER_PHYS_BASE 0xa0000000
#define U300_AHB_PER_VIRT_BASE 0xff010000
/* FAST Peripherals */
#define U300_FAST_PER_PHYS_BASE 0xc0000000
#define U300_FAST_PER_VIRT_BASE 0xff020000
/* SLOW Peripherals */
#define U300_SLOW_PER_PHYS_BASE 0xc0010000
#define U300_SLOW_PER_VIRT_BASE 0xff000000
/* Boot ROM */
#define U300_BOOTROM_PHYS_BASE 0xffff0000
#define U300_BOOTROM_VIRT_BASE 0xffff0000
/* SEMI config base */
#define U300_SEMI_CONFIG_BASE 0x2FFE0000
/*
* AHB peripherals
*/
/* AHB Peripherals Bridge Controller */
#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
/* Vectored Interrupt Controller 0, servicing 32 interrupts */
#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
/* Vectored Interrupt Controller 1, servicing 32 interrupts */
#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
/* Memory Stick Pro (MSPRO) controller */
#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
/* EMIF Configuration Area */
#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
/*
* FAST peripherals
*/
/* FAST bridge control */
#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
/* MMC/SD controller */
#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
/* PCM I2S0 controller */
#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
/* PCM I2S1 controller */
#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
/* I2C0 controller */
#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
/* I2C1 controller */
#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
/* SPI controller */
#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
/* Fast UART1 on U335 only */
#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
/*
* SLOW peripherals
*/
/* SLOW bridge control */
#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
/* SYSCON */
#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
/* Watchdog */
#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
/* UART0 */
#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
/* APP side special timer */
#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
/* Keypad */
#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
/* GPIO */
#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
/* RTC */
#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
/* Bus tracer */
#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
/* Event handler (hardware queue) */
#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
/* Genric Timer */
#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
/* PPM */
#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
/*
* REST peripherals
*/
/* ISP (image signal processor) */
#define U300_ISP_BASE (0xA0008000)
/* DMA Controller base */
#define U300_DMAC_BASE (0xC0020000)
/* MSL Base */
#define U300_MSL_BASE (0xc0022000)
/* APEX Base */
#define U300_APEX_BASE (0xc0030000)
/* Video Encoder Base */
#define U300_VIDEOENC_BASE (0xc0080000)
/* XGAM Base */
#define U300_XGAM_BASE (0xd0000000)
/*
* SYSCON addresses applicable to the core machine.
*/
/* Chip ID register 16bit (R/-) */
#define U300_SYSCON_CIDR (0x400)
/* SMCR */
#define U300_SYSCON_SMCR (0x4d0)
#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
#define U300_SYSCON_CSDR (0x4f0)
#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
/* PRINT_CONTROL Print Control 16bit (R/-) */
#define U300_SYSCON_PCR (0x4f8)
#define U300_SYSCON_PCR_SERV_IND (0x0001)
/* BOOT_CONTROL 16bit (R/-) */
#define U300_SYSCON_BCR (0x4fc)
#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
static void __iomem *syscon_base;
/*
* Static I/O mappings that are needed for booting the U300 platforms. The
* only things we need are the areas where we find the timer, syscon and
* intcon, since the remaining device drivers will map their own memory
* physical to virtual as the need arise.
*/
static struct map_desc u300_io_desc[] __initdata = {
{
.virtual = U300_SLOW_PER_VIRT_BASE,
.pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
.length = SZ_64K,
.type = MT_DEVICE,
},
{
.virtual = U300_AHB_PER_VIRT_BASE,
.pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
.length = SZ_32K,
.type = MT_DEVICE,
},
{
.virtual = U300_FAST_PER_VIRT_BASE,
.pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
.length = SZ_32K,
.type = MT_DEVICE,
},
};
static void __init u300_map_io(void)
{
iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
}
static unsigned long pin_pullup_conf[] = {
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
};
static unsigned long pin_highz_conf[] = {
PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
};
/* Pin control settings */
static const struct pinctrl_map u300_pinmux_map[] = {
/* anonymous maps for chip power and EMIFs */
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
/* per-device maps for MMC/SD, SPI and UART */
PIN_MAP_MUX_GROUP_DEFAULT("mmci", "pinctrl-u300", NULL, "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
/* This pin is used for clock return rather than GPIO */
PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
pin_pullup_conf),
/* This pin is used for card detect */
PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
pin_highz_conf),
};
struct db_chip {
u16 chipid;
const char *name;
};
/*
* This is a list of the Digital Baseband chips used in the U300 platform.
*/
static struct db_chip db_chips[] __initdata = {
{
.chipid = 0xb800,
.name = "DB3000",
},
{
.chipid = 0xc000,
.name = "DB3100",
},
{
.chipid = 0xc800,
.name = "DB3150",
},
{
.chipid = 0xd800,
.name = "DB3200",
},
{
.chipid = 0xe000,
.name = "DB3250",
},
{
.chipid = 0xe800,
.name = "DB3210",
},
{
.chipid = 0xf000,
.name = "DB3350 P1x",
},
{
.chipid = 0xf100,
.name = "DB3350 P2x",
},
{
.chipid = 0x0000, /* List terminator */
.name = NULL,
}
};
static void __init u300_init_check_chip(void)
{
u16 val;
struct db_chip *chip;
const char *chipname;
const char unknown[] = "UNKNOWN";
/* Read out and print chip ID */
val = readw(syscon_base + U300_SYSCON_CIDR);
/* This is in funky bigendian order... */
val = (val & 0xFFU) << 8 | (val >> 8);
chip = db_chips;
chipname = unknown;
for ( ; chip->chipid; chip++) {
if (chip->chipid == (val & 0xFF00U)) {
chipname = chip->name;
break;
}
}
printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
"(chip ID 0x%04x)\n", chipname, val);
if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
printk(KERN_ERR "Platform configured for BS335 " \
" with DB3350 but %s detected, expect problems!",
chipname);
}
}
/* Forward declare this function from the watchdog */
void coh901327_watchdog_reset(void);
static void u300_restart(enum reboot_mode mode, const char *cmd)
{
switch (mode) {
case REBOOT_SOFT:
case REBOOT_HARD:
#ifdef CONFIG_COH901327_WATCHDOG
coh901327_watchdog_reset();
#endif
break;
default:
/* Do nothing */
break;
}
/* Wait for system do die/reset. */
while (1);
}
/* These are mostly to get the right device names for the clock lookups */
static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
"pinctrl-u300", NULL),
OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
"u300-gpio", NULL),
OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
"coh901327_wdog", NULL),
OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
"rtc-coh901331", NULL),
OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
"coh901318", NULL),
OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
"fsmc-nand", NULL),
OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
"uart0", NULL),
OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
"uart1", NULL),
OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
"pl022", NULL),
OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
"stu300.0", NULL),
OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
"stu300.1", NULL),
OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
"mmci", NULL),
{ /* sentinel */ },
};
static void __init u300_init_irq_dt(void)
{
struct device_node *syscon;
struct clk *clk;
syscon = of_find_node_by_path("/syscon@c0011000");
if (!syscon) {
pr_crit("could not find syscon node\n");
return;
}
syscon_base = of_iomap(syscon, 0);
if (!syscon_base) {
pr_crit("could not remap syscon\n");
return;
}
/* initialize clocking early, we want to clock the INTCON */
u300_clk_init(syscon_base);
/* Bootstrap EMIF and SEMI clocks */
clk = clk_get_sys("pl172", NULL);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
clk = clk_get_sys("semi", NULL);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
/* Clock the interrupt controller */
clk = clk_get_sys("intcon", NULL);
BUG_ON(IS_ERR(clk));
clk_prepare_enable(clk);
irqchip_init();
}
static void __init u300_init_machine_dt(void)
{
u16 val;
/* Check what platform we run and print some status information */
u300_init_check_chip();
/* Initialize pinmuxing */
pinctrl_register_mappings(u300_pinmux_map,
ARRAY_SIZE(u300_pinmux_map));
of_platform_default_populate(NULL, u300_auxdata_lookup, NULL);
/* Enable SEMI self refresh */
val = readw(syscon_base + U300_SYSCON_SMCR) |
U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
writew(val, syscon_base + U300_SYSCON_SMCR);
}
static const char * u300_board_compat[] = {
"stericsson,u300",
NULL,
};
DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
.map_io = u300_map_io,
.init_irq = u300_init_irq_dt,
.init_time = timer_probe,
.init_machine = u300_init_machine_dt,
.restart = u300_restart,
.dt_compat = u300_board_compat,
MACHINE_END

134
arch/arm/mach-u300/regulator.c
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@ -1,134 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-u300/regulator.c
*
* Copyright (C) 2009 ST-Ericsson AB
* Handle board-bound regulators and board power not related
* to any devices.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <linux/device.h>
#include <linux/signal.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/consumer.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
/* Power Management Control 16bit (R/W) */
#define U300_SYSCON_PMCR (0x50)
#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
/*
* Regulators that power the board and chip and which are
* not copuled to specific drivers are hogged in these
* instances.
*/
static struct regulator *main_power_15;
/*
* This function is used from pm.h to shut down the system by
* resetting all regulators in turn and then disable regulator
* LDO D (main power).
*/
void u300_pm_poweroff(void)
{
sigset_t old, all;
sigfillset(&all);
if (!sigprocmask(SIG_BLOCK, &all, &old)) {
/* Disable LDO D to shut down the system */
if (main_power_15)
regulator_disable(main_power_15);
else
pr_err("regulator not available to shut down system\n");
(void) sigprocmask(SIG_SETMASK, &old, NULL);
}
return;
}
/*
* Hog the regulators needed to power up the board.
*/
static int __init __u300_init_boardpower(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *syscon_np;
struct regmap *regmap;
int err;
pr_info("U300: setting up board power\n");
syscon_np = of_parse_phandle(np, "syscon", 0);
if (!syscon_np) {
pr_crit("U300: no syscon node\n");
return -ENODEV;
}
regmap = syscon_node_to_regmap(syscon_np);
if (IS_ERR(regmap)) {
pr_crit("U300: could not locate syscon regmap\n");
return PTR_ERR(regmap);
}
main_power_15 = regulator_get(&pdev->dev, "vana15");
if (IS_ERR(main_power_15)) {
pr_err("could not get vana15");
return PTR_ERR(main_power_15);
}
err = regulator_enable(main_power_15);
if (err) {
pr_err("could not enable vana15\n");
return err;
}
/*
* On U300 a special system controller register pulls up the DC
* until the vana15 (LDO D) regulator comes up. At this point, all
* regulators are set and we do not need power control via
* DC ON anymore. This function will likely be moved whenever
* the rest of the U300 power management is implemented.
*/
pr_info("U300: disable system controller pull-up\n");
regmap_update_bits(regmap, U300_SYSCON_PMCR,
U300_SYSCON_PMCR_DCON_ENABLE, 0);
/* Register globally exported PM poweroff hook */
pm_power_off = u300_pm_poweroff;
return 0;
}
static int __init s365_board_probe(struct platform_device *pdev)
{
return __u300_init_boardpower(pdev);
}
static const struct of_device_id s365_board_match[] = {
{ .compatible = "stericsson,s365" },
{},
};
static struct platform_driver s365_board_driver = {
.driver = {
.name = "s365-board",
.of_match_table = s365_board_match,
},
};
/*
* So at module init time we hog the regulator!
*/
static int __init u300_init_boardpower(void)
{
return platform_driver_probe(&s365_board_driver,
s365_board_probe);
}
device_initcall(u300_init_boardpower);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Linus Walleij");

21
arch/arm/mach-zx/Kconfig
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@ -1,21 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
menuconfig ARCH_ZX
bool "ZTE ZX family"
depends on ARCH_MULTI_V7
help
Support for ZTE ZX-based family of processors. TV
set-top-box processor is supported. More will be
added soon.
if ARCH_ZX
config SOC_ZX296702
def_bool y
select ARM_GIC
select ARM_GLOBAL_TIMER
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select PM_GENERIC_DOMAINS if PM
help
Support for ZTE ZX296702 SoC which is a dual core CortexA9MP
endif

3
arch/arm/mach-zx/Makefile
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@ -1,3 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_SOC_ZX296702) += zx296702.o zx296702-pm-domain.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o

16
arch/arm/mach-zx/core.h
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@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2014 Linaro Ltd.
* Copyright (C) 2014 ZTE Corporation.
*/
#ifndef __MACH_ZX_CORE_H
#define __MACH_ZX_CORE_H
extern void zx_resume_jump(void);
extern size_t zx_suspend_iram_sz;
extern unsigned long zx_secondary_startup_pa;
void zx_secondary_startup(void);
#endif /* __MACH_ZX_CORE_H */

30
arch/arm/mach-zx/headsmp.S
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@ -1,30 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2014 Linaro Ltd.
* Copyright (C) 2014 ZTE Corporation.
*/
#include <linux/linkage.h>
.align 3
.arm
/* It runs from physical address */
ENTRY(zx_resume_jump)
adr r1, zx_secondary_startup_pa
ldr r0, [r1]
bx r0
ENDPROC(zx_resume_jump)
ENTRY(zx_secondary_startup_pa)
.word zx_secondary_startup_pa
ENTRY(zx_suspend_iram_sz)
.word . - zx_resume_jump
ENDPROC(zx_secondary_startup_pa)
ENTRY(zx_secondary_startup)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(zx_secondary_startup)

186
arch/arm/mach-zx/platsmp.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2014 Linaro Ltd.
* Copyright (C) 2014 ZTE Corporation.
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/smp.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/fncpy.h>
#include <asm/proc-fns.h>
#include <asm/smp_scu.h>
#include <asm/smp_plat.h>
#include "core.h"
#define AON_SYS_CTRL_RESERVED1 0xa8
#define BUS_MATRIX_REMAP_CONFIG 0x00
#define PCU_CPU0_CTRL 0x00
#define PCU_CPU1_CTRL 0x04
#define PCU_CPU1_ST 0x0c
#define PCU_GLOBAL_CTRL 0x14
#define PCU_EXPEND_CONTROL 0x34
#define ZX_IRAM_BASE 0x00200000
static void __iomem *pcu_base;
static void __iomem *matrix_base;
static void __iomem *scu_base;
void __init zx_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np;
unsigned long base = 0;
void __iomem *aonsysctrl_base;
void __iomem *sys_iram;
base = scu_a9_get_base();
scu_base = ioremap(base, SZ_256);
if (!scu_base) {
pr_err("%s: failed to map scu\n", __func__);
return;
}
scu_enable(scu_base);
np = of_find_compatible_node(NULL, NULL, "zte,sysctrl");
if (!np) {
pr_err("%s: failed to find sysctrl node\n", __func__);
return;
}
aonsysctrl_base = of_iomap(np, 0);
if (!aonsysctrl_base) {
pr_err("%s: failed to map aonsysctrl\n", __func__);
of_node_put(np);
return;
}
/*
* Write the address of secondary startup into the
* system-wide flags register. The BootMonitor waits
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
__raw_writel(__pa_symbol(zx_secondary_startup),
aonsysctrl_base + AON_SYS_CTRL_RESERVED1);
iounmap(aonsysctrl_base);
of_node_put(np);
np = of_find_compatible_node(NULL, NULL, "zte,zx296702-pcu");
pcu_base = of_iomap(np, 0);
of_node_put(np);
WARN_ON(!pcu_base);
np = of_find_compatible_node(NULL, NULL, "zte,zx-bus-matrix");
matrix_base = of_iomap(np, 0);
of_node_put(np);
WARN_ON(!matrix_base);
/* Map the first 4 KB IRAM for suspend usage */
sys_iram = __arm_ioremap_exec(ZX_IRAM_BASE, PAGE_SIZE, false);
zx_secondary_startup_pa = __pa_symbol(zx_secondary_startup);
fncpy(sys_iram, &zx_resume_jump, zx_suspend_iram_sz);
}
static int zx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
static bool first_boot = true;
if (first_boot) {
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
first_boot = false;
return 0;
}
/* Swap the base address mapping between IRAM and IROM */
writel_relaxed(0x1, matrix_base + BUS_MATRIX_REMAP_CONFIG);
/* Power on CPU1 */
writel_relaxed(0x0, pcu_base + PCU_CPU1_CTRL);
/* Wait for power on ack */
while (readl_relaxed(pcu_base + PCU_CPU1_ST) & 0x4)
cpu_relax();
/* Swap back the mapping of IRAM and IROM */
writel_relaxed(0x0, matrix_base + BUS_MATRIX_REMAP_CONFIG);
return 0;
}
#ifdef CONFIG_HOTPLUG_CPU
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
asm volatile(
"mcr p15, 0, %1, c7, c5, 0\n"
" mcr p15, 0, %1, c7, c10, 4\n"
/*
* Turn off coherency
*/
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, %3\n"
" mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "r" (0), "Ir" (CR_C), "Ir" (0x40)
: "cc");
}
static int zx_cpu_kill(unsigned int cpu)
{
unsigned long timeout = jiffies + msecs_to_jiffies(2000);
writel_relaxed(0x2, pcu_base + PCU_CPU1_CTRL);
while ((readl_relaxed(pcu_base + PCU_CPU1_ST) & 0x3) != 0x0) {
if (time_after(jiffies, timeout)) {
pr_err("*** cpu1 poweroff timeout\n");
break;
}
}
return 1;
}
static void zx_cpu_die(unsigned int cpu)
{
scu_power_mode(scu_base, SCU_PM_POWEROFF);
cpu_enter_lowpower();
while (1)
cpu_do_idle();
}
#endif
static void zx_secondary_init(unsigned int cpu)
{
scu_power_mode(scu_base, SCU_PM_NORMAL);
}
static const struct smp_operations zx_smp_ops __initconst = {
.smp_prepare_cpus = zx_smp_prepare_cpus,
.smp_secondary_init = zx_secondary_init,
.smp_boot_secondary = zx_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = zx_cpu_kill,
.cpu_die = zx_cpu_die,
#endif
};
CPU_METHOD_OF_DECLARE(zx_smp, "zte,zx296702-smp", &zx_smp_ops);

202
arch/arm/mach-zx/zx296702-pm-domain.c
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@ -1,202 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Linaro Ltd.
*
* Author: Jun Nie <jun.nie@linaro.org>
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/slab.h>
#define PCU_DM_CLKEN 0x18
#define PCU_DM_RSTEN 0x1C
#define PCU_DM_ISOEN 0x20
#define PCU_DM_PWRDN 0x24
#define PCU_DM_ACK_SYNC 0x28
enum {
PCU_DM_NEON0 = 0,
PCU_DM_NEON1,
PCU_DM_GPU,
PCU_DM_DECPPU,
PCU_DM_VOU,
PCU_DM_R2D,
PCU_DM_TOP,
};
static void __iomem *pcubase;
struct zx_pm_domain {
struct generic_pm_domain dm;
unsigned int bit;
};
static int normal_power_off(struct generic_pm_domain *domain)
{
struct zx_pm_domain *zpd = (struct zx_pm_domain *)domain;
unsigned long loop = 1000;
u32 tmp;
tmp = readl_relaxed(pcubase + PCU_DM_CLKEN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp, pcubase + PCU_DM_CLKEN);
udelay(5);
tmp = readl_relaxed(pcubase + PCU_DM_ISOEN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_ISOEN);
udelay(5);
tmp = readl_relaxed(pcubase + PCU_DM_RSTEN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp, pcubase + PCU_DM_RSTEN);
udelay(5);
tmp = readl_relaxed(pcubase + PCU_DM_PWRDN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_PWRDN);
do {
tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit);
} while (--loop && !tmp);
if (!loop) {
pr_err("Error: %s %s fail\n", __func__, domain->name);
return -EIO;
}
return 0;
}
static int normal_power_on(struct generic_pm_domain *domain)
{
struct zx_pm_domain *zpd = (struct zx_pm_domain *)domain;
unsigned long loop = 10000;
u32 tmp;
tmp = readl_relaxed(pcubase + PCU_DM_PWRDN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp, pcubase + PCU_DM_PWRDN);
do {
tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit);
} while (--loop && tmp);
if (!loop) {
pr_err("Error: %s %s fail\n", __func__, domain->name);
return -EIO;
}
tmp = readl_relaxed(pcubase + PCU_DM_RSTEN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_RSTEN);
udelay(5);
tmp = readl_relaxed(pcubase + PCU_DM_ISOEN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp, pcubase + PCU_DM_ISOEN);
udelay(5);
tmp = readl_relaxed(pcubase + PCU_DM_CLKEN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_CLKEN);
udelay(5);
return 0;
}
static struct zx_pm_domain gpu_domain = {
.dm = {
.name = "gpu_domain",
.power_off = normal_power_off,
.power_on = normal_power_on,
},
.bit = PCU_DM_GPU,
};
static struct zx_pm_domain decppu_domain = {
.dm = {
.name = "decppu_domain",
.power_off = normal_power_off,
.power_on = normal_power_on,
},
.bit = PCU_DM_DECPPU,
};
static struct zx_pm_domain vou_domain = {
.dm = {
.name = "vou_domain",
.power_off = normal_power_off,
.power_on = normal_power_on,
},
.bit = PCU_DM_VOU,
};
static struct zx_pm_domain r2d_domain = {
.dm = {
.name = "r2d_domain",
.power_off = normal_power_off,
.power_on = normal_power_on,
},
.bit = PCU_DM_R2D,
};
static struct generic_pm_domain *zx296702_pm_domains[] = {
&vou_domain.dm,
&gpu_domain.dm,
&decppu_domain.dm,
&r2d_domain.dm,
};
static int zx296702_pd_probe(struct platform_device *pdev)
{
struct genpd_onecell_data *genpd_data;
struct resource *res;
int i;
genpd_data = devm_kzalloc(&pdev->dev, sizeof(*genpd_data), GFP_KERNEL);
if (!genpd_data)
return -ENOMEM;
genpd_data->domains = zx296702_pm_domains;
genpd_data->num_domains = ARRAY_SIZE(zx296702_pm_domains);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "no memory resource defined\n");
return -ENODEV;
}
pcubase = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pcubase)) {
dev_err(&pdev->dev, "ioremap fail.\n");
return -EIO;
}
for (i = 0; i < ARRAY_SIZE(zx296702_pm_domains); ++i)
pm_genpd_init(zx296702_pm_domains[i], NULL, false);
of_genpd_add_provider_onecell(pdev->dev.of_node, genpd_data);
return 0;
}
static const struct of_device_id zx296702_pm_domain_matches[] __initconst = {
{ .compatible = "zte,zx296702-pcu", },
{ },
};
static struct platform_driver zx296702_pd_driver __initdata = {
.driver = {
.name = "zx-powerdomain",
.owner = THIS_MODULE,
.of_match_table = zx296702_pm_domain_matches,
},
.probe = zx296702_pd_probe,
};
static int __init zx296702_pd_init(void)
{
return platform_driver_register(&zx296702_pd_driver);
}
subsys_initcall(zx296702_pd_init);

22
arch/arm/mach-zx/zx296702.c
View File

@ -1,22 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2014 Linaro Ltd.
* Copyright (C) 2014 ZTE Corporation.
*/
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
static const char *const zx296702_dt_compat[] __initconst = {
"zte,zx296702",
NULL,
};
DT_MACHINE_START(ZX, "ZTE ZX296702 (Device Tree)")
.dt_compat = zx296702_dt_compat,
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
MACHINE_END

1
arch/arm/mm/Kconfig
View File

@ -638,7 +638,6 @@ config CPU_V7M_NUM_IRQ
int "Number of external interrupts connected to the NVIC"
depends on CPU_V7M
default 90 if ARCH_STM32
default 38 if ARCH_EFM32
default 112 if SOC_VF610
default 240
help

6
arch/arm64/Kconfig.platforms
View File

@ -317,12 +317,6 @@ config ARCH_XGENE
help
This enables support for AppliedMicro X-Gene SOC Family
config ARCH_ZX
bool "ZTE ZX SoC Family"
select PINCTRL
help
This enables support for ZTE ZX SoC Family
config ARCH_ZYNQMP
bool "Xilinx ZynqMP Family"
help

1
arch/arm64/boot/dts/Makefile
View File

@ -29,4 +29,3 @@ subdir-y += synaptics
subdir-y += ti
subdir-y += toshiba
subdir-y += xilinx
subdir-y += zte

3
arch/arm64/boot/dts/zte/Makefile
View File

@ -1,3 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_ZX) += zx296718-evb.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296718-pcbox.dtb

144
arch/arm64/boot/dts/zte/zx296718-evb.dts
View File

@ -1,144 +0,0 @@
/*
* Copyright 2016 ZTE Corporation.
* Copyright 2016 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "zx296718.dtsi"
/ {
model = "ZTE zx296718 evaluation board";
compatible = "zte,zx296718-evb", "zte,zx296718";
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x40000000>;
};
sound-spdif0 {
compatible = "audio-graph-card";
dais = <&spdif0_port>;
};
sound-i2s0 {
compatible = "audio-graph-card";
dais = <&i2s0_port>;
pinctrl-names = "default";
pinctrl-0 = <&amplifier_pins>;
pa-gpios = <&bgpio4 0 GPIO_ACTIVE_HIGH>;
widgets = "Line", "Line Out Jack";
routing = "Amplifier", "LINEOUTL",
"Amplifier", "LINEOUTR",
"Line Out Jack", "Amplifier";
};
};
&aud96p22 {
port {
aud96p22_endpoint: endpoint {
remote-endpoint = <&i2s0_endpoint>;
};
};
};
&emmc {
status = "okay";
};
&hdmi {
status = "okay";
port {
hdmi_endpoint: endpoint {
remote-endpoint = <&spdif0_endpoint>;
};
};
};
&i2c0 {
status = "okay";
};
&i2s0 {
status = "okay";
i2s0_port: port {
i2s0_endpoint: endpoint {
remote-endpoint = <&aud96p22_endpoint>;
dai-format = "i2s";
frame-master;
bitclock-master;
};
};
};
&pmm {
amplifier_pins: amplifier {
pins = "TSI3_DATA";
function = "BGPIO";
};
};
&sd1 {
status = "okay";
};
&spdif0 {
status = "okay";
spdif0_port: port {
spdif0_endpoint: endpoint {
remote-endpoint = <&hdmi_endpoint>;
};
};
};
&tvenc {
status = "okay";
};
&uart0 {
status = "okay";
};

143
arch/arm64/boot/dts/zte/zx296718-pcbox.dts
View File

@ -1,143 +0,0 @@
/*
* Copyright (C) 2017 Sanechips Technology Co., Ltd.
* Copyright 2017 Linaro Ltd.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "zx296718.dtsi"
#include <dt-bindings/pwm/pwm.h>
/ {
model = "ZTE ZX296718 PCBOX Board";
compatible = "zte,zx296718-pcbox", "zte,zx296718";
chosen {
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
a53_vdd0v9: regulator-a53 {
compatible = "pwm-regulator";
pwms = <&pwm 3 1250 PWM_POLARITY_INVERTED>;
regulator-name = "A53_VDD0V9";
regulator-min-microvolt = <855000>;
regulator-max-microvolt = <1183000>;
pwm-dutycycle-unit = <100>;
pwm-dutycycle-range = <0 100>;
regulator-always-on;
regulator-boot-on;
};
sound-spdif0 {
compatible = "audio-graph-card";
dais = <&spdif0_port>;
};
sound-i2s0 {
compatible = "audio-graph-card";
dais = <&i2s0_port>;
};
};
&aud96p22 {
port {
aud96p22_endpoint: endpoint {
remote-endpoint = <&i2s0_endpoint>;
};
};
};
&cpu0 {
cpu-supply = <&a53_vdd0v9>;
};
&emmc {
status = "okay";
};
&hdmi {
status = "disabled";
port {
hdmi_endpoint: endpoint {
remote-endpoint = <&spdif0_endpoint>;
};
};
};
&i2c0 {
status = "okay";
};
&i2s0 {
status = "okay";
i2s0_port: port {
i2s0_endpoint: endpoint {
remote-endpoint = <&aud96p22_endpoint>;
dai-format = "i2s";
frame-master;
bitclock-master;
};
};
};
&irdec {
status = "okay";
};
&pmm {
pwm3_pins: pwm3 {
pins = "KEY_ROW2";
function = "PWM";
};
vga_pins: vga {
pins = "KEY_COL1", "KEY_COL2", "VGA_HS", "VGA_VS";
function = "VGA";
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pins>;
status = "okay";
};
&sd0 {
status = "okay";
};
&sd1 {
status = "okay";
};
&spdif0 {
status = "okay";
spdif0_port: port {
spdif0_endpoint: endpoint {
remote-endpoint = <&hdmi_endpoint>;
};
};
};
&tvenc {
status = "disabled";
};
&uart0 {
status = "okay";
};
&vga {
pinctrl-names = "default";
pinctrl-0 = <&vga_pins>;
status = "okay";
};

627
arch/arm64/boot/dts/zte/zx296718.dtsi
View File

@ -1,627 +0,0 @@
/*
* Copyright 2016 ZTE Corporation.
* Copyright 2016 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/zx296718-clock.h>
/ {
compatible = "zte,zx296718";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
gpio0 = &bgpio0;
gpio1 = &bgpio1;
gpio2 = &bgpio2;
gpio3 = &bgpio3;
gpio4 = &bgpio4;
gpio5 = &bgpio5;
gpio6 = &bgpio6;
serial0 = &uart0;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
};
cluster0_opp: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <866000>;
clock-latency-ns = <500000>;
};
opp-648000000 {
opp-hz = /bits/ 64 <648000000>;
opp-microvolt = <866000>;
clock-latency-ns = <500000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <888000>;
clock-latency-ns = <500000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <898000>;
clock-latency-ns = <500000>;
};
opp-1188000000 {
opp-hz = /bits/ 64 <1188000000>;
opp-microvolt = <1015000>;
clock-latency-ns = <500000>;
};
};
clk24k: clk-24k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000>;
clock-output-names = "rtcclk";
};
osc32k: clk-osc32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-output-names = "osc32k";
};
osc12m: clk-osc12m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
clock-output-names = "osc12m";
};
osc24m: clk-osc24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc24m";
};
osc25m: clk-osc25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "osc25m";
};
osc60m: clk-osc60m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
clock-output-names = "osc60m";
};
osc99m: clk-osc99m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <99000000>;
clock-output-names = "osc99m";
};
osc125m: clk-osc125m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "osc125m";
};
osc198m: clk-osc198m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <198000000>;
clock-output-names = "osc198m";
};
pll_audio: clk-pll-884m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <884000000>;
clock-output-names = "pll_audio";
};
pll_ddr: clk-pll-932m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <932000000>;
clock-output-names = "pll_ddr";
};
pll_hsic: clk-pll-960m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <960000000>;
clock-output-names = "pll_hsic";
};
pll_mac: clk-pll-1000m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000000>;
clock-output-names = "pll_mac";
};
pll_mm0: clk-pll-1188m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1188000000>;
clock-output-names = "pll_mm0";
};
pll_mm1: clk-pll-1296m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1296000000>;
clock-output-names = "pll_mm1";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@2a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x02a00000 0x10000>,
<0x02b00000 0xc0000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
irdec: ir-decoder@111000 {
compatible = "zte,zx296718-irdec";
reg = <0x111000 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
aon_sysctrl: aon-sysctrl@116000 {
compatible = "zte,zx296718-aon-sysctrl", "syscon";
reg = <0x116000 0x1000>;
};
iocfg: pin-controller@119000 {
compatible = "zte,zx296718-iocfg";
reg = <0x119000 0x1000>;
};
uart0: uart@11f000 {
compatible = "arm,pl011", "arm,primecell";
arm,primecell-periphid = <0x001feffe>;
reg = <0x11f000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24m>;
clock-names = "apb_pclk";
status = "disabled";
};
sd0: mmc@1110000 {
compatible = "zte,zx296718-dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01110000 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <32>;
data-addr = <0x200>;
fifo-watermark-aligned;
bus-width = <4>;
clock-frequency = <50000000>;
clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
clock-names = "biu", "ciu";
max-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
sd-uhs-ddr50;
status = "disabled";
};
sd1: mmc@1111000 {
compatible = "zte,zx296718-dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01111000 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <32>;
data-addr = <0x200>;
fifo-watermark-aligned;
bus-width = <4>;
clock-frequency = <167000000>;
clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>;
clock-names = "biu", "ciu";
max-frequency = <167000000>;
cap-sdio-irq;
cap-sd-highspeed;
status = "disabled";
};
dma: dma-controller@1460000 {
compatible = "zte,zx296702-dma";
reg = <0x01460000 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24m>;
clock-names = "dmaclk";
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <32>;
};
lsp0crm: clock-controller@1420000 {
compatible = "zte,zx296718-lsp0crm";
reg = <0x01420000 0x1000>;
#clock-cells = <1>;
};
bgpio0: gpio@142d000 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d000 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 48 16>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio1: gpio@142d040 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d040 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 80 16>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio2: gpio@142d080 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d080 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 80 3
&pmm 3 32 4
&pmm 7 83 9>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio3: gpio@142d0c0 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d0c0 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 92 16>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio4: gpio@142d100 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d100 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 108 12
&pmm 12 121 4>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio5: gpio@142d140 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d140 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 125 16>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio6: gpio@142d180 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d180 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 141 2>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
lsp1crm: clock-controller@1430000 {
compatible = "zte,zx296718-lsp1crm";
reg = <0x01430000 0x1000>;
#clock-cells = <1>;
};
pwm: pwm@1439000 {
compatible = "zte,zx296718-pwm";
reg = <0x1439000 0x1000>;
clocks = <&lsp1crm LSP1_PWM_PCLK>,
<&lsp1crm LSP1_PWM_WCLK>;
clock-names = "pclk", "wclk";
#pwm-cells = <3>;
status = "disabled";
};
vou: vou@1440000 {
compatible = "zte,zx296718-vou";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1440000 0x10000>;
dpc: dpc@0 {
compatible = "zte,zx296718-dpc";
reg = <0x0000 0x1000>, <0x1000 0x1000>,
<0x5000 0x1000>, <0x6000 0x1000>,
<0xa000 0x1000>;
reg-names = "osd", "timing_ctrl",
"dtrc", "vou_ctrl",
"otfppu";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
<&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
clock-names = "aclk", "ppu_wclk",
"main_wclk", "aux_wclk";
};
vga: vga@8000 {
compatible = "zte,zx296718-vga";
reg = <0x8000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topcrm VGA_I2C_WCLK>;
clock-names = "i2c_wclk";
zte,vga-power-control = <&sysctrl 0x170 0xe0>;
status = "disabled";
};
hdmi: hdmi@c000 {
compatible = "zte,zx296718-hdmi";
reg = <0xc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
clocks = <&topcrm HDMI_OSC_CEC>,
<&topcrm HDMI_OSC_CLK>,
<&topcrm HDMI_XCLK>;
clock-names = "osc_cec", "osc_clk", "xclk";
#sound-dai-cells = <0>;
status = "disabled";
};
tvenc: tvenc@2000 {
compatible = "zte,zx296718-tvenc";
reg = <0x2000 0x1000>;
zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
status = "disabled";
};
};
topcrm: clock-controller@1461000 {
compatible = "zte,zx296718-topcrm";
reg = <0x01461000 0x1000>;
#clock-cells = <1>;
};
pmm: pin-controller@1462000 {
compatible = "zte,zx296718-pmm";
reg = <0x1462000 0x1000>;
zte,auxiliary-controller = <&iocfg>;
};
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
};
emmc: mmc@1470000{
compatible = "zte,zx296718-dw-mshc";
reg = <0x01470000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
zte,aon-syscon = <&aon_sysctrl>;
bus-width = <8>;
fifo-depth = <128>;
data-addr = <0x200>;
fifo-watermark-aligned;
clock-frequency = <167000000>;
clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>;
clock-names = "biu", "ciu";
max-frequency = <167000000>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
disable-wp;
status = "disabled";
};
audiocrm: clock-controller@1480000 {
compatible = "zte,zx296718-audiocrm";
reg = <0x01480000 0x1000>;
#clock-cells = <1>;
};
i2s0: i2s@1482000 {
compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
reg = <0x01482000 0x1000>;
clocks = <&audiocrm AUDIO_I2S0_WCLK>,
<&audiocrm AUDIO_I2S0_PCLK>;
clock-names = "wclk", "pclk";
assigned-clocks = <&audiocrm I2S0_WCLK_MUX>;
assigned-clock-parents = <&topcrm AUDIO_99M>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma 22>, <&dma 23>;
dma-names = "tx", "rx";
#sound-dai-cells = <0>;
status = "disabled";
};
i2c0: i2c@1486000 {
compatible = "zte,zx296718-i2c";
reg = <0x01486000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&audiocrm AUDIO_I2C0_WCLK>;
clock-frequency = <1600000>;
status = "disabled";
aud96p22: codec@22 {
compatible = "zte,zx-aud96p22";
#sound-dai-cells = <0>;
reg = <0x22>;
};
};
spdif0: spdif@1488000 {
compatible = "zte,zx296702-spdif";
reg = <0x1488000 0x1000>;
clocks = <&audiocrm AUDIO_SPDIF0_WCLK>;
clock-names = "tx";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#sound-dai-cells = <0>;
dmas = <&dma 30>;
dma-names = "tx";
status = "disabled";
};
};
};

113
arch/c6x/Kconfig
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@ -1,113 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
#
# For a description of the syntax of this configuration file,
# see Documentation/kbuild/kconfig-language.rst.
#
config C6X
def_bool y
select ARCH_32BIT_OFF_T
select ARCH_HAS_BINFMT_FLAT
select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select CLKDEV_LOOKUP
select HAVE_LEGACY_CLK
select GENERIC_ATOMIC64
select GENERIC_IRQ_SHOW
select HAVE_ARCH_TRACEHOOK
select SPARSE_IRQ
select IRQ_DOMAIN
select OF
select OF_EARLY_FLATTREE
select MODULES_USE_ELF_RELA
select MMU_GATHER_NO_RANGE if MMU
select SET_FS
config MMU
def_bool n
config FPU
def_bool n
config GENERIC_CALIBRATE_DELAY
def_bool y
config GENERIC_HWEIGHT
def_bool y
config GENERIC_BUG
def_bool y
depends on BUG
config C6X_BIG_KERNEL
bool "Build a big kernel"
help
The C6X function call instruction has a limited range of +/- 2MiB.
This is sufficient for most kernels, but some kernel configurations
with lots of compiled-in functionality may require a larger range
for function calls. Use this option to have the compiler generate
function calls with 32-bit range. This will make the kernel both
larger and slower.
If unsure, say N.
# Use the generic interrupt handling code in kernel/irq/
config CMDLINE_BOOL
bool "Default bootloader kernel arguments"
config CMDLINE
string "Kernel command line"
depends on CMDLINE_BOOL
default "console=ttyS0,57600"
help
On some architectures there is currently no way for the boot loader
to pass arguments to the kernel. For these architectures, you should
supply some command-line options at build time by entering them
here.
config CMDLINE_FORCE
bool "Force default kernel command string"
depends on CMDLINE_BOOL
default n
help
Set this to have arguments from the default kernel command string
override those passed by the boot loader.
config CPU_BIG_ENDIAN
bool "Build big-endian kernel"
default n
help
Say Y if you plan on running a kernel in big-endian mode.
Note that your board must be properly built and your board
port must properly enable any big-endian related features
of your chipset/board/processor.
config FORCE_MAX_ZONEORDER
int "Maximum zone order"
default "13"
help
The kernel memory allocator divides physically contiguous memory
blocks into "zones", where each zone is a power of two number of
pages. This option selects the largest power of two that the kernel
keeps in the memory allocator. If you need to allocate very large
blocks of physically contiguous memory, then you may need to
increase this value.
This config option is actually maximum order plus one. For example,
a value of 11 means that the largest free memory block is 2^10 pages.
menu "Processor type and features"
source "arch/c6x/platforms/Kconfig"
config KERNEL_RAM_BASE_ADDRESS
hex "Virtual address of memory base"
default 0xe0000000 if SOC_TMS320C6455
default 0xe0000000 if SOC_TMS320C6457
default 0xe0000000 if SOC_TMS320C6472
default 0x80000000
source "kernel/Kconfig.hz"
endmenu

10
arch/c6x/Kconfig.debug
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@ -1,10 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
config ACCESS_CHECK
bool "Check the user pointer address"
default y
help
Usually the pointer transfer from user space is checked to see if its
address is in the kernel space.
Say N here to disable that check to improve the performance.

60
arch/c6x/Makefile
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@ -1,60 +0,0 @@
#
# linux/arch/c6x/Makefile
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
KBUILD_DEFCONFIG := dsk6455_defconfig
cflags-y += -mno-dsbt -msdata=none -D__linux__
cflags-$(CONFIG_C6X_BIG_KERNEL) += -mlong-calls
KBUILD_CFLAGS_MODULE += -mlong-calls -mno-dsbt -msdata=none
CHECKFLAGS +=
KBUILD_CFLAGS += $(cflags-y)
KBUILD_AFLAGS += $(cflags-y)
ifdef CONFIG_CPU_BIG_ENDIAN
KBUILD_CFLAGS += -mbig-endian
KBUILD_AFLAGS += -mbig-endian
LINKFLAGS += -mbig-endian
KBUILD_LDFLAGS += -mbig-endian -EB
CHECKFLAGS += -D_BIG_ENDIAN
endif
head-y := arch/c6x/kernel/head.o
core-y += arch/c6x/kernel/ arch/c6x/mm/ arch/c6x/platforms/
libs-y += arch/c6x/lib/
# Default to vmlinux.bin, override when needed
all: vmlinux.bin
boot := arch/$(ARCH)/boot
# Are we making a dtbImage.<boardname> target? If so, crack out the boardname
DTB:=$(subst dtbImage.,,$(filter dtbImage.%, $(MAKECMDGOALS)))
export DTB
core-y += $(boot)/dts/
# With make 3.82 we cannot mix normal and wildcard targets
vmlinux.bin: vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
dtbImage.%: vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
archclean:
$(Q)$(MAKE) $(clean)=$(boot)
define archhelp
@echo ' vmlinux.bin - Binary kernel image (arch/$(ARCH)/boot/vmlinux.bin)'
@echo ' dtbImage.<dt> - ELF image with $(arch)/boot/dts/<dt>.dts linked in'
@echo ' - stripped elf with fdt blob'
endef

11
arch/c6x/boot/Makefile
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@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for bootable kernel images
#
OBJCOPYFLAGS_vmlinux.bin := -O binary
$(obj)/vmlinux.bin: vmlinux FORCE
$(call if_changed,objcopy)
$(obj)/dtbImage.%: vmlinux
$(call if_changed,objcopy)

16
arch/c6x/boot/dts/Makefile
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@ -1,16 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for device trees
#
DTC_FLAGS ?= -p 1024
dtb-$(CONFIG_SOC_TMS320C6455) += dsk6455.dtb
dtb-$(CONFIG_SOC_TMS320C6457) += evmc6457.dtb
dtb-$(CONFIG_SOC_TMS320C6472) += evmc6472.dtb
dtb-$(CONFIG_SOC_TMS320C6474) += evmc6474.dtb
dtb-$(CONFIG_SOC_TMS320C6678) += evmc6678.dtb
ifneq ($(DTB),)
obj-y += $(DTB).dtb.o
endif

57
arch/c6x/boot/dts/dsk6455.dts
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@ -1,57 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* arch/c6x/boot/dts/dsk6455.dts
*
* DSK6455 Evaluation Platform For TMS320C6455
* Copyright (C) 2011 Texas Instruments Incorporated
*
* Author: Mark Salter <msalter@redhat.com>
*/
/dts-v1/;
/include/ "tms320c6455.dtsi"
/ {
model = "Spectrum Digital DSK6455";
compatible = "spectrum-digital,dsk6455";
chosen {
bootargs = "root=/dev/nfs ip=dhcp rw";
};
memory {
device_type = "memory";
reg = <0xE0000000 0x08000000>;
};
soc {
megamod_pic: interrupt-controller@1800000 {
interrupts = < 12 13 14 15 >;
};
emifa@70000000 {
flash@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x3 0x0 0x400000>;
bank-width = <1>;
device-width = <1>;
partition@0 {
reg = <0x0 0x400000>;
label = "NOR";
};
};
};
timer1: timer@2980000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 69 >;
};
clock-controller@029a0000 {
clock-frequency = <50000000>;
};
};
};

43
arch/c6x/boot/dts/evmc6457.dts
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@ -1,43 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* arch/c6x/boot/dts/evmc6457.dts
*
* EVMC6457 Evaluation Platform For TMS320C6457
*
* Copyright (C) 2011 Texas Instruments Incorporated
*
* Author: Mark Salter <msalter@redhat.com>
*/
/dts-v1/;
/include/ "tms320c6457.dtsi"
/ {
model = "eInfochips EVMC6457";
compatible = "einfochips,evmc6457";
chosen {
bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
};
memory {
device_type = "memory";
reg = <0xE0000000 0x10000000>;
};
soc {
megamod_pic: interrupt-controller@1800000 {
interrupts = < 12 13 14 15 >;
};
timer0: timer@2940000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 67 >;
};
clock-controller@29a0000 {
clock-frequency = <60000000>;
};
};
};

68
arch/c6x/boot/dts/evmc6472.dts
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@ -1,68 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* arch/c6x/boot/dts/evmc6472.dts
*
* EVMC6472 Evaluation Platform For TMS320C6472
*
* Copyright (C) 2011 Texas Instruments Incorporated
*
* Author: Mark Salter <msalter@redhat.com>
*/
/dts-v1/;
/include/ "tms320c6472.dtsi"
/ {
model = "eInfochips EVMC6472";
compatible = "einfochips,evmc6472";
chosen {
bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
};
memory {
device_type = "memory";
reg = <0xE0000000 0x10000000>;
};
soc {
megamod_pic: interrupt-controller@1800000 {
interrupts = < 12 13 14 15 >;
};
timer0: timer@25e0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 16 >;
};
timer1: timer@25f0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 16 >;
};
timer2: timer@2600000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 16 >;
};
timer3: timer@2610000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 16 >;
};
timer4: timer@2620000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 16 >;
};
timer5: timer@2630000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 16 >;
};
clock-controller@29a0000 {
clock-frequency = <25000000>;
};
};
};

53
arch/c6x/boot/dts/evmc6474.dts
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* arch/c6x/boot/dts/evmc6474.dts
*
* EVMC6474 Evaluation Platform For TMS320C6474
*
* Copyright (C) 2011 Texas Instruments Incorporated
*
* Author: Mark Salter <msalter@redhat.com>
*/
/dts-v1/;
/include/ "tms320c6474.dtsi"
/ {
model = "Spectrum Digital EVMC6474";
compatible = "spectrum-digital,evmc6474";
chosen {
bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
};
memory {
device_type = "memory";
reg = <0x80000000 0x08000000>;
};
soc {
megamod_pic: interrupt-controller@1800000 {
interrupts = < 12 13 14 15 >;
};
timer3: timer@2940000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 39 >;
};
timer4: timer@2950000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 41 >;
};
timer5: timer@2960000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 43 >;
};
clock-controller@29a0000 {
clock-frequency = <50000000>;
};
};
};

78
arch/c6x/boot/dts/evmc6678.dts
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* arch/c6x/boot/dts/evmc6678.dts
*
* EVMC6678 Evaluation Platform For TMS320C6678
*
* Copyright (C) 2012 Texas Instruments Incorporated
*
* Author: Ken Cox <jkc@redhat.com>
*/
/dts-v1/;
/include/ "tms320c6678.dtsi"
/ {
model = "Advantech EVMC6678";
compatible = "advantech,evmc6678";
chosen {
bootargs = "root=/dev/nfs ip=dhcp rw";
};
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
soc {
megamod_pic: interrupt-controller@1800000 {
interrupts = < 12 13 14 15 >;
};
timer8: timer@2280000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 66 >;
};
timer9: timer@2290000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 68 >;
};
timer10: timer@22A0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 70 >;
};
timer11: timer@22B0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 72 >;
};
timer12: timer@22C0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 74 >;
};
timer13: timer@22D0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 76 >;
};
timer14: timer@22E0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 78 >;
};
timer15: timer@22F0000 {
interrupt-parent = <&megamod_pic>;
interrupts = < 80 >;
};
clock-controller@2310000 {
clock-frequency = <100000000>;
};
};
};

97
arch/c6x/boot/dts/tms320c6455.dtsi
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// SPDX-License-Identifier: GPL-2.0
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
model = "ti,c64x+";
reg = <0>;
};
};
soc {
compatible = "simple-bus";
model = "tms320c6455";
#address-cells = <1>;
#size-cells = <1>;
ranges;
core_pic: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
compatible = "ti,c64x+core-pic";
};
/*
* Megamodule interrupt controller
*/
megamod_pic: interrupt-controller@1800000 {
compatible = "ti,c64x+megamod-pic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x1800000 0x1000>;
interrupt-parent = <&core_pic>;
};
cache-controller@1840000 {
compatible = "ti,c64x+cache";
reg = <0x01840000 0x8400>;
};
emifa@70000000 {
compatible = "ti,c64x+emifa", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x70000000 0x100>;
ranges = <0x2 0x0 0xa0000000 0x00000008
0x3 0x0 0xb0000000 0x00400000
0x4 0x0 0xc0000000 0x10000000
0x5 0x0 0xD0000000 0x10000000>;
ti,dscr-dev-enable = <13>;
ti,emifa-burst-priority = <255>;
ti,emifa-ce-config = <0x00240120
0x00240120
0x00240122
0x00240122>;
};
timer1: timer@2980000 {
compatible = "ti,c64x+timer64";
reg = <0x2980000 0x40>;
ti,dscr-dev-enable = <4>;
};
clock-controller@029a0000 {
compatible = "ti,c6455-pll", "ti,c64x+pll";
reg = <0x029a0000 0x200>;
ti,c64x+pll-bypass-delay = <1440>;
ti,c64x+pll-reset-delay = <15360>;
ti,c64x+pll-lock-delay = <24000>;
};
device-state-config-regs@2a80000 {
compatible = "ti,c64x+dscr";
reg = <0x02a80000 0x41000>;
ti,dscr-devstat = <0>;
ti,dscr-silicon-rev = <8 28 0xf>;
ti,dscr-rmii-resets = <0 0x40020 0x00040000>;
ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
ti,dscr-devstate-ctl-regs =
<0 12 0x40008 1 0 0 2
12 1 0x40008 3 0 30 2
13 2 0x4002c 1 0xffffffff 0 1>;
ti,dscr-devstate-stat-regs =
<0 10 0x40014 1 0 0 3
10 2 0x40018 1 0 0 3>;
};
};
};

69
arch/c6x/boot/dts/tms320c6457.dtsi
View File

@ -1,69 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
model = "ti,c64x+";
reg = <0>;
};
};
soc {
compatible = "simple-bus";
model = "tms320c6457";
#address-cells = <1>;
#size-cells = <1>;
ranges;
core_pic: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
compatible = "ti,c64x+core-pic";
};
megamod_pic: interrupt-controller@1800000 {
compatible = "ti,c64x+megamod-pic";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&core_pic>;
reg = <0x1800000 0x1000>;
};
cache-controller@1840000 {
compatible = "ti,c64x+cache";
reg = <0x01840000 0x8400>;
};
device-state-controller@2880800 {
compatible = "ti,c64x+dscr";
reg = <0x02880800 0x400>;
ti,dscr-devstat = <0x20>;
ti,dscr-silicon-rev = <0x18 28 0xf>;
ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
0x118 0 0 1 2>;
ti,dscr-kick-regs = <0x38 0x83E70B13
0x3c 0x95A4F1E0>;
};
timer0: timer@2940000 {
compatible = "ti,c64x+timer64";
reg = <0x2940000 0x40>;
};
clock-controller@29a0000 {
compatible = "ti,c6457-pll", "ti,c64x+pll";
reg = <0x029a0000 0x200>;
ti,c64x+pll-bypass-delay = <300>;
ti,c64x+pll-reset-delay = <24000>;
ti,c64x+pll-lock-delay = <50000>;
};
};
};

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