mirror of https://gitee.com/openkylin/linux.git
ath9k_hw: fix stopping rx DMA during resets
During PHY errors, the MAC can sometimes fail to enter an idle state on older hardware (before AR9380) after an rx stop has been requested. This typically shows up in the kernel log with messages like these: ath: Could not stop RX, we could be confusing the DMA engine when we start RX up ------------[ cut here ]------------ WARNING: at drivers/net/wireless/ath/ath9k/recv.c:504 ath_stoprecv+0xcc/0xf0 [ath9k]() Call Trace: [<8023f0e8>] dump_stack+0x8/0x34 [<80075050>] warn_slowpath_common+0x78/0xa4 [<80075094>] warn_slowpath_null+0x18/0x24 [<80d66d60>] ath_stoprecv+0xcc/0xf0 [ath9k] [<80d642cc>] ath_set_channel+0xbc/0x270 [ath9k] [<80d65254>] ath_radio_disable+0x4a4/0x7fc [ath9k] When this happens, the state that the MAC enters is easy to identify and does not result in bogus DMA traffic, however to ensure a working state after a channel change, the hardware should still be reset. This patch adds detection for this specific MAC state, after which the above warnings completely disappear in my tests. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Cc: stable@kernel.org Cc: Kyungwan Nam <Kyungwan.Nam@Atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -1254,15 +1254,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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ah->txchainmask = common->tx_chainmask;
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ah->rxchainmask = common->rx_chainmask;
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if ((common->bus_ops->ath_bus_type != ATH_USB) && !ah->chip_fullsleep) {
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ath9k_hw_abortpcurecv(ah);
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if (!ath9k_hw_stopdmarecv(ah)) {
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ath_dbg(common, ATH_DBG_XMIT,
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"Failed to stop receive dma\n");
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bChannelChange = false;
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}
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}
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if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
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return -EIO;
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@ -751,28 +751,47 @@ void ath9k_hw_abortpcurecv(struct ath_hw *ah)
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}
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EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
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bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
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bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset)
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{
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#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
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#define AH_RX_TIME_QUANTUM 100 /* usec */
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struct ath_common *common = ath9k_hw_common(ah);
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u32 mac_status, last_mac_status = 0;
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int i;
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/* Enable access to the DMA observation bus */
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REG_WRITE(ah, AR_MACMISC,
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((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
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(AR_MACMISC_MISC_OBS_BUS_1 <<
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AR_MACMISC_MISC_OBS_BUS_MSB_S)));
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REG_WRITE(ah, AR_CR, AR_CR_RXD);
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/* Wait for rx enable bit to go low */
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for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
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if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
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break;
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if (!AR_SREV_9300_20_OR_LATER(ah)) {
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mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
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if (mac_status == 0x1c0 && mac_status == last_mac_status) {
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*reset = true;
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break;
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}
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last_mac_status = mac_status;
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}
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udelay(AH_TIME_QUANTUM);
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}
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if (i == 0) {
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ath_err(common,
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"DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
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"DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
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AH_RX_STOP_DMA_TIMEOUT / 1000,
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REG_READ(ah, AR_CR),
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REG_READ(ah, AR_DIAG_SW));
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REG_READ(ah, AR_DIAG_SW),
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REG_READ(ah, AR_DMADBG_7));
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return false;
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} else {
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return true;
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@ -695,7 +695,7 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
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void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
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void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning);
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void ath9k_hw_abortpcurecv(struct ath_hw *ah);
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bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
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bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset);
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int ath9k_hw_beaconq_setup(struct ath_hw *ah);
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/* Interrupt Handling */
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@ -486,12 +486,12 @@ int ath_startrecv(struct ath_softc *sc)
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bool ath_stoprecv(struct ath_softc *sc)
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{
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struct ath_hw *ah = sc->sc_ah;
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bool stopped;
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bool stopped, reset = false;
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spin_lock_bh(&sc->rx.rxbuflock);
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ath9k_hw_abortpcurecv(ah);
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ath9k_hw_setrxfilter(ah, 0);
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stopped = ath9k_hw_stopdmarecv(ah);
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stopped = ath9k_hw_stopdmarecv(ah, &reset);
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if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
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ath_edma_stop_recv(sc);
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@ -506,7 +506,7 @@ bool ath_stoprecv(struct ath_softc *sc)
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"confusing the DMA engine when we start RX up\n");
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ATH_DBG_WARN_ON_ONCE(!stopped);
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}
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return stopped;
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return stopped || reset;
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}
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void ath_flushrecv(struct ath_softc *sc)
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