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drm/amdgpu: limit reg_write_reg_wait workaround to SRIOV v2 

Turned out that this locks up some bare metal Vega10.

v2: fix stupid typo

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König 2018-04-17 14:47:42 +02:00 committed by Alex Deucher
parent b5b4ea4d98
commit 58cd8fbc64
1 changed files with 6 additions and 1 deletions
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7
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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@ -4144,7 +4144,12 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
{
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, ref, mask, 0x20);
if (amdgpu_sriov_vf(ring->adev))
gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
ref, mask, 0x20);
else
amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
ref, mask);
}
static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,