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Merge branch 'net-phy-dp83867-add-some-fixes' 

Max Uvarov says:

====================
net: phy: dp83867: add some fixes

v3: use phy_modify_mmd()
v2: fix minor comments by Heiner Kallweit and Florian Fainelli
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2019-05-29 14:28:48 -07:00
parent 3d3ced2ec5 2b89264925
commit 58e8b37069
1 changed files with 37 additions and 4 deletions
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41
drivers/net/phy/dp83867.c
View File

@ -26,10 +26,18 @@
/* Extended Registers */
#define DP83867_CFG4 0x0031
#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
#define DP83867_RGMIICTL 0x0032
#define DP83867_STRAP_STS1 0x006E
#define DP83867_RGMIIDCTL 0x0086
#define DP83867_IO_MUX_CFG 0x0170
#define DP83867_10M_SGMII_CFG 0x016F
#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
#define DP83867_SW_RESET BIT(15)
#define DP83867_SW_RESTART BIT(14)
@ -247,10 +255,8 @@ static int dp83867_config_init(struct phy_device *phydev)
ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
if (ret)
return ret;
}
if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
(phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
/* Set up RGMII delays */
val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
@ -277,6 +283,33 @@ static int dp83867_config_init(struct phy_device *phydev)
DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
}
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
/* For support SPEED_10 in SGMII mode
* DP83867_10M_SGMII_RATE_ADAPT bit
* has to be cleared by software. That
* does not affect SPEED_100 and
* SPEED_1000.
*/
ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
DP83867_10M_SGMII_CFG,
DP83867_10M_SGMII_RATE_ADAPT_MASK,
0);
if (ret)
return ret;
/* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
* are 01). That is not enough to finalize autoneg on some
* devices. Increase this timer duration to maximum 16ms.
*/
ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
DP83867_CFG4,
DP83867_CFG4_SGMII_ANEG_MASK,
DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
if (ret)
return ret;
}
/* Enable Interrupt output INT_OE in CFG3 register */
if (phy_interrupt_is_valid(phydev)) {
val = phy_read(phydev, DP83867_CFG3);
@ -307,7 +340,7 @@ static int dp83867_phy_reset(struct phy_device *phydev)
usleep_range(10, 20);
return dp83867_config_init(phydev);
return 0;
}
static struct phy_driver dp83867_driver[] = {