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ARM: i.MX28: shift frac value in _CLK_SET_RATE 

Noticed when setting SSP0 in clk_set_rate, _CLK_SET_RATE attempts to
reset the clock divider for the SSP0 parent clock, in this case
IO0FRAC. Bits 24-29 of HW_CLKCTRL_FRAC0 are cleared correctly, but
when the new frac value is written the value isn't shifted up to write
the correct bit-field.  This results in IO0FRAC being set to 0 and
CPUFRAC being corrupted.

This should occur when writing IO1FRAC, EMIFRAC in HW_CLKCTRL_FRAC0
and GPMIFRAC, HSADCFRAC in HW_CLKCTRL_FRAC1.

Tested on custom i.MX28 board with SSP0 SPI driver.

Signed-off-by: Matt Burtch <matt@grid-net.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Matt Burtch 2011-10-17 09:25:45 -07:00 committed by Sascha Hauer
parent 6571534b60
commit 590842f909
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mach-mxs/clock-mx28.c
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@ -349,7 +349,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \
\
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \
reg |= frac; \
reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC; \
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
} \
\