dt-bindings: clock: renesas: div6: Convert to json-schema

Convert the Renesas CPG DIV6 Clock Device Tree binding documentation to
json-schema.

Drop R-Car Gen2 compatible values, which were obsoleted by the unified
"Renesas Clock Pulse Generator / Module Standby and Software Reset" DT
bindings.
Update the example to match reality.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20200507075026.31941-1-geert+renesas@glider.be

Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml

@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas CPG DIV6 Clock
+
+maintainers:
+  - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+  The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
+  Generator (CPG). Their clock input is divided by a configurable factor from 1
+  to 64.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,r8a73a4-div6-clock # R-Mobile APE6
+          - renesas,r8a7740-div6-clock # R-Mobile A1
+          - renesas,sh73a0-div6-clock  # SH-Mobile AG5
+      - const: renesas,cpg-div6-clock
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    oneOf:
+      - maxItems: 1
+      - maxItems: 4
+      - maxItems: 8
+    description:
+      For clocks with multiple parents, invalid settings must be specified as
+      "<0>".
+
+  '#clock-cells':
+    const: 0
+
+  clock-output-names: true
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r8a73a4-clock.h>
+    sdhi2_clk: sdhi2_clk@e615007c {
+            compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+            reg = <0xe615007c 4>;
+            clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
+                     <&extal2_clk>;
+            #clock-cells = <0>;
+    };

Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt

@@ -1,40 +0,0 @@
-* Renesas CPG DIV6 Clock
-
-The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
-Generator (CPG). Their clock input is divided by a configurable factor from 1
-to 64.
-
-Required Properties:
-
-  - compatible: Must be one of the following
-    - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
-    - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
-    - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
-    - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
-    - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
-    - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks
-    - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
-    and "renesas,cpg-div6-clock" as a fallback.
-  - reg: Base address and length of the memory resource used by the DIV6 clock
-  - clocks: Reference to the parent clock(s); either one, four, or eight
-    clocks must be specified.  For clocks with multiple parents, invalid
-    settings must be specified as "<0>".
-  - #clock-cells: Must be 0
-
-
-Optional Properties:
-
-  - clock-output-names: The name of the clock as a free-form string
-
-
-Example
--------
-
-	sdhi2_clk: sdhi2_clk@e615007c {
-		compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
-		reg = <0 0xe615007c 0 4>;
-		clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
-			 <0>, <&extal2_clk>;
-		#clock-cells = <0>;
-		clock-output-names = "sdhi2ck";
-	};