Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (33 commits)
  sony-laptop: re-read the rfkill state when resuming from suspend
  sony-laptop: check for rfkill hard block at load time
  wext: add back wireless/ dir in sysfs for cfg80211 interfaces
  wext: Add bound checks for copy_from_user
  mac80211: improve/fix mlme messages
  cfg80211: always get BSS
  iwlwifi: fix 3945 ucode info retrieval after failure
  iwlwifi: fix memory leak in command queue handling
  iwlwifi: fix debugfs buffer handling
  cfg80211: don't set privacy w/o key
  cfg80211: wext: don't display BSSID unless associated
  net: Add explicit bound checks in net/socket.c
  bridge: Fix double-free in br_add_if.
  isdn: fix netjet/isdnhdlc build errors
  atm: dereference of he_dev->rbps_virt in he_init_group()
  ax25: Add missing dev_put in ax25_setsockopt
  Revert "sit: stateless autoconf for isatap"
  net: fix double skb free in dcbnl
  net: fix nlmsg len size for skb when error bit is set.
  net: fix vlan_get_size to include vlan_flags size
  ...
This commit is contained in:
Linus Torvalds 2009-09-30 08:07:12 -07:00
commit 5a4c8d75f4
38 changed files with 6306 additions and 10559 deletions

View File

@ -921,9 +921,9 @@ he_init_group(struct he_dev *he_dev, int group)
he_dev->rbrq_phys); he_dev->rbrq_phys);
i = CONFIG_RBPL_SIZE; i = CONFIG_RBPL_SIZE;
out_free_rbpl_virt: out_free_rbpl_virt:
while (--i) while (i--)
pci_pool_free(he_dev->rbps_pool, he_dev->rbpl_virt[i].virt, pci_pool_free(he_dev->rbpl_pool, he_dev->rbpl_virt[i].virt,
he_dev->rbps_base[i].phys); he_dev->rbpl_base[i].phys);
kfree(he_dev->rbpl_virt); kfree(he_dev->rbpl_virt);
out_free_rbpl_base: out_free_rbpl_base:
@ -933,11 +933,11 @@ he_init_group(struct he_dev *he_dev, int group)
out_destroy_rbpl_pool: out_destroy_rbpl_pool:
pci_pool_destroy(he_dev->rbpl_pool); pci_pool_destroy(he_dev->rbpl_pool);
i = CONFIG_RBPL_SIZE; i = CONFIG_RBPS_SIZE;
out_free_rbps_virt: out_free_rbps_virt:
while (--i) while (i--)
pci_pool_free(he_dev->rbpl_pool, he_dev->rbps_virt[i].virt, pci_pool_free(he_dev->rbps_pool, he_dev->rbps_virt[i].virt,
he_dev->rbpl_base[i].phys); he_dev->rbps_base[i].phys);
kfree(he_dev->rbps_virt); kfree(he_dev->rbps_virt);
out_free_rbps_base: out_free_rbps_base:

View File

@ -78,6 +78,7 @@ config MISDN_NETJET
depends on PCI depends on PCI
select MISDN_IPAC select MISDN_IPAC
select ISDN_HDLC select ISDN_HDLC
select ISDN_I4L
help help
Enable support for Traverse Technologies NETJet PCI cards. Enable support for Traverse Technologies NETJet PCI cards.

View File

@ -142,7 +142,6 @@ endif
config ISDN_HDLC config ISDN_HDLC
tristate tristate
depends on HISAX_ST5481
select CRC_CCITT select CRC_CCITT
select BITREVERSE select BITREVERSE

View File

@ -149,7 +149,6 @@ do { \
#define AUTO_ALL_MODES 0 #define AUTO_ALL_MODES 0
#define E1000_EEPROM_82544_APM 0x0004 #define E1000_EEPROM_82544_APM 0x0004
#define E1000_EEPROM_ICH8_APME 0x0004
#define E1000_EEPROM_APME 0x0400 #define E1000_EEPROM_APME 0x0400
#ifndef E1000_MASTER_SLAVE #ifndef E1000_MASTER_SLAVE
@ -293,7 +292,6 @@ struct e1000_adapter {
u64 hw_csum_err; u64 hw_csum_err;
u64 hw_csum_good; u64 hw_csum_good;
u64 rx_hdr_split;
u32 alloc_rx_buff_failed; u32 alloc_rx_buff_failed;
u32 rx_int_delay; u32 rx_int_delay;
u32 rx_abs_int_delay; u32 rx_abs_int_delay;
@ -317,7 +315,6 @@ struct e1000_adapter {
struct e1000_rx_ring test_rx_ring; struct e1000_rx_ring test_rx_ring;
int msg_enable; int msg_enable;
bool have_msi;
/* to not mess up cache alignment, always add to the bottom */ /* to not mess up cache alignment, always add to the bottom */
bool tso_force; bool tso_force;

View File

@ -82,7 +82,6 @@ static const struct e1000_stats e1000_gstrings_stats[] = {
{ "rx_long_byte_count", E1000_STAT(stats.gorcl) }, { "rx_long_byte_count", E1000_STAT(stats.gorcl) },
{ "rx_csum_offload_good", E1000_STAT(hw_csum_good) }, { "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
{ "rx_csum_offload_errors", E1000_STAT(hw_csum_err) }, { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) },
{ "rx_header_split", E1000_STAT(rx_hdr_split) },
{ "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) }, { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) },
{ "tx_smbus", E1000_STAT(stats.mgptc) }, { "tx_smbus", E1000_STAT(stats.mgptc) },
{ "rx_smbus", E1000_STAT(stats.mgprc) }, { "rx_smbus", E1000_STAT(stats.mgprc) },
@ -114,8 +113,6 @@ static int e1000_get_settings(struct net_device *netdev,
SUPPORTED_1000baseT_Full| SUPPORTED_1000baseT_Full|
SUPPORTED_Autoneg | SUPPORTED_Autoneg |
SUPPORTED_TP); SUPPORTED_TP);
if (hw->phy_type == e1000_phy_ife)
ecmd->supported &= ~SUPPORTED_1000baseT_Full;
ecmd->advertising = ADVERTISED_TP; ecmd->advertising = ADVERTISED_TP;
if (hw->autoneg == 1) { if (hw->autoneg == 1) {
@ -178,14 +175,6 @@ static int e1000_set_settings(struct net_device *netdev,
struct e1000_adapter *adapter = netdev_priv(netdev); struct e1000_adapter *adapter = netdev_priv(netdev);
struct e1000_hw *hw = &adapter->hw; struct e1000_hw *hw = &adapter->hw;
/* When SoL/IDER sessions are active, autoneg/speed/duplex
* cannot be changed */
if (e1000_check_phy_reset_block(hw)) {
DPRINTK(DRV, ERR, "Cannot change link characteristics "
"when SoL/IDER is active.\n");
return -EINVAL;
}
while (test_and_set_bit(__E1000_RESETTING, &adapter->flags)) while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
msleep(1); msleep(1);
@ -330,9 +319,6 @@ static int e1000_set_tso(struct net_device *netdev, u32 data)
else else
netdev->features &= ~NETIF_F_TSO; netdev->features &= ~NETIF_F_TSO;
if (data && (adapter->hw.mac_type > e1000_82547_rev_2))
netdev->features |= NETIF_F_TSO6;
else
netdev->features &= ~NETIF_F_TSO6; netdev->features &= ~NETIF_F_TSO6;
DPRINTK(PROBE, INFO, "TSO is %s\n", data ? "Enabled" : "Disabled"); DPRINTK(PROBE, INFO, "TSO is %s\n", data ? "Enabled" : "Disabled");
@ -441,7 +427,6 @@ static void e1000_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
regs_buff[24] = (u32)phy_data; /* phy local receiver status */ regs_buff[24] = (u32)phy_data; /* phy local receiver status */
regs_buff[25] = regs_buff[24]; /* phy remote receiver status */ regs_buff[25] = regs_buff[24]; /* phy remote receiver status */
if (hw->mac_type >= e1000_82540 && if (hw->mac_type >= e1000_82540 &&
hw->mac_type < e1000_82571 &&
hw->media_type == e1000_media_type_copper) { hw->media_type == e1000_media_type_copper) {
regs_buff[26] = er32(MANC); regs_buff[26] = er32(MANC);
} }
@ -554,10 +539,8 @@ static int e1000_set_eeprom(struct net_device *netdev,
ret_val = e1000_write_eeprom(hw, first_word, ret_val = e1000_write_eeprom(hw, first_word,
last_word - first_word + 1, eeprom_buff); last_word - first_word + 1, eeprom_buff);
/* Update the checksum over the first part of the EEPROM if needed /* Update the checksum over the first part of the EEPROM if needed */
* and flush shadow RAM for 82573 conrollers */ if ((ret_val == 0) && (first_word <= EEPROM_CHECKSUM_REG))
if ((ret_val == 0) && ((first_word <= EEPROM_CHECKSUM_REG) ||
(hw->mac_type == e1000_82573)))
e1000_update_eeprom_checksum(hw); e1000_update_eeprom_checksum(hw);
kfree(eeprom_buff); kfree(eeprom_buff);
@ -568,31 +551,12 @@ static void e1000_get_drvinfo(struct net_device *netdev,
struct ethtool_drvinfo *drvinfo) struct ethtool_drvinfo *drvinfo)
{ {
struct e1000_adapter *adapter = netdev_priv(netdev); struct e1000_adapter *adapter = netdev_priv(netdev);
struct e1000_hw *hw = &adapter->hw;
char firmware_version[32]; char firmware_version[32];
u16 eeprom_data;
strncpy(drvinfo->driver, e1000_driver_name, 32); strncpy(drvinfo->driver, e1000_driver_name, 32);
strncpy(drvinfo->version, e1000_driver_version, 32); strncpy(drvinfo->version, e1000_driver_version, 32);
/* EEPROM image version # is reported as firmware version # for
* 8257{1|2|3} controllers */
e1000_read_eeprom(hw, 5, 1, &eeprom_data);
switch (hw->mac_type) {
case e1000_82571:
case e1000_82572:
case e1000_82573:
case e1000_80003es2lan:
case e1000_ich8lan:
sprintf(firmware_version, "%d.%d-%d",
(eeprom_data & 0xF000) >> 12,
(eeprom_data & 0x0FF0) >> 4,
eeprom_data & 0x000F);
break;
default:
sprintf(firmware_version, "N/A"); sprintf(firmware_version, "N/A");
}
strncpy(drvinfo->fw_version, firmware_version, 32); strncpy(drvinfo->fw_version, firmware_version, 32);
strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
drvinfo->regdump_len = e1000_get_regs_len(netdev); drvinfo->regdump_len = e1000_get_regs_len(netdev);
@ -781,21 +745,9 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
/* The status register is Read Only, so a write should fail. /* The status register is Read Only, so a write should fail.
* Some bits that get toggled are ignored. * Some bits that get toggled are ignored.
*/ */
switch (hw->mac_type) {
/* there are several bits on newer hardware that are r/w */ /* there are several bits on newer hardware that are r/w */
case e1000_82571:
case e1000_82572:
case e1000_80003es2lan:
toggle = 0x7FFFF3FF;
break;
case e1000_82573:
case e1000_ich8lan:
toggle = 0x7FFFF033;
break;
default:
toggle = 0xFFFFF833; toggle = 0xFFFFF833;
break;
}
before = er32(STATUS); before = er32(STATUS);
value = (er32(STATUS) & toggle); value = (er32(STATUS) & toggle);
@ -810,12 +762,10 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
/* restore previous status */ /* restore previous status */
ew32(STATUS, before); ew32(STATUS, before);
if (hw->mac_type != e1000_ich8lan) {
REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF); REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF); REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF); REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF); REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
}
REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF); REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF); REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
@ -830,8 +780,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000); REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
before = (hw->mac_type == e1000_ich8lan ? before = 0x06DFB3FE;
0x06C3B33E : 0x06DFB3FE);
REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB); REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB);
REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000); REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
@ -839,12 +788,10 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF); REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF);
REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF); REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
if (hw->mac_type != e1000_ich8lan)
REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF); REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF); REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF); REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
value = (hw->mac_type == e1000_ich8lan ? value = E1000_RAR_ENTRIES;
E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES);
for (i = 0; i < value; i++) { for (i = 0; i < value; i++) {
REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF, REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
0xFFFFFFFF); 0xFFFFFFFF);
@ -859,8 +806,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
} }
value = (hw->mac_type == e1000_ich8lan ? value = E1000_MC_TBL_SIZE;
E1000_MC_TBL_SIZE_ICH8LAN : E1000_MC_TBL_SIZE);
for (i = 0; i < value; i++) for (i = 0; i < value; i++)
REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF); REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF);
@ -933,9 +879,6 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
/* Test each interrupt */ /* Test each interrupt */
for (; i < 10; i++) { for (; i < 10; i++) {
if (hw->mac_type == e1000_ich8lan && i == 8)
continue;
/* Interrupt to test */ /* Interrupt to test */
mask = 1 << i; mask = 1 << i;
@ -1289,24 +1232,10 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
e1000_write_phy_reg(hw, PHY_CTRL, 0x9140); e1000_write_phy_reg(hw, PHY_CTRL, 0x9140);
/* autoneg off */ /* autoneg off */
e1000_write_phy_reg(hw, PHY_CTRL, 0x8140); e1000_write_phy_reg(hw, PHY_CTRL, 0x8140);
} else if (hw->phy_type == e1000_phy_gg82563) }
e1000_write_phy_reg(hw,
GG82563_PHY_KMRN_MODE_CTRL,
0x1CC);
ctrl_reg = er32(CTRL); ctrl_reg = er32(CTRL);
if (hw->phy_type == e1000_phy_ife) {
/* force 100, set loopback */
e1000_write_phy_reg(hw, PHY_CTRL, 0x6100);
/* Now set up the MAC to the same speed/duplex as the PHY. */
ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
E1000_CTRL_SPD_100 |/* Force Speed to 100 */
E1000_CTRL_FD); /* Force Duplex to FULL */
} else {
/* force 1000, set loopback */ /* force 1000, set loopback */
e1000_write_phy_reg(hw, PHY_CTRL, 0x4140); e1000_write_phy_reg(hw, PHY_CTRL, 0x4140);
@ -1317,7 +1246,6 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
E1000_CTRL_FD); /* Force Duplex to FULL */ E1000_CTRL_FD); /* Force Duplex to FULL */
}
if (hw->media_type == e1000_media_type_copper && if (hw->media_type == e1000_media_type_copper &&
hw->phy_type == e1000_phy_m88) hw->phy_type == e1000_phy_m88)
@ -1373,14 +1301,8 @@ static int e1000_set_phy_loopback(struct e1000_adapter *adapter)
case e1000_82541_rev_2: case e1000_82541_rev_2:
case e1000_82547: case e1000_82547:
case e1000_82547_rev_2: case e1000_82547_rev_2:
case e1000_82571:
case e1000_82572:
case e1000_82573:
case e1000_80003es2lan:
case e1000_ich8lan:
return e1000_integrated_phy_loopback(adapter); return e1000_integrated_phy_loopback(adapter);
break; break;
default: default:
/* Default PHY loopback work is to read the MII /* Default PHY loopback work is to read the MII
* control register and assert bit 14 (loopback mode). * control register and assert bit 14 (loopback mode).
@ -1409,14 +1331,6 @@ static int e1000_setup_loopback_test(struct e1000_adapter *adapter)
case e1000_82546_rev_3: case e1000_82546_rev_3:
return e1000_set_phy_loopback(adapter); return e1000_set_phy_loopback(adapter);
break; break;
case e1000_82571:
case e1000_82572:
#define E1000_SERDES_LB_ON 0x410
e1000_set_phy_loopback(adapter);
ew32(SCTL, E1000_SERDES_LB_ON);
msleep(10);
return 0;
break;
default: default:
rctl = er32(RCTL); rctl = er32(RCTL);
rctl |= E1000_RCTL_LBM_TCVR; rctl |= E1000_RCTL_LBM_TCVR;
@ -1440,26 +1354,12 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
ew32(RCTL, rctl); ew32(RCTL, rctl);
switch (hw->mac_type) { switch (hw->mac_type) {
case e1000_82571:
case e1000_82572:
if (hw->media_type == e1000_media_type_fiber ||
hw->media_type == e1000_media_type_internal_serdes) {
#define E1000_SERDES_LB_OFF 0x400
ew32(SCTL, E1000_SERDES_LB_OFF);
msleep(10);
break;
}
/* Fall Through */
case e1000_82545: case e1000_82545:
case e1000_82546: case e1000_82546:
case e1000_82545_rev_3: case e1000_82545_rev_3:
case e1000_82546_rev_3: case e1000_82546_rev_3:
default: default:
hw->autoneg = true; hw->autoneg = true;
if (hw->phy_type == e1000_phy_gg82563)
e1000_write_phy_reg(hw,
GG82563_PHY_KMRN_MODE_CTRL,
0x180);
e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
if (phy_reg & MII_CR_LOOPBACK) { if (phy_reg & MII_CR_LOOPBACK) {
phy_reg &= ~MII_CR_LOOPBACK; phy_reg &= ~MII_CR_LOOPBACK;
@ -1560,17 +1460,6 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data) static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
{ {
struct e1000_hw *hw = &adapter->hw;
/* PHY loopback cannot be performed if SoL/IDER
* sessions are active */
if (e1000_check_phy_reset_block(hw)) {
DPRINTK(DRV, ERR, "Cannot do PHY loopback test "
"when SoL/IDER is active.\n");
*data = 0;
goto out;
}
*data = e1000_setup_desc_rings(adapter); *data = e1000_setup_desc_rings(adapter);
if (*data) if (*data)
goto out; goto out;
@ -1592,13 +1481,13 @@ static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
*data = 0; *data = 0;
if (hw->media_type == e1000_media_type_internal_serdes) { if (hw->media_type == e1000_media_type_internal_serdes) {
int i = 0; int i = 0;
hw->serdes_link_down = true; hw->serdes_has_link = false;
/* On some blade server designs, link establishment /* On some blade server designs, link establishment
* could take as long as 2-3 minutes */ * could take as long as 2-3 minutes */
do { do {
e1000_check_for_link(hw); e1000_check_for_link(hw);
if (!hw->serdes_link_down) if (hw->serdes_has_link)
return *data; return *data;
msleep(20); msleep(20);
} while (i++ < 3750); } while (i++ < 3750);
@ -1716,15 +1605,11 @@ static int e1000_wol_exclusion(struct e1000_adapter *adapter,
case E1000_DEV_ID_82545EM_COPPER: case E1000_DEV_ID_82545EM_COPPER:
case E1000_DEV_ID_82546GB_QUAD_COPPER: case E1000_DEV_ID_82546GB_QUAD_COPPER:
case E1000_DEV_ID_82546GB_PCIE: case E1000_DEV_ID_82546GB_PCIE:
case E1000_DEV_ID_82571EB_SERDES_QUAD:
/* these don't support WoL at all */ /* these don't support WoL at all */
wol->supported = 0; wol->supported = 0;
break; break;
case E1000_DEV_ID_82546EB_FIBER: case E1000_DEV_ID_82546EB_FIBER:
case E1000_DEV_ID_82546GB_FIBER: case E1000_DEV_ID_82546GB_FIBER:
case E1000_DEV_ID_82571EB_FIBER:
case E1000_DEV_ID_82571EB_SERDES:
case E1000_DEV_ID_82571EB_COPPER:
/* Wake events not supported on port B */ /* Wake events not supported on port B */
if (er32(STATUS) & E1000_STATUS_FUNC_1) { if (er32(STATUS) & E1000_STATUS_FUNC_1) {
wol->supported = 0; wol->supported = 0;
@ -1733,10 +1618,6 @@ static int e1000_wol_exclusion(struct e1000_adapter *adapter,
/* return success for non excluded adapter ports */ /* return success for non excluded adapter ports */
retval = 0; retval = 0;
break; break;
case E1000_DEV_ID_82571EB_QUAD_COPPER:
case E1000_DEV_ID_82571EB_QUAD_FIBER:
case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
case E1000_DEV_ID_82571PT_QUAD_COPPER:
case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
/* quad port adapters only support WoL on port A */ /* quad port adapters only support WoL on port A */
if (!adapter->quad_port_a) { if (!adapter->quad_port_a) {
@ -1872,7 +1753,6 @@ static int e1000_phys_id(struct net_device *netdev, u32 data)
if (!data) if (!data)
data = INT_MAX; data = INT_MAX;
if (hw->mac_type < e1000_82571) {
if (!adapter->blink_timer.function) { if (!adapter->blink_timer.function) {
init_timer(&adapter->blink_timer); init_timer(&adapter->blink_timer);
adapter->blink_timer.function = e1000_led_blink_callback; adapter->blink_timer.function = e1000_led_blink_callback;
@ -1882,20 +1762,6 @@ static int e1000_phys_id(struct net_device *netdev, u32 data)
mod_timer(&adapter->blink_timer, jiffies); mod_timer(&adapter->blink_timer, jiffies);
msleep_interruptible(data * 1000); msleep_interruptible(data * 1000);
del_timer_sync(&adapter->blink_timer); del_timer_sync(&adapter->blink_timer);
} else if (hw->phy_type == e1000_phy_ife) {
if (!adapter->blink_timer.function) {
init_timer(&adapter->blink_timer);
adapter->blink_timer.function = e1000_led_blink_callback;
adapter->blink_timer.data = (unsigned long)adapter;
}
mod_timer(&adapter->blink_timer, jiffies);
msleep_interruptible(data * 1000);
del_timer_sync(&adapter->blink_timer);
e1000_write_phy_reg(&(adapter->hw), IFE_PHY_SPECIAL_CONTROL_LED, 0);
} else {
e1000_blink_led_start(hw);
msleep_interruptible(data * 1000);
}
e1000_led_off(hw); e1000_led_off(hw);
clear_bit(E1000_LED_ON, &adapter->led_status); clear_bit(E1000_LED_ON, &adapter->led_status);

File diff suppressed because it is too large Load Diff

View File

@ -35,7 +35,6 @@
#include "e1000_osdep.h" #include "e1000_osdep.h"
/* Forward declarations of structures used by the shared code */ /* Forward declarations of structures used by the shared code */
struct e1000_hw; struct e1000_hw;
struct e1000_hw_stats; struct e1000_hw_stats;
@ -57,11 +56,6 @@ typedef enum {
e1000_82541_rev_2, e1000_82541_rev_2,
e1000_82547, e1000_82547,
e1000_82547_rev_2, e1000_82547_rev_2,
e1000_82571,
e1000_82572,
e1000_82573,
e1000_80003es2lan,
e1000_ich8lan,
e1000_num_macs e1000_num_macs
} e1000_mac_type; } e1000_mac_type;
@ -70,7 +64,6 @@ typedef enum {
e1000_eeprom_spi, e1000_eeprom_spi,
e1000_eeprom_microwire, e1000_eeprom_microwire,
e1000_eeprom_flash, e1000_eeprom_flash,
e1000_eeprom_ich8,
e1000_eeprom_none, /* No NVM support */ e1000_eeprom_none, /* No NVM support */
e1000_num_eeprom_types e1000_num_eeprom_types
} e1000_eeprom_type; } e1000_eeprom_type;
@ -109,7 +102,6 @@ typedef enum {
e1000_bus_type_unknown = 0, e1000_bus_type_unknown = 0,
e1000_bus_type_pci, e1000_bus_type_pci,
e1000_bus_type_pcix, e1000_bus_type_pcix,
e1000_bus_type_pci_express,
e1000_bus_type_reserved e1000_bus_type_reserved
} e1000_bus_type; } e1000_bus_type;
@ -121,18 +113,12 @@ typedef enum {
e1000_bus_speed_100, e1000_bus_speed_100,
e1000_bus_speed_120, e1000_bus_speed_120,
e1000_bus_speed_133, e1000_bus_speed_133,
e1000_bus_speed_2500,
e1000_bus_speed_reserved e1000_bus_speed_reserved
} e1000_bus_speed; } e1000_bus_speed;
/* PCI bus widths */ /* PCI bus widths */
typedef enum { typedef enum {
e1000_bus_width_unknown = 0, e1000_bus_width_unknown = 0,
/* These PCIe values should literally match the possible return values
* from config space */
e1000_bus_width_pciex_1 = 1,
e1000_bus_width_pciex_2 = 2,
e1000_bus_width_pciex_4 = 4,
e1000_bus_width_32, e1000_bus_width_32,
e1000_bus_width_64, e1000_bus_width_64,
e1000_bus_width_reserved e1000_bus_width_reserved
@ -224,10 +210,6 @@ typedef enum {
typedef enum { typedef enum {
e1000_phy_m88 = 0, e1000_phy_m88 = 0,
e1000_phy_igp, e1000_phy_igp,
e1000_phy_igp_2,
e1000_phy_gg82563,
e1000_phy_igp_3,
e1000_phy_ife,
e1000_phy_undefined = 0xFF e1000_phy_undefined = 0xFF
} e1000_phy_type; } e1000_phy_type;
@ -274,8 +256,6 @@ struct e1000_eeprom_info {
u16 address_bits; u16 address_bits;
u16 delay_usec; u16 delay_usec;
u16 page_size; u16 page_size;
bool use_eerd;
bool use_eewr;
}; };
/* Flex ASF Information */ /* Flex ASF Information */
@ -287,8 +267,6 @@ typedef enum {
e1000_dword_align = 2 e1000_dword_align = 2
} e1000_align_type; } e1000_align_type;
/* Error Codes */ /* Error Codes */
#define E1000_SUCCESS 0 #define E1000_SUCCESS 0
#define E1000_ERR_EEPROM 1 #define E1000_ERR_EEPROM 1
@ -301,7 +279,6 @@ typedef enum {
#define E1000_ERR_MASTER_REQUESTS_PENDING 10 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
#define E1000_ERR_HOST_INTERFACE_COMMAND 11 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
#define E1000_BLK_PHY_RESET 12 #define E1000_BLK_PHY_RESET 12
#define E1000_ERR_SWFW_SYNC 13
#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \ #define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \
(((_value) & 0xff00) >> 8)) (((_value) & 0xff00) >> 8))
@ -318,19 +295,17 @@ s32 e1000_setup_link(struct e1000_hw *hw);
s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
void e1000_config_collision_dist(struct e1000_hw *hw); void e1000_config_collision_dist(struct e1000_hw *hw);
s32 e1000_check_for_link(struct e1000_hw *hw); s32 e1000_check_for_link(struct e1000_hw *hw);
s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex); s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex);
s32 e1000_force_mac_fc(struct e1000_hw *hw); s32 e1000_force_mac_fc(struct e1000_hw *hw);
/* PHY */ /* PHY */
s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data); s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data);
s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data); s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
s32 e1000_phy_hw_reset(struct e1000_hw *hw); s32 e1000_phy_hw_reset(struct e1000_hw *hw);
s32 e1000_phy_reset(struct e1000_hw *hw); s32 e1000_phy_reset(struct e1000_hw *hw);
s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
s32 e1000_validate_mdi_setting(struct e1000_hw *hw); s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
/* EEPROM Functions */ /* EEPROM Functions */
s32 e1000_init_eeprom_params(struct e1000_hw *hw); s32 e1000_init_eeprom_params(struct e1000_hw *hw);
@ -363,10 +338,10 @@ struct e1000_host_mng_command_header {
struct e1000_host_mng_command_info { struct e1000_host_mng_command_info {
struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658 */
}; };
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
struct e1000_host_mng_dhcp_cookie{ struct e1000_host_mng_dhcp_cookie {
u32 signature; u32 signature;
u16 vlan_id; u16 vlan_id;
u8 reserved0; u8 reserved0;
@ -377,7 +352,7 @@ struct e1000_host_mng_dhcp_cookie{
u16 reserved2; u16 reserved2;
}; };
#else #else
struct e1000_host_mng_dhcp_cookie{ struct e1000_host_mng_dhcp_cookie {
u32 signature; u32 signature;
u8 status; u8 status;
u8 reserved0; u8 reserved0;
@ -389,15 +364,12 @@ struct e1000_host_mng_dhcp_cookie{
}; };
#endif #endif
s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer,
u16 length);
bool e1000_check_mng_mode(struct e1000_hw *hw); bool e1000_check_mng_mode(struct e1000_hw *hw);
bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data);
s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw); s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
s32 e1000_update_eeprom_checksum(struct e1000_hw *hw); s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data); s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
s32 e1000_read_mac_addr(struct e1000_hw * hw); s32 e1000_read_mac_addr(struct e1000_hw *hw);
/* Filters (multicast, vlan, receive) */ /* Filters (multicast, vlan, receive) */
u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr); u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
@ -417,18 +389,15 @@ s32 e1000_blink_led_start(struct e1000_hw *hw);
/* Everything else */ /* Everything else */
void e1000_reset_adaptive(struct e1000_hw *hw); void e1000_reset_adaptive(struct e1000_hw *hw);
void e1000_update_adaptive(struct e1000_hw *hw); void e1000_update_adaptive(struct e1000_hw *hw);
void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, u32 frame_len, u8 * mac_addr); void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
u32 frame_len, u8 * mac_addr);
void e1000_get_bus_info(struct e1000_hw *hw); void e1000_get_bus_info(struct e1000_hw *hw);
void e1000_pci_set_mwi(struct e1000_hw *hw); void e1000_pci_set_mwi(struct e1000_hw *hw);
void e1000_pci_clear_mwi(struct e1000_hw *hw); void e1000_pci_clear_mwi(struct e1000_hw *hw);
s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc); void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc);
int e1000_pcix_get_mmrbc(struct e1000_hw *hw); int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
/* Port I/O is only supported on 82544 and newer */ /* Port I/O is only supported on 82544 and newer */
void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value); void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
s32 e1000_disable_pciex_master(struct e1000_hw *hw);
s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
#define E1000_READ_REG_IO(a, reg) \ #define E1000_READ_REG_IO(a, reg) \
e1000_read_reg_io((a), E1000_##reg) e1000_read_reg_io((a), E1000_##reg)
@ -471,36 +440,7 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
#define E1000_DEV_ID_82547EI 0x1019 #define E1000_DEV_ID_82547EI 0x1019
#define E1000_DEV_ID_82547EI_MOBILE 0x101A #define E1000_DEV_ID_82547EI_MOBILE 0x101A
#define E1000_DEV_ID_82571EB_COPPER 0x105E
#define E1000_DEV_ID_82571EB_FIBER 0x105F
#define E1000_DEV_ID_82571EB_SERDES 0x1060
#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
#define E1000_DEV_ID_82572EI_COPPER 0x107D
#define E1000_DEV_ID_82572EI_FIBER 0x107E
#define E1000_DEV_ID_82572EI_SERDES 0x107F
#define E1000_DEV_ID_82572EI 0x10B9
#define E1000_DEV_ID_82573E 0x108B
#define E1000_DEV_ID_82573E_IAMT 0x108C
#define E1000_DEV_ID_82573L 0x109A
#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
#define E1000_DEV_ID_ICH8_IGP_C 0x104B
#define E1000_DEV_ID_ICH8_IFE 0x104C
#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
#define E1000_DEV_ID_ICH8_IGP_M 0x104D
#define NODE_ADDRESS_SIZE 6 #define NODE_ADDRESS_SIZE 6
#define ETH_LENGTH_OF_ADDRESS 6 #define ETH_LENGTH_OF_ADDRESS 6
@ -530,7 +470,6 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
#define CRC_LENGTH ETHERNET_FCS_SIZE #define CRC_LENGTH ETHERNET_FCS_SIZE
#define MAX_JUMBO_FRAME_SIZE 0x3F00 #define MAX_JUMBO_FRAME_SIZE 0x3F00
/* 802.1q VLAN Packet Sizes */ /* 802.1q VLAN Packet Sizes */
#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
@ -567,15 +506,6 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
E1000_IMS_RXSEQ | \ E1000_IMS_RXSEQ | \
E1000_IMS_LSC) E1000_IMS_LSC)
/* Additional interrupts need to be handled for e1000_ich8lan:
DSW = The FW changed the status of the DISSW bit in FWSM
PHYINT = The LAN connected device generates an interrupt
EPRST = Manageability reset event */
#define IMS_ICH8LAN_ENABLE_MASK (\
E1000_IMS_DSW | \
E1000_IMS_PHYINT | \
E1000_IMS_EPRST)
/* Number of high/low register pairs in the RAR. The RAR (Receive Address /* Number of high/low register pairs in the RAR. The RAR (Receive Address
* Registers) holds the directed and multicast addresses that we monitor. We * Registers) holds the directed and multicast addresses that we monitor. We
* reserve one of these spots for our directed address, allowing us room for * reserve one of these spots for our directed address, allowing us room for
@ -583,8 +513,6 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
*/ */
#define E1000_RAR_ENTRIES 15 #define E1000_RAR_ENTRIES 15
#define E1000_RAR_ENTRIES_ICH8LAN 6
#define MIN_NUMBER_OF_DESCRIPTORS 8 #define MIN_NUMBER_OF_DESCRIPTORS 8
#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
@ -654,12 +582,12 @@ union e1000_rx_desc_packet_split {
} wb; /* writeback */ } wb; /* writeback */
}; };
/* Receive Decriptor bit definitions */ /* Receive Descriptor bit definitions */
#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
@ -698,7 +626,6 @@ union e1000_rx_desc_packet_split {
E1000_RXD_ERR_CXE | \ E1000_RXD_ERR_CXE | \
E1000_RXD_ERR_RXE) E1000_RXD_ERR_RXE)
/* Same mask, but for extended and packet split descriptors */ /* Same mask, but for extended and packet split descriptors */
#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
E1000_RXDEXT_STATERR_CE | \ E1000_RXDEXT_STATERR_CE | \
@ -707,7 +634,6 @@ union e1000_rx_desc_packet_split {
E1000_RXDEXT_STATERR_CXE | \ E1000_RXDEXT_STATERR_CXE | \
E1000_RXDEXT_STATERR_RXE) E1000_RXDEXT_STATERR_RXE)
/* Transmit Descriptor */ /* Transmit Descriptor */
struct e1000_tx_desc { struct e1000_tx_desc {
__le64 buffer_addr; /* Address of the descriptor's data buffer */ __le64 buffer_addr; /* Address of the descriptor's data buffer */
@ -806,10 +732,6 @@ struct e1000_data_desc {
#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
#define E1000_NUM_UNICAST_ICH8LAN 7
#define E1000_MC_TBL_SIZE_ICH8LAN 32
/* Receive Address Register */ /* Receive Address Register */
struct e1000_rar { struct e1000_rar {
volatile __le32 low; /* receive address low */ volatile __le32 low; /* receive address low */
@ -818,7 +740,6 @@ struct e1000_rar {
/* Number of entries in the Multicast Table Array (MTA). */ /* Number of entries in the Multicast Table Array (MTA). */
#define E1000_NUM_MTA_REGISTERS 128 #define E1000_NUM_MTA_REGISTERS 128
#define E1000_NUM_MTA_REGISTERS_ICH8LAN 32
/* IPv4 Address Table Entry */ /* IPv4 Address Table Entry */
struct e1000_ipv4_at_entry { struct e1000_ipv4_at_entry {
@ -829,7 +750,6 @@ struct e1000_ipv4_at_entry {
/* Four wakeup IP addresses are supported */ /* Four wakeup IP addresses are supported */
#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
#define E1000_IP4AT_SIZE_ICH8LAN 3
#define E1000_IP6AT_SIZE 1 #define E1000_IP6AT_SIZE 1
/* IPv6 Address Table Entry */ /* IPv6 Address Table Entry */
@ -1043,7 +963,7 @@ struct e1000_ffvt_entry {
#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ #define E1000_RFCTL 0x05008 /* Receive Filter Control */
#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
#define E1000_RA 0x05400 /* Receive Address - RW Array */ #define E1000_RA 0x05400 /* Receive Address - RW Array */
#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
@ -1075,7 +995,7 @@ struct e1000_ffvt_entry {
#define E1000_SWSM 0x05B50 /* SW Semaphore */ #define E1000_SWSM 0x05B50 /* SW Semaphore */
#define E1000_FWSM 0x05B54 /* FW Semaphore */ #define E1000_FWSM 0x05B54 /* FW Semaphore */
#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ #define E1000_FFLT_DBG 0x05F04 /* Debug Register */
#define E1000_HICR 0x08F00 /* Host Inteface Control */ #define E1000_HICR 0x08F00 /* Host Interface Control */
/* RSS registers */ /* RSS registers */
#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
@ -1302,7 +1222,6 @@ struct e1000_ffvt_entry {
#define E1000_82542_RSSIR E1000_RSSIR #define E1000_82542_RSSIR E1000_RSSIR
#define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA #define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
#define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC #define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC
#define E1000_82542_MANC2H E1000_MANC2H
/* Statistics counters collected by the MAC */ /* Statistics counters collected by the MAC */
struct e1000_hw_stats { struct e1000_hw_stats {
@ -1399,8 +1318,6 @@ struct e1000_hw {
e1000_ffe_config ffe_config_state; e1000_ffe_config ffe_config_state;
u32 asf_firmware_present; u32 asf_firmware_present;
u32 eeprom_semaphore_present; u32 eeprom_semaphore_present;
u32 swfw_sync_present;
u32 swfwhw_semaphore_present;
unsigned long io_base; unsigned long io_base;
u32 phy_id; u32 phy_id;
u32 phy_revision; u32 phy_revision;
@ -1447,7 +1364,7 @@ struct e1000_hw {
e1000_smart_speed smart_speed; e1000_smart_speed smart_speed;
e1000_dsp_config dsp_config_state; e1000_dsp_config dsp_config_state;
bool get_link_status; bool get_link_status;
bool serdes_link_down; bool serdes_has_link;
bool tbi_compatibility_en; bool tbi_compatibility_en;
bool tbi_compatibility_on; bool tbi_compatibility_on;
bool laa_is_present; bool laa_is_present;
@ -1461,14 +1378,10 @@ struct e1000_hw {
bool in_ifs_mode; bool in_ifs_mode;
bool mng_reg_access_disabled; bool mng_reg_access_disabled;
bool leave_av_bit_off; bool leave_av_bit_off;
bool kmrn_lock_loss_workaround_disabled;
bool bad_tx_carr_stats_fd; bool bad_tx_carr_stats_fd;
bool has_manc2h;
bool rx_needs_kicking;
bool has_smbus; bool has_smbus;
}; };
#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
@ -1550,7 +1463,7 @@ struct e1000_hw {
#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
/* Constants used to intrepret the masked PCI-X bus speed. */ /* Constants used to interpret the masked PCI-X bus speed. */
#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
@ -1773,7 +1686,7 @@ struct e1000_hw {
#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ #define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ #define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
/* Interrupt Cause Set */ /* Interrupt Cause Set */
#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@ -2018,8 +1931,6 @@ struct e1000_hw {
#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
/* Receive Checksum Control */ /* Receive Checksum Control */
#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
@ -2148,7 +2059,7 @@ typedef enum {
e1000_mng_mode_host_interface_only e1000_mng_mode_host_interface_only
} e1000_mng_mode; } e1000_mng_mode;
/* Host Inteface Control Register */ /* Host Interface Control Register */
#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done #define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
* to put command in RAM */ * to put command in RAM */
@ -2246,7 +2157,7 @@ struct e1000_host_command_info {
#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erase/write disable */
/* EEPROM Commands - SPI */ /* EEPROM Commands - SPI */
#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
@ -2289,16 +2200,10 @@ struct e1000_host_command_info {
/* Word definitions for ID LED Settings */ /* Word definitions for ID LED Settings */
#define ID_LED_RESERVED_0000 0x0000 #define ID_LED_RESERVED_0000 0x0000
#define ID_LED_RESERVED_FFFF 0xFFFF #define ID_LED_RESERVED_FFFF 0xFFFF
#define ID_LED_RESERVED_82573 0xF746
#define ID_LED_DEFAULT_82573 0x1811
#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
(ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_OFF1_OFF2 << 8) | \
(ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2 << 4) | \
(ID_LED_DEF1_DEF2)) (ID_LED_DEF1_DEF2))
#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
(ID_LED_DEF1_OFF2 << 8) | \
(ID_LED_DEF1_ON2 << 4) | \
(ID_LED_DEF1_DEF2))
#define ID_LED_DEF1_DEF2 0x1 #define ID_LED_DEF1_DEF2 0x1
#define ID_LED_DEF1_ON2 0x2 #define ID_LED_DEF1_ON2 0x2
#define ID_LED_DEF1_OFF2 0x3 #define ID_LED_DEF1_OFF2 0x3
@ -2313,7 +2218,6 @@ struct e1000_host_command_info {
#define IGP_ACTIVITY_LED_ENABLE 0x0300 #define IGP_ACTIVITY_LED_ENABLE 0x0300
#define IGP_LED3_MODE 0x07000000 #define IGP_LED3_MODE 0x07000000
/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
@ -2384,11 +2288,8 @@ struct e1000_host_command_info {
#define DEFAULT_82542_TIPG_IPGR2 10 #define DEFAULT_82542_TIPG_IPGR2 10
#define DEFAULT_82543_TIPG_IPGR2 6 #define DEFAULT_82543_TIPG_IPGR2 6
#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
#define E1000_TIPG_IPGR2_SHIFT 20 #define E1000_TIPG_IPGR2_SHIFT 20
#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
#define E1000_TXDMAC_DPP 0x00000001 #define E1000_TXDMAC_DPP 0x00000001
/* Adaptive IFS defines */ /* Adaptive IFS defines */
@ -2458,7 +2359,6 @@ struct e1000_host_command_info {
#define PCIX_STATUS_HI_MMRBC_4K 0x3 #define PCIX_STATUS_HI_MMRBC_4K 0x3
#define PCIX_STATUS_HI_MMRBC_2K 0x2 #define PCIX_STATUS_HI_MMRBC_2K 0x2
/* Number of bits required to shift right the "pause" bits from the /* Number of bits required to shift right the "pause" bits from the
* EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
*/ */
@ -2479,14 +2379,11 @@ struct e1000_host_command_info {
*/ */
#define ILOS_SHIFT 3 #define ILOS_SHIFT 3
#define RECEIVE_BUFFER_ALIGN_SIZE (256) #define RECEIVE_BUFFER_ALIGN_SIZE (256)
/* Number of milliseconds we wait for auto-negotiation to complete */ /* Number of milliseconds we wait for auto-negotiation to complete */
#define LINK_UP_TIMEOUT 500 #define LINK_UP_TIMEOUT 500
/* Number of 100 microseconds we wait for PCI Express master disable */
#define MASTER_DISABLE_TIMEOUT 800
/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
#define AUTO_READ_DONE_TIMEOUT 10 #define AUTO_READ_DONE_TIMEOUT 10
/* Number of milliseconds we wait for PHY configuration done after MAC reset */ /* Number of milliseconds we wait for PHY configuration done after MAC reset */
@ -2534,7 +2431,6 @@ struct e1000_host_command_info {
(((length) > (adapter)->min_frame_size) && \ (((length) > (adapter)->min_frame_size) && \
((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
/* Structures, enums, and macros for the PHY */ /* Structures, enums, and macros for the PHY */
/* Bit definitions for the Management Data IO (MDIO) and Management Data /* Bit definitions for the Management Data IO (MDIO) and Management Data
@ -2552,7 +2448,7 @@ struct e1000_host_command_info {
/* PHY 1000 MII Register/Bit Definitions */ /* PHY 1000 MII Register/Bit Definitions */
/* PHY Registers defined by IEEE */ /* PHY Registers defined by IEEE */
#define PHY_CTRL 0x00 /* Control Register */ #define PHY_CTRL 0x00 /* Control Register */
#define PHY_STATUS 0x01 /* Status Regiser */ #define PHY_STATUS 0x01 /* Status Register */
#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
@ -2636,79 +2532,6 @@ struct e1000_host_command_info {
#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
/* Bits...
* 15-5: page
* 4-0: register offset
*/
#define GG82563_PAGE_SHIFT 5
#define GG82563_REG(page, reg) \
(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
#define GG82563_MIN_ALT_REG 30
/* GG82563 Specific Registers */
#define GG82563_PHY_SPEC_CTRL \
GG82563_REG(0, 16) /* PHY Specific Control */
#define GG82563_PHY_SPEC_STATUS \
GG82563_REG(0, 17) /* PHY Specific Status */
#define GG82563_PHY_INT_ENABLE \
GG82563_REG(0, 18) /* Interrupt Enable */
#define GG82563_PHY_SPEC_STATUS_2 \
GG82563_REG(0, 19) /* PHY Specific Status 2 */
#define GG82563_PHY_RX_ERR_CNTR \
GG82563_REG(0, 21) /* Receive Error Counter */
#define GG82563_PHY_PAGE_SELECT \
GG82563_REG(0, 22) /* Page Select */
#define GG82563_PHY_SPEC_CTRL_2 \
GG82563_REG(0, 26) /* PHY Specific Control 2 */
#define GG82563_PHY_PAGE_SELECT_ALT \
GG82563_REG(0, 29) /* Alternate Page Select */
#define GG82563_PHY_TEST_CLK_CTRL \
GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
#define GG82563_PHY_MAC_SPEC_CTRL \
GG82563_REG(2, 21) /* MAC Specific Control Register */
#define GG82563_PHY_MAC_SPEC_CTRL_2 \
GG82563_REG(2, 26) /* MAC Specific Control 2 */
#define GG82563_PHY_DSP_DISTANCE \
GG82563_REG(5, 26) /* DSP Distance */
/* Page 193 - Port Control Registers */
#define GG82563_PHY_KMRN_MODE_CTRL \
GG82563_REG(193, 16) /* Kumeran Mode Control */
#define GG82563_PHY_PORT_RESET \
GG82563_REG(193, 17) /* Port Reset */
#define GG82563_PHY_REVISION_ID \
GG82563_REG(193, 18) /* Revision ID */
#define GG82563_PHY_DEVICE_ID \
GG82563_REG(193, 19) /* Device ID */
#define GG82563_PHY_PWR_MGMT_CTRL \
GG82563_REG(193, 20) /* Power Management Control */
#define GG82563_PHY_RATE_ADAPT_CTRL \
GG82563_REG(193, 25) /* Rate Adaptation Control */
/* Page 194 - KMRN Registers */
#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
GG82563_REG(194, 16) /* FIFO's Control/Status */
#define GG82563_PHY_KMRN_CTRL \
GG82563_REG(194, 17) /* Control */
#define GG82563_PHY_INBAND_CTRL \
GG82563_REG(194, 18) /* Inband Control */
#define GG82563_PHY_KMRN_DIAGNOSTIC \
GG82563_REG(194, 19) /* Diagnostic */
#define GG82563_PHY_ACK_TIMEOUTS \
GG82563_REG(194, 20) /* Acknowledge Timeouts */
#define GG82563_PHY_ADV_ABILITY \
GG82563_REG(194, 21) /* Advertised Ability */
#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
GG82563_REG(194, 23) /* Link Partner Advertised Ability */
#define GG82563_PHY_ADV_NEXT_PAGE \
GG82563_REG(194, 24) /* Advertised Next Page */
#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
GG82563_REG(194, 25) /* Link Partner Advertised Next page */
#define GG82563_PHY_KMRN_MISC \
GG82563_REG(194, 26) /* Misc. */
/* PHY Control Register */ /* PHY Control Register */
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
@ -3032,114 +2855,6 @@ struct e1000_host_command_info {
#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
#define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */
#define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */
#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */
#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */
#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */
#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */
#define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
#define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
#define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */
#define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
#define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
#define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
/* PHY Specific Status Register (Page 0, Register 17) */
#define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
#define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
#define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
#define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
#define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
#define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
#define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
#define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
#define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
#define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
#define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
#define GG82563_PSSR_SPEED_MASK 0xC000
#define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
#define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
#define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
/* PHY Specific Status Register 2 (Page 0, Register 19) */
#define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
#define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */
#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
#define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
#define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
#define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
#define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
/* PHY Specific Control Register 2 (Page 0, Register 26) */
#define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */
#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */
#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */
#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */
#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */
#define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */
#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
/* MAC Specific Control Register (Page 2, Register 21) */
/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
#define GG82563_MSCR_TX_CLK_MASK 0x0007
#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
/* DSP Distance Register (Page 5, Register 26) */
#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
1 = 50-80M;
2 = 80-110M;
3 = 110-140M;
4 = >140M */
/* Kumeran Mode Control Register (Page 193, Register 16) */
#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */
#define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */
#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
/* Power Management Control Register (Page 193, Register 20) */
#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES Electrical Idle */
#define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
#define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
#define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */
#define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */
#define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */
#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */
#define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
/* In-Band Control Register (Page 194, Register 18) */
#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
/* Bit definitions for valid PHY IDs. */ /* Bit definitions for valid PHY IDs. */
/* I = Integrated /* I = Integrated
* E = External * E = External
@ -3154,8 +2869,6 @@ struct e1000_host_command_info {
#define M88E1011_I_REV_4 0x04 #define M88E1011_I_REV_4 0x04
#define M88E1111_I_PHY_ID 0x01410CC0 #define M88E1111_I_PHY_ID 0x01410CC0
#define L1LXT971A_PHY_ID 0x001378E0 #define L1LXT971A_PHY_ID 0x001378E0
#define GG82563_E_PHY_ID 0x01410CA0
/* Bits... /* Bits...
* 15-5: page * 15-5: page
@ -3224,7 +2937,7 @@ struct e1000_host_command_info {
#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */ #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */ #define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */ #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnect Counter */
#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */ #define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */ #define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */ #define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
@ -3235,7 +2948,7 @@ struct e1000_host_command_info {
#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */ #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */ #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Default 1 = Disable auto reduced power down */
#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */ #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */ #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */ #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
@ -3244,7 +2957,7 @@ struct e1000_host_command_info {
#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */ #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
#define IFE_PESC_POLARITY_REVERSED_SHIFT 8 #define IFE_PESC_POLARITY_REVERSED_SHIFT 8
#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */ #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dynamic Power Down disabled */
#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */ #define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */ #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */ #define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
@ -3305,74 +3018,6 @@ struct e1000_host_command_info {
#define ICH_GFPREG_BASE_MASK 0x1FFF #define ICH_GFPREG_BASE_MASK 0x1FFF
#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
/* Offset 04h HSFSTS */
union ich8_hws_flash_status {
struct ich8_hsfsts {
#ifdef __BIG_ENDIAN
u16 reserved2 :6;
u16 fldesvalid :1;
u16 flockdn :1;
u16 flcdone :1;
u16 flcerr :1;
u16 dael :1;
u16 berasesz :2;
u16 flcinprog :1;
u16 reserved1 :2;
#else
u16 flcdone :1; /* bit 0 Flash Cycle Done */
u16 flcerr :1; /* bit 1 Flash Cycle Error */
u16 dael :1; /* bit 2 Direct Access error Log */
u16 berasesz :2; /* bit 4:3 Block/Sector Erase Size */
u16 flcinprog :1; /* bit 5 flash SPI cycle in Progress */
u16 reserved1 :2; /* bit 13:6 Reserved */
u16 reserved2 :6; /* bit 13:6 Reserved */
u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
u16 flockdn :1; /* bit 15 Flash Configuration Lock-Down */
#endif
} hsf_status;
u16 regval;
};
/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
/* Offset 06h FLCTL */
union ich8_hws_flash_ctrl {
struct ich8_hsflctl {
#ifdef __BIG_ENDIAN
u16 fldbcount :2;
u16 flockdn :6;
u16 flcgo :1;
u16 flcycle :2;
u16 reserved :5;
#else
u16 flcgo :1; /* 0 Flash Cycle Go */
u16 flcycle :2; /* 2:1 Flash Cycle */
u16 reserved :5; /* 7:3 Reserved */
u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
u16 flockdn :6; /* 15:10 Reserved */
#endif
} hsf_ctrl;
u16 regval;
};
/* ICH8 Flash Region Access Permissions */
union ich8_hws_flash_regacc {
struct ich8_flracc {
#ifdef __BIG_ENDIAN
u32 gmwag :8;
u32 gmrag :8;
u32 grwa :8;
u32 grra :8;
#else
u32 grra :8; /* 0:7 GbE region Read Access */
u32 grwa :8; /* 8:15 GbE region Write Access */
u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
#endif
} hsf_flregacc;
u16 regval;
};
/* Miscellaneous PHY bit definitions. */ /* Miscellaneous PHY bit definitions. */
#define PHY_PREAMBLE 0xFFFFFFFF #define PHY_PREAMBLE 0xFFFFFFFF
#define PHY_SOF 0x01 #define PHY_SOF 0x01
@ -3397,7 +3042,7 @@ union ich8_hws_flash_regacc {
#define ADVERTISE_1000_HALF 0x0010 #define ADVERTISE_1000_HALF 0x0010
#define ADVERTISE_1000_FULL 0x0020 #define ADVERTISE_1000_FULL 0x0020
#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
#endif /* _E1000_HW_H_ */ #endif /* _E1000_HW_H_ */

File diff suppressed because it is too large Load Diff

View File

@ -518,22 +518,6 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter)
adapter->smart_power_down = opt.def; adapter->smart_power_down = opt.def;
} }
} }
{ /* Kumeran Lock Loss Workaround */
opt = (struct e1000_option) {
.type = enable_option,
.name = "Kumeran Lock Loss Workaround",
.err = "defaulting to Enabled",
.def = OPTION_ENABLED
};
if (num_KumeranLockLoss > bd) {
unsigned int kmrn_lock_loss = KumeranLockLoss[bd];
e1000_validate_option(&kmrn_lock_loss, &opt, adapter);
adapter->hw.kmrn_lock_loss_workaround_disabled = !kmrn_lock_loss;
} else {
adapter->hw.kmrn_lock_loss_workaround_disabled = !opt.def;
}
}
switch (adapter->hw.media_type) { switch (adapter->hw.media_type) {
case e1000_media_type_fiber: case e1000_media_type_fiber:
@ -626,12 +610,6 @@ static void __devinit e1000_check_copper_options(struct e1000_adapter *adapter)
.p = dplx_list }} .p = dplx_list }}
}; };
if (e1000_check_phy_reset_block(&adapter->hw)) {
DPRINTK(PROBE, INFO,
"Link active due to SoL/IDER Session. "
"Speed/Duplex/AutoNeg parameter ignored.\n");
return;
}
if (num_Duplex > bd) { if (num_Duplex > bd) {
dplx = Duplex[bd]; dplx = Duplex[bd];
e1000_validate_option(&dplx, &opt, adapter); e1000_validate_option(&dplx, &opt, adapter);

View File

@ -99,6 +99,8 @@ static struct iwl_lib_ops iwl1000_lib = {
.setup_deferred_work = iwl5000_setup_deferred_work, .setup_deferred_work = iwl5000_setup_deferred_work,
.is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
.load_ucode = iwl5000_load_ucode, .load_ucode = iwl5000_load_ucode,
.dump_nic_event_log = iwl_dump_nic_event_log,
.dump_nic_error_log = iwl_dump_nic_error_log,
.init_alive_start = iwl5000_init_alive_start, .init_alive_start = iwl5000_init_alive_start,
.alive_notify = iwl5000_alive_notify, .alive_notify = iwl5000_alive_notify,
.send_tx_power = iwl5000_send_tx_power, .send_tx_power = iwl5000_send_tx_power,

View File

@ -2839,6 +2839,8 @@ static struct iwl_lib_ops iwl3945_lib = {
.txq_free_tfd = iwl3945_hw_txq_free_tfd, .txq_free_tfd = iwl3945_hw_txq_free_tfd,
.txq_init = iwl3945_hw_tx_queue_init, .txq_init = iwl3945_hw_tx_queue_init,
.load_ucode = iwl3945_load_bsm, .load_ucode = iwl3945_load_bsm,
.dump_nic_event_log = iwl3945_dump_nic_event_log,
.dump_nic_error_log = iwl3945_dump_nic_error_log,
.apm_ops = { .apm_ops = {
.init = iwl3945_apm_init, .init = iwl3945_apm_init,
.reset = iwl3945_apm_reset, .reset = iwl3945_apm_reset,

View File

@ -209,6 +209,8 @@ extern int __must_check iwl3945_send_cmd(struct iwl_priv *priv,
struct iwl_host_cmd *cmd); struct iwl_host_cmd *cmd);
extern unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv, extern unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
struct ieee80211_hdr *hdr,int left); struct ieee80211_hdr *hdr,int left);
extern void iwl3945_dump_nic_event_log(struct iwl_priv *priv);
extern void iwl3945_dump_nic_error_log(struct iwl_priv *priv);
/* /*
* Currently used by iwl-3945-rs... look at restructuring so that it doesn't * Currently used by iwl-3945-rs... look at restructuring so that it doesn't

View File

@ -2298,6 +2298,8 @@ static struct iwl_lib_ops iwl4965_lib = {
.alive_notify = iwl4965_alive_notify, .alive_notify = iwl4965_alive_notify,
.init_alive_start = iwl4965_init_alive_start, .init_alive_start = iwl4965_init_alive_start,
.load_ucode = iwl4965_load_bsm, .load_ucode = iwl4965_load_bsm,
.dump_nic_event_log = iwl_dump_nic_event_log,
.dump_nic_error_log = iwl_dump_nic_error_log,
.apm_ops = { .apm_ops = {
.init = iwl4965_apm_init, .init = iwl4965_apm_init,
.reset = iwl4965_apm_reset, .reset = iwl4965_apm_reset,

View File

@ -1535,6 +1535,8 @@ struct iwl_lib_ops iwl5000_lib = {
.rx_handler_setup = iwl5000_rx_handler_setup, .rx_handler_setup = iwl5000_rx_handler_setup,
.setup_deferred_work = iwl5000_setup_deferred_work, .setup_deferred_work = iwl5000_setup_deferred_work,
.is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
.dump_nic_event_log = iwl_dump_nic_event_log,
.dump_nic_error_log = iwl_dump_nic_error_log,
.load_ucode = iwl5000_load_ucode, .load_ucode = iwl5000_load_ucode,
.init_alive_start = iwl5000_init_alive_start, .init_alive_start = iwl5000_init_alive_start,
.alive_notify = iwl5000_alive_notify, .alive_notify = iwl5000_alive_notify,
@ -1585,6 +1587,8 @@ static struct iwl_lib_ops iwl5150_lib = {
.rx_handler_setup = iwl5000_rx_handler_setup, .rx_handler_setup = iwl5000_rx_handler_setup,
.setup_deferred_work = iwl5000_setup_deferred_work, .setup_deferred_work = iwl5000_setup_deferred_work,
.is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
.dump_nic_event_log = iwl_dump_nic_event_log,
.dump_nic_error_log = iwl_dump_nic_error_log,
.load_ucode = iwl5000_load_ucode, .load_ucode = iwl5000_load_ucode,
.init_alive_start = iwl5000_init_alive_start, .init_alive_start = iwl5000_init_alive_start,
.alive_notify = iwl5000_alive_notify, .alive_notify = iwl5000_alive_notify,

View File

@ -100,6 +100,8 @@ static struct iwl_lib_ops iwl6000_lib = {
.setup_deferred_work = iwl5000_setup_deferred_work, .setup_deferred_work = iwl5000_setup_deferred_work,
.is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
.load_ucode = iwl5000_load_ucode, .load_ucode = iwl5000_load_ucode,
.dump_nic_event_log = iwl_dump_nic_event_log,
.dump_nic_error_log = iwl_dump_nic_error_log,
.init_alive_start = iwl5000_init_alive_start, .init_alive_start = iwl5000_init_alive_start,
.alive_notify = iwl5000_alive_notify, .alive_notify = iwl5000_alive_notify,
.send_tx_power = iwl5000_send_tx_power, .send_tx_power = iwl5000_send_tx_power,

View File

@ -1526,6 +1526,191 @@ static int iwl_read_ucode(struct iwl_priv *priv)
return ret; return ret;
} }
#ifdef CONFIG_IWLWIFI_DEBUG
static const char *desc_lookup_text[] = {
"OK",
"FAIL",
"BAD_PARAM",
"BAD_CHECKSUM",
"NMI_INTERRUPT_WDG",
"SYSASSERT",
"FATAL_ERROR",
"BAD_COMMAND",
"HW_ERROR_TUNE_LOCK",
"HW_ERROR_TEMPERATURE",
"ILLEGAL_CHAN_FREQ",
"VCC_NOT_STABLE",
"FH_ERROR",
"NMI_INTERRUPT_HOST",
"NMI_INTERRUPT_ACTION_PT",
"NMI_INTERRUPT_UNKNOWN",
"UCODE_VERSION_MISMATCH",
"HW_ERROR_ABS_LOCK",
"HW_ERROR_CAL_LOCK_FAIL",
"NMI_INTERRUPT_INST_ACTION_PT",
"NMI_INTERRUPT_DATA_ACTION_PT",
"NMI_TRM_HW_ER",
"NMI_INTERRUPT_TRM",
"NMI_INTERRUPT_BREAK_POINT"
"DEBUG_0",
"DEBUG_1",
"DEBUG_2",
"DEBUG_3",
"UNKNOWN"
};
static const char *desc_lookup(int i)
{
int max = ARRAY_SIZE(desc_lookup_text) - 1;
if (i < 0 || i > max)
i = max;
return desc_lookup_text[i];
}
#define ERROR_START_OFFSET (1 * sizeof(u32))
#define ERROR_ELEM_SIZE (7 * sizeof(u32))
void iwl_dump_nic_error_log(struct iwl_priv *priv)
{
u32 data2, line;
u32 desc, time, count, base, data1;
u32 blink1, blink2, ilink1, ilink2;
if (priv->ucode_type == UCODE_INIT)
base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
else
base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
return;
}
count = iwl_read_targ_mem(priv, base);
if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
IWL_ERR(priv, "Start IWL Error Log Dump:\n");
IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
priv->status, count);
}
desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
IWL_ERR(priv, "Desc Time "
"data1 data2 line\n");
IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
desc_lookup(desc), desc, time, data1, data2, line);
IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
ilink1, ilink2);
}
#define EVENT_START_OFFSET (4 * sizeof(u32))
/**
* iwl_print_event_log - Dump error event log to syslog
*
*/
static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
u32 num_events, u32 mode)
{
u32 i;
u32 base; /* SRAM byte address of event log header */
u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
u32 ptr; /* SRAM byte address of log data */
u32 ev, time, data; /* event log data */
if (num_events == 0)
return;
if (priv->ucode_type == UCODE_INIT)
base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
else
base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
if (mode == 0)
event_size = 2 * sizeof(u32);
else
event_size = 3 * sizeof(u32);
ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
/* "time" is actually "data" for mode 0 (no timestamp).
* place event id # at far right for easier visual parsing. */
for (i = 0; i < num_events; i++) {
ev = iwl_read_targ_mem(priv, ptr);
ptr += sizeof(u32);
time = iwl_read_targ_mem(priv, ptr);
ptr += sizeof(u32);
if (mode == 0) {
/* data, ev */
IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
} else {
data = iwl_read_targ_mem(priv, ptr);
ptr += sizeof(u32);
IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
time, data, ev);
}
}
}
void iwl_dump_nic_event_log(struct iwl_priv *priv)
{
u32 base; /* SRAM byte address of event log header */
u32 capacity; /* event log capacity in # entries */
u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
u32 num_wraps; /* # times uCode wrapped to top of log */
u32 next_entry; /* index of next entry to be written by uCode */
u32 size; /* # entries that we'll print */
if (priv->ucode_type == UCODE_INIT)
base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
else
base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
return;
}
/* event log header */
capacity = iwl_read_targ_mem(priv, base);
mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
size = num_wraps ? capacity : next_entry;
/* bail out if nothing in log */
if (size == 0) {
IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
return;
}
IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
size, num_wraps);
/* if uCode has wrapped back to top of log, start at the oldest entry,
* i.e the next one that uCode would fill. */
if (num_wraps)
iwl_print_event_log(priv, next_entry,
capacity - next_entry, mode);
/* (then/else) start at top of log */
iwl_print_event_log(priv, 0, next_entry, mode);
}
#endif
/** /**
* iwl_alive_start - called after REPLY_ALIVE notification received * iwl_alive_start - called after REPLY_ALIVE notification received
* from protocol/runtime uCode (initialization uCode's * from protocol/runtime uCode (initialization uCode's

View File

@ -1309,189 +1309,6 @@ static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr); IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
} }
static const char *desc_lookup_text[] = {
"OK",
"FAIL",
"BAD_PARAM",
"BAD_CHECKSUM",
"NMI_INTERRUPT_WDG",
"SYSASSERT",
"FATAL_ERROR",
"BAD_COMMAND",
"HW_ERROR_TUNE_LOCK",
"HW_ERROR_TEMPERATURE",
"ILLEGAL_CHAN_FREQ",
"VCC_NOT_STABLE",
"FH_ERROR",
"NMI_INTERRUPT_HOST",
"NMI_INTERRUPT_ACTION_PT",
"NMI_INTERRUPT_UNKNOWN",
"UCODE_VERSION_MISMATCH",
"HW_ERROR_ABS_LOCK",
"HW_ERROR_CAL_LOCK_FAIL",
"NMI_INTERRUPT_INST_ACTION_PT",
"NMI_INTERRUPT_DATA_ACTION_PT",
"NMI_TRM_HW_ER",
"NMI_INTERRUPT_TRM",
"NMI_INTERRUPT_BREAK_POINT"
"DEBUG_0",
"DEBUG_1",
"DEBUG_2",
"DEBUG_3",
"UNKNOWN"
};
static const char *desc_lookup(int i)
{
int max = ARRAY_SIZE(desc_lookup_text) - 1;
if (i < 0 || i > max)
i = max;
return desc_lookup_text[i];
}
#define ERROR_START_OFFSET (1 * sizeof(u32))
#define ERROR_ELEM_SIZE (7 * sizeof(u32))
static void iwl_dump_nic_error_log(struct iwl_priv *priv)
{
u32 data2, line;
u32 desc, time, count, base, data1;
u32 blink1, blink2, ilink1, ilink2;
if (priv->ucode_type == UCODE_INIT)
base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
else
base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
return;
}
count = iwl_read_targ_mem(priv, base);
if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
IWL_ERR(priv, "Start IWL Error Log Dump:\n");
IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
priv->status, count);
}
desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
IWL_ERR(priv, "Desc Time "
"data1 data2 line\n");
IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
desc_lookup(desc), desc, time, data1, data2, line);
IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
ilink1, ilink2);
}
#define EVENT_START_OFFSET (4 * sizeof(u32))
/**
* iwl_print_event_log - Dump error event log to syslog
*
*/
static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
u32 num_events, u32 mode)
{
u32 i;
u32 base; /* SRAM byte address of event log header */
u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
u32 ptr; /* SRAM byte address of log data */
u32 ev, time, data; /* event log data */
if (num_events == 0)
return;
if (priv->ucode_type == UCODE_INIT)
base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
else
base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
if (mode == 0)
event_size = 2 * sizeof(u32);
else
event_size = 3 * sizeof(u32);
ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
/* "time" is actually "data" for mode 0 (no timestamp).
* place event id # at far right for easier visual parsing. */
for (i = 0; i < num_events; i++) {
ev = iwl_read_targ_mem(priv, ptr);
ptr += sizeof(u32);
time = iwl_read_targ_mem(priv, ptr);
ptr += sizeof(u32);
if (mode == 0) {
/* data, ev */
IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
} else {
data = iwl_read_targ_mem(priv, ptr);
ptr += sizeof(u32);
IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
time, data, ev);
}
}
}
void iwl_dump_nic_event_log(struct iwl_priv *priv)
{
u32 base; /* SRAM byte address of event log header */
u32 capacity; /* event log capacity in # entries */
u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
u32 num_wraps; /* # times uCode wrapped to top of log */
u32 next_entry; /* index of next entry to be written by uCode */
u32 size; /* # entries that we'll print */
if (priv->ucode_type == UCODE_INIT)
base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
else
base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
return;
}
/* event log header */
capacity = iwl_read_targ_mem(priv, base);
mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
size = num_wraps ? capacity : next_entry;
/* bail out if nothing in log */
if (size == 0) {
IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
return;
}
IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
size, num_wraps);
/* if uCode has wrapped back to top of log, start at the oldest entry,
* i.e the next one that uCode would fill. */
if (num_wraps)
iwl_print_event_log(priv, next_entry,
capacity - next_entry, mode);
/* (then/else) start at top of log */
iwl_print_event_log(priv, 0, next_entry, mode);
}
#endif #endif
/** /**
* iwl_irq_handle_error - called for HW or SW error interrupt from card * iwl_irq_handle_error - called for HW or SW error interrupt from card
@ -1506,8 +1323,8 @@ void iwl_irq_handle_error(struct iwl_priv *priv)
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) { if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) {
iwl_dump_nic_error_log(priv); priv->cfg->ops->lib->dump_nic_error_log(priv);
iwl_dump_nic_event_log(priv); priv->cfg->ops->lib->dump_nic_event_log(priv);
iwl_print_rx_config_cmd(priv); iwl_print_rx_config_cmd(priv);
} }
#endif #endif

View File

@ -166,6 +166,8 @@ struct iwl_lib_ops {
int (*is_valid_rtc_data_addr)(u32 addr); int (*is_valid_rtc_data_addr)(u32 addr);
/* 1st ucode load */ /* 1st ucode load */
int (*load_ucode)(struct iwl_priv *priv); int (*load_ucode)(struct iwl_priv *priv);
void (*dump_nic_event_log)(struct iwl_priv *priv);
void (*dump_nic_error_log)(struct iwl_priv *priv);
/* power management */ /* power management */
struct iwl_apm_ops apm_ops; struct iwl_apm_ops apm_ops;
@ -540,7 +542,19 @@ int iwl_pci_resume(struct pci_dev *pdev);
/***************************************************** /*****************************************************
* Error Handling Debugging * Error Handling Debugging
******************************************************/ ******************************************************/
#ifdef CONFIG_IWLWIFI_DEBUG
void iwl_dump_nic_event_log(struct iwl_priv *priv); void iwl_dump_nic_event_log(struct iwl_priv *priv);
void iwl_dump_nic_error_log(struct iwl_priv *priv);
#else
static inline void iwl_dump_nic_event_log(struct iwl_priv *priv)
{
}
static inline void iwl_dump_nic_error_log(struct iwl_priv *priv)
{
}
#endif
void iwl_clear_isr_stats(struct iwl_priv *priv); void iwl_clear_isr_stats(struct iwl_priv *priv);
/***************************************************** /*****************************************************

View File

@ -410,7 +410,7 @@ static ssize_t iwl_dbgfs_nvm_read(struct file *file,
pos += scnprintf(buf + pos, buf_size - pos, "0x%.4x ", ofs); pos += scnprintf(buf + pos, buf_size - pos, "0x%.4x ", ofs);
hex_dump_to_buffer(ptr + ofs, 16 , 16, 2, buf + pos, hex_dump_to_buffer(ptr + ofs, 16 , 16, 2, buf + pos,
buf_size - pos, 0); buf_size - pos, 0);
pos += strlen(buf); pos += strlen(buf + pos);
if (buf_size - pos > 0) if (buf_size - pos > 0)
buf[pos++] = '\n'; buf[pos++] = '\n';
} }
@ -436,7 +436,7 @@ static ssize_t iwl_dbgfs_log_event_write(struct file *file,
if (sscanf(buf, "%d", &event_log_flag) != 1) if (sscanf(buf, "%d", &event_log_flag) != 1)
return -EFAULT; return -EFAULT;
if (event_log_flag == 1) if (event_log_flag == 1)
iwl_dump_nic_event_log(priv); priv->cfg->ops->lib->dump_nic_event_log(priv);
return count; return count;
} }
@ -909,7 +909,7 @@ static ssize_t iwl_dbgfs_traffic_log_read(struct file *file,
"0x%.4x ", ofs); "0x%.4x ", ofs);
hex_dump_to_buffer(ptr + ofs, 16, 16, 2, hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
buf + pos, bufsz - pos, 0); buf + pos, bufsz - pos, 0);
pos += strlen(buf); pos += strlen(buf + pos);
if (bufsz - pos > 0) if (bufsz - pos > 0)
buf[pos++] = '\n'; buf[pos++] = '\n';
} }
@ -932,7 +932,7 @@ static ssize_t iwl_dbgfs_traffic_log_read(struct file *file,
"0x%.4x ", ofs); "0x%.4x ", ofs);
hex_dump_to_buffer(ptr + ofs, 16, 16, 2, hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
buf + pos, bufsz - pos, 0); buf + pos, bufsz - pos, 0);
pos += strlen(buf); pos += strlen(buf + pos);
if (bufsz - pos > 0) if (bufsz - pos > 0)
buf[pos++] = '\n'; buf[pos++] = '\n';
} }

View File

@ -197,6 +197,12 @@ void iwl_cmd_queue_free(struct iwl_priv *priv)
pci_free_consistent(dev, priv->hw_params.tfd_size * pci_free_consistent(dev, priv->hw_params.tfd_size *
txq->q.n_bd, txq->tfds, txq->q.dma_addr); txq->q.n_bd, txq->tfds, txq->q.dma_addr);
/* deallocate arrays */
kfree(txq->cmd);
kfree(txq->meta);
txq->cmd = NULL;
txq->meta = NULL;
/* 0-fill queue descriptor structure */ /* 0-fill queue descriptor structure */
memset(txq, 0, sizeof(*txq)); memset(txq, 0, sizeof(*txq));
} }

View File

@ -1481,6 +1481,7 @@ static inline void iwl_synchronize_irq(struct iwl_priv *priv)
tasklet_kill(&priv->irq_tasklet); tasklet_kill(&priv->irq_tasklet);
} }
#ifdef CONFIG_IWLWIFI_DEBUG
static const char *desc_lookup(int i) static const char *desc_lookup(int i)
{ {
switch (i) { switch (i) {
@ -1504,7 +1505,7 @@ static const char *desc_lookup(int i)
#define ERROR_START_OFFSET (1 * sizeof(u32)) #define ERROR_START_OFFSET (1 * sizeof(u32))
#define ERROR_ELEM_SIZE (7 * sizeof(u32)) #define ERROR_ELEM_SIZE (7 * sizeof(u32))
static void iwl3945_dump_nic_error_log(struct iwl_priv *priv) void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
{ {
u32 i; u32 i;
u32 desc, time, count, base, data1; u32 desc, time, count, base, data1;
@ -1598,7 +1599,7 @@ static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
} }
} }
static void iwl3945_dump_nic_event_log(struct iwl_priv *priv) void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
{ {
u32 base; /* SRAM byte address of event log header */ u32 base; /* SRAM byte address of event log header */
u32 capacity; /* event log capacity in # entries */ u32 capacity; /* event log capacity in # entries */
@ -1640,6 +1641,16 @@ static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
iwl3945_print_event_log(priv, 0, next_entry, mode); iwl3945_print_event_log(priv, 0, next_entry, mode);
} }
#else
void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
{
}
void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
{
}
#endif
static void iwl3945_irq_tasklet(struct iwl_priv *priv) static void iwl3945_irq_tasklet(struct iwl_priv *priv)
{ {
@ -3683,21 +3694,6 @@ static ssize_t dump_error_log(struct device *d,
static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
static ssize_t dump_event_log(struct device *d,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct iwl_priv *priv = dev_get_drvdata(d);
char *p = (char *)buf;
if (p[0] == '1')
iwl3945_dump_nic_event_log(priv);
return strnlen(buf, count);
}
static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
/***************************************************************************** /*****************************************************************************
* *
* driver setup and tear down * driver setup and tear down
@ -3742,7 +3738,6 @@ static struct attribute *iwl3945_sysfs_entries[] = {
&dev_attr_antenna.attr, &dev_attr_antenna.attr,
&dev_attr_channels.attr, &dev_attr_channels.attr,
&dev_attr_dump_errors.attr, &dev_attr_dump_errors.attr,
&dev_attr_dump_events.attr,
&dev_attr_flags.attr, &dev_attr_flags.attr,
&dev_attr_filter_flags.attr, &dev_attr_filter_flags.attr,
#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT

View File

@ -1041,6 +1041,9 @@ static int sony_nc_resume(struct acpi_device *device)
sony_backlight_update_status(sony_backlight_device) < 0) sony_backlight_update_status(sony_backlight_device) < 0)
printk(KERN_WARNING DRV_PFX "unable to restore brightness level\n"); printk(KERN_WARNING DRV_PFX "unable to restore brightness level\n");
/* re-read rfkill state */
sony_nc_rfkill_update();
return 0; return 0;
} }
@ -1078,6 +1081,8 @@ static int sony_nc_setup_rfkill(struct acpi_device *device,
struct rfkill *rfk; struct rfkill *rfk;
enum rfkill_type type; enum rfkill_type type;
const char *name; const char *name;
int result;
bool hwblock;
switch (nc_type) { switch (nc_type) {
case SONY_WIFI: case SONY_WIFI:
@ -1105,6 +1110,10 @@ static int sony_nc_setup_rfkill(struct acpi_device *device,
if (!rfk) if (!rfk)
return -ENOMEM; return -ENOMEM;
sony_call_snc_handle(0x124, 0x200, &result);
hwblock = !(result & 0x1);
rfkill_set_hw_state(rfk, hwblock);
err = rfkill_register(rfk); err = rfkill_register(rfk);
if (err) { if (err) {
rfkill_destroy(rfk); rfkill_destroy(rfk);

View File

@ -44,7 +44,7 @@ struct ip_tunnel_prl {
__u16 flags; __u16 flags;
__u16 __reserved; __u16 __reserved;
__u32 datalen; __u32 datalen;
__u32 rs_delay; __u32 __reserved2;
/* data follows */ /* data follows */
}; };

View File

@ -27,18 +27,11 @@ struct ip_tunnel
unsigned int prl_count; /* # of entries in PRL */ unsigned int prl_count; /* # of entries in PRL */
}; };
/* ISATAP: default interval between RS in secondy */
#define IPTUNNEL_RS_DEFAULT_DELAY (900)
struct ip_tunnel_prl_entry struct ip_tunnel_prl_entry
{ {
struct ip_tunnel_prl_entry *next; struct ip_tunnel_prl_entry *next;
__be32 addr; __be32 addr;
u16 flags; u16 flags;
unsigned long rs_delay;
struct timer_list rs_timer;
struct ip_tunnel *tunnel;
spinlock_t lock;
}; };
#define IPTUNNEL_XMIT() do { \ #define IPTUNNEL_XMIT() do { \

View File

@ -14,6 +14,7 @@ extern int wext_handle_ioctl(struct net *net, struct ifreq *ifr, unsigned int cm
void __user *arg); void __user *arg);
extern int compat_wext_handle_ioctl(struct net *net, unsigned int cmd, extern int compat_wext_handle_ioctl(struct net *net, unsigned int cmd,
unsigned long arg); unsigned long arg);
extern struct iw_statistics *get_wireless_stats(struct net_device *dev);
#else #else
static inline int wext_proc_init(struct net *net) static inline int wext_proc_init(struct net *net)
{ {

View File

@ -169,6 +169,7 @@ static size_t vlan_get_size(const struct net_device *dev)
struct vlan_dev_info *vlan = vlan_dev_info(dev); struct vlan_dev_info *vlan = vlan_dev_info(dev);
return nla_total_size(2) + /* IFLA_VLAN_ID */ return nla_total_size(2) + /* IFLA_VLAN_ID */
sizeof(struct ifla_vlan_flags) + /* IFLA_VLAN_FLAGS */
vlan_qos_map_size(vlan->nr_ingress_mappings) + vlan_qos_map_size(vlan->nr_ingress_mappings) +
vlan_qos_map_size(vlan->nr_egress_mappings); vlan_qos_map_size(vlan->nr_egress_mappings);
} }

View File

@ -641,28 +641,29 @@ static int ax25_setsockopt(struct socket *sock, int level, int optname,
case SO_BINDTODEVICE: case SO_BINDTODEVICE:
if (optlen > IFNAMSIZ) if (optlen > IFNAMSIZ)
optlen=IFNAMSIZ; optlen = IFNAMSIZ;
if (copy_from_user(devname, optval, optlen)) { if (copy_from_user(devname, optval, optlen)) {
res = -EFAULT; res = -EFAULT;
break; break;
} }
dev = dev_get_by_name(&init_net, devname);
if (dev == NULL) {
res = -ENODEV;
break;
}
if (sk->sk_type == SOCK_SEQPACKET && if (sk->sk_type == SOCK_SEQPACKET &&
(sock->state != SS_UNCONNECTED || (sock->state != SS_UNCONNECTED ||
sk->sk_state == TCP_LISTEN)) { sk->sk_state == TCP_LISTEN)) {
res = -EADDRNOTAVAIL; res = -EADDRNOTAVAIL;
dev_put(dev); break;
}
dev = dev_get_by_name(&init_net, devname);
if (!dev) {
res = -ENODEV;
break; break;
} }
ax25->ax25_dev = ax25_dev_ax25dev(dev); ax25->ax25_dev = ax25_dev_ax25dev(dev);
ax25_fillin_cb(ax25, ax25->ax25_dev); ax25_fillin_cb(ax25, ax25->ax25_dev);
dev_put(dev);
break; break;
default: default:

View File

@ -432,6 +432,7 @@ int br_add_if(struct net_bridge *br, struct net_device *dev)
br_fdb_delete_by_port(br, p, 1); br_fdb_delete_by_port(br, p, 1);
err1: err1:
kobject_put(&p->kobj); kobject_put(&p->kobj);
p = NULL; /* kobject_put frees */
err0: err0:
dev_set_promiscuity(dev, -1); dev_set_promiscuity(dev, -1);
put_back: put_back:

View File

@ -16,7 +16,7 @@
#include <net/sock.h> #include <net/sock.h>
#include <linux/rtnetlink.h> #include <linux/rtnetlink.h>
#include <linux/wireless.h> #include <linux/wireless.h>
#include <net/iw_handler.h> #include <net/wext.h>
#include "net-sysfs.h" #include "net-sysfs.h"
@ -363,15 +363,13 @@ static ssize_t wireless_show(struct device *d, char *buf,
char *)) char *))
{ {
struct net_device *dev = to_net_dev(d); struct net_device *dev = to_net_dev(d);
const struct iw_statistics *iw = NULL; const struct iw_statistics *iw;
ssize_t ret = -EINVAL; ssize_t ret = -EINVAL;
read_lock(&dev_base_lock); read_lock(&dev_base_lock);
if (dev_isalive(dev)) { if (dev_isalive(dev)) {
if (dev->wireless_handlers && iw = get_wireless_stats(dev);
dev->wireless_handlers->get_wireless_stats) if (iw)
iw = dev->wireless_handlers->get_wireless_stats(dev);
if (iw != NULL)
ret = (*format)(iw, buf); ret = (*format)(iw, buf);
} }
read_unlock(&dev_base_lock); read_unlock(&dev_base_lock);
@ -505,7 +503,7 @@ int netdev_register_kobject(struct net_device *net)
*groups++ = &netstat_group; *groups++ = &netstat_group;
#ifdef CONFIG_WIRELESS_EXT_SYSFS #ifdef CONFIG_WIRELESS_EXT_SYSFS
if (net->wireless_handlers && net->wireless_handlers->get_wireless_stats) if (net->wireless_handlers || net->ieee80211_ptr)
*groups++ = &wireless_group; *groups++ = &wireless_group;
#endif #endif
#endif /* CONFIG_SYSFS */ #endif /* CONFIG_SYSFS */

View File

@ -194,7 +194,7 @@ static int dcbnl_reply(u8 value, u8 event, u8 cmd, u8 attr, u32 pid,
nlmsg_end(dcbnl_skb, nlh); nlmsg_end(dcbnl_skb, nlh);
ret = rtnl_unicast(dcbnl_skb, &init_net, pid); ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret) if (ret)
goto err; return -EINVAL;
return 0; return 0;
nlmsg_failure: nlmsg_failure:
@ -275,7 +275,7 @@ static int dcbnl_getpfccfg(struct net_device *netdev, struct nlattr **tb,
ret = rtnl_unicast(dcbnl_skb, &init_net, pid); ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret) if (ret)
goto err; goto err_out;
return 0; return 0;
nlmsg_failure: nlmsg_failure:
@ -316,12 +316,11 @@ static int dcbnl_getperm_hwaddr(struct net_device *netdev, struct nlattr **tb,
ret = rtnl_unicast(dcbnl_skb, &init_net, pid); ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret) if (ret)
goto err; goto err_out;
return 0; return 0;
nlmsg_failure: nlmsg_failure:
err:
kfree_skb(dcbnl_skb); kfree_skb(dcbnl_skb);
err_out: err_out:
return -EINVAL; return -EINVAL;
@ -383,7 +382,7 @@ static int dcbnl_getcap(struct net_device *netdev, struct nlattr **tb,
ret = rtnl_unicast(dcbnl_skb, &init_net, pid); ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret) if (ret)
goto err; goto err_out;
return 0; return 0;
nlmsg_failure: nlmsg_failure:
@ -460,7 +459,7 @@ static int dcbnl_getnumtcs(struct net_device *netdev, struct nlattr **tb,
ret = rtnl_unicast(dcbnl_skb, &init_net, pid); ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret) { if (ret) {
ret = -EINVAL; ret = -EINVAL;
goto err; goto err_out;
} }
return 0; return 0;
@ -799,7 +798,7 @@ static int __dcbnl_pg_getcfg(struct net_device *netdev, struct nlattr **tb,
ret = rtnl_unicast(dcbnl_skb, &init_net, pid); ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret) if (ret)
goto err; goto err_out;
return 0; return 0;
@ -1063,7 +1062,7 @@ static int dcbnl_bcn_getcfg(struct net_device *netdev, struct nlattr **tb,
ret = rtnl_unicast(dcbnl_skb, &init_net, pid); ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret) if (ret)
goto err; goto err_out;
return 0; return 0;

View File

@ -658,7 +658,6 @@ void ndisc_send_rs(struct net_device *dev, const struct in6_addr *saddr,
&icmp6h, NULL, &icmp6h, NULL,
send_sllao ? ND_OPT_SOURCE_LL_ADDR : 0); send_sllao ? ND_OPT_SOURCE_LL_ADDR : 0);
} }
EXPORT_SYMBOL(ndisc_send_rs);
static void ndisc_error_report(struct neighbour *neigh, struct sk_buff *skb) static void ndisc_error_report(struct neighbour *neigh, struct sk_buff *skb)

View File

@ -15,7 +15,6 @@
* Roger Venning <r.venning@telstra.com>: 6to4 support * Roger Venning <r.venning@telstra.com>: 6to4 support
* Nate Thompson <nate@thebog.net>: 6to4 support * Nate Thompson <nate@thebog.net>: 6to4 support
* Fred Templin <fred.l.templin@boeing.com>: isatap support * Fred Templin <fred.l.templin@boeing.com>: isatap support
* Sascha Hlusiak <mail@saschahlusiak.de>: stateless autoconf for isatap
*/ */
#include <linux/module.h> #include <linux/module.h>
@ -223,44 +222,6 @@ static struct ip_tunnel * ipip6_tunnel_locate(struct net *net,
return NULL; return NULL;
} }
static void ipip6_tunnel_rs_timer(unsigned long data)
{
struct ip_tunnel_prl_entry *p = (struct ip_tunnel_prl_entry *) data;
struct inet6_dev *ifp;
struct inet6_ifaddr *addr;
spin_lock(&p->lock);
ifp = __in6_dev_get(p->tunnel->dev);
read_lock_bh(&ifp->lock);
for (addr = ifp->addr_list; addr; addr = addr->if_next) {
struct in6_addr rtr;
if (!(ipv6_addr_type(&addr->addr) & IPV6_ADDR_LINKLOCAL))
continue;
/* Send RS to guessed linklocal address of router
*
* Better: send to ff02::2 encapsuled in unicast directly
* to router-v4 instead of guessing the v6 address.
*
* Cisco/Windows seem to not set the u/l bit correctly,
* so we won't guess right.
*/
ipv6_addr_set(&rtr, htonl(0xFE800000), 0, 0, 0);
if (!__ipv6_isatap_ifid(rtr.s6_addr + 8,
p->addr)) {
ndisc_send_rs(p->tunnel->dev, &addr->addr, &rtr);
}
}
read_unlock_bh(&ifp->lock);
mod_timer(&p->rs_timer, jiffies + HZ * p->rs_delay);
spin_unlock(&p->lock);
return;
}
static struct ip_tunnel_prl_entry * static struct ip_tunnel_prl_entry *
__ipip6_tunnel_locate_prl(struct ip_tunnel *t, __be32 addr) __ipip6_tunnel_locate_prl(struct ip_tunnel *t, __be32 addr)
{ {
@ -319,7 +280,6 @@ static int ipip6_tunnel_get_prl(struct ip_tunnel *t,
continue; continue;
kp[c].addr = prl->addr; kp[c].addr = prl->addr;
kp[c].flags = prl->flags; kp[c].flags = prl->flags;
kp[c].rs_delay = prl->rs_delay;
c++; c++;
if (kprl.addr != htonl(INADDR_ANY)) if (kprl.addr != htonl(INADDR_ANY))
break; break;
@ -369,23 +329,11 @@ ipip6_tunnel_add_prl(struct ip_tunnel *t, struct ip_tunnel_prl *a, int chg)
} }
p->next = t->prl; p->next = t->prl;
p->tunnel = t;
t->prl = p; t->prl = p;
t->prl_count++; t->prl_count++;
spin_lock_init(&p->lock);
setup_timer(&p->rs_timer, ipip6_tunnel_rs_timer, (unsigned long) p);
update: update:
p->addr = a->addr; p->addr = a->addr;
p->flags = a->flags; p->flags = a->flags;
p->rs_delay = a->rs_delay;
if (p->rs_delay == 0)
p->rs_delay = IPTUNNEL_RS_DEFAULT_DELAY;
spin_lock(&p->lock);
del_timer(&p->rs_timer);
if (p->flags & PRL_DEFAULT)
mod_timer(&p->rs_timer, jiffies + 1);
spin_unlock(&p->lock);
out: out:
write_unlock(&ipip6_lock); write_unlock(&ipip6_lock);
return err; return err;
@ -404,9 +352,6 @@ ipip6_tunnel_del_prl(struct ip_tunnel *t, struct ip_tunnel_prl *a)
if ((*p)->addr == a->addr) { if ((*p)->addr == a->addr) {
x = *p; x = *p;
*p = x->next; *p = x->next;
spin_lock(&x->lock);
del_timer(&x->rs_timer);
spin_unlock(&x->lock);
kfree(x); kfree(x);
t->prl_count--; t->prl_count--;
goto out; goto out;
@ -417,9 +362,6 @@ ipip6_tunnel_del_prl(struct ip_tunnel *t, struct ip_tunnel_prl *a)
while (t->prl) { while (t->prl) {
x = t->prl; x = t->prl;
t->prl = t->prl->next; t->prl = t->prl->next;
spin_lock(&x->lock);
del_timer(&x->rs_timer);
spin_unlock(&x->lock);
kfree(x); kfree(x);
t->prl_count--; t->prl_count--;
} }

View File

@ -1388,8 +1388,8 @@ ieee80211_rx_mgmt_disassoc(struct ieee80211_sub_if_data *sdata,
reason_code = le16_to_cpu(mgmt->u.disassoc.reason_code); reason_code = le16_to_cpu(mgmt->u.disassoc.reason_code);
printk(KERN_DEBUG "%s: disassociated (Reason: %u)\n", printk(KERN_DEBUG "%s: disassociated from %pM (Reason: %u)\n",
sdata->dev->name, reason_code); sdata->dev->name, mgmt->sa, reason_code);
ieee80211_set_disassoc(sdata, false); ieee80211_set_disassoc(sdata, false);
return RX_MGMT_CFG80211_DISASSOC; return RX_MGMT_CFG80211_DISASSOC;
@ -1675,7 +1675,7 @@ static void ieee80211_rx_mgmt_probe_resp(struct ieee80211_sub_if_data *sdata,
/* direct probe may be part of the association flow */ /* direct probe may be part of the association flow */
if (wk && wk->state == IEEE80211_MGD_STATE_PROBE) { if (wk && wk->state == IEEE80211_MGD_STATE_PROBE) {
printk(KERN_DEBUG "%s direct probe responded\n", printk(KERN_DEBUG "%s: direct probe responded\n",
sdata->dev->name); sdata->dev->name);
wk->tries = 0; wk->tries = 0;
wk->state = IEEE80211_MGD_STATE_AUTH; wk->state = IEEE80211_MGD_STATE_AUTH;
@ -2502,9 +2502,6 @@ int ieee80211_mgd_deauth(struct ieee80211_sub_if_data *sdata,
struct ieee80211_mgd_work *wk; struct ieee80211_mgd_work *wk;
const u8 *bssid = NULL; const u8 *bssid = NULL;
printk(KERN_DEBUG "%s: deauthenticating by local choice (reason=%d)\n",
sdata->dev->name, req->reason_code);
mutex_lock(&ifmgd->mtx); mutex_lock(&ifmgd->mtx);
if (ifmgd->associated && &ifmgd->associated->cbss == req->bss) { if (ifmgd->associated && &ifmgd->associated->cbss == req->bss) {
@ -2532,6 +2529,9 @@ int ieee80211_mgd_deauth(struct ieee80211_sub_if_data *sdata,
mutex_unlock(&ifmgd->mtx); mutex_unlock(&ifmgd->mtx);
printk(KERN_DEBUG "%s: deauthenticating from %pM by local choice (reason=%d)\n",
sdata->dev->name, bssid, req->reason_code);
ieee80211_send_deauth_disassoc(sdata, bssid, ieee80211_send_deauth_disassoc(sdata, bssid,
IEEE80211_STYPE_DEAUTH, req->reason_code, IEEE80211_STYPE_DEAUTH, req->reason_code,
cookie); cookie);
@ -2545,9 +2545,6 @@ int ieee80211_mgd_disassoc(struct ieee80211_sub_if_data *sdata,
{ {
struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; struct ieee80211_if_managed *ifmgd = &sdata->u.mgd;
printk(KERN_DEBUG "%s: disassociating by local choice (reason=%d)\n",
sdata->dev->name, req->reason_code);
mutex_lock(&ifmgd->mtx); mutex_lock(&ifmgd->mtx);
/* /*
@ -2561,6 +2558,9 @@ int ieee80211_mgd_disassoc(struct ieee80211_sub_if_data *sdata,
return -ENOLINK; return -ENOLINK;
} }
printk(KERN_DEBUG "%s: disassociating from %pM by local choice (reason=%d)\n",
sdata->dev->name, req->bss->bssid, req->reason_code);
ieee80211_set_disassoc(sdata, false); ieee80211_set_disassoc(sdata, false);
mutex_unlock(&ifmgd->mtx); mutex_unlock(&ifmgd->mtx);

View File

@ -1788,7 +1788,7 @@ void netlink_ack(struct sk_buff *in_skb, struct nlmsghdr *nlh, int err)
} }
rep = __nlmsg_put(skb, NETLINK_CB(in_skb).pid, nlh->nlmsg_seq, rep = __nlmsg_put(skb, NETLINK_CB(in_skb).pid, nlh->nlmsg_seq,
NLMSG_ERROR, sizeof(struct nlmsgerr), 0); NLMSG_ERROR, payload, 0);
errmsg = nlmsg_data(rep); errmsg = nlmsg_data(rep);
errmsg->error = err; errmsg->error = err;
memcpy(&errmsg->msg, nlh, err ? nlh->nlmsg_len : sizeof(*nlh)); memcpy(&errmsg->msg, nlh, err ? nlh->nlmsg_len : sizeof(*nlh));

View File

@ -2098,12 +2098,17 @@ SYSCALL_DEFINE2(socketcall, int, call, unsigned long __user *, args)
unsigned long a[6]; unsigned long a[6];
unsigned long a0, a1; unsigned long a0, a1;
int err; int err;
unsigned int len;
if (call < 1 || call > SYS_ACCEPT4) if (call < 1 || call > SYS_ACCEPT4)
return -EINVAL; return -EINVAL;
len = nargs[call];
if (len > sizeof(a))
return -EINVAL;
/* copy_from_user should be SMP safe. */ /* copy_from_user should be SMP safe. */
if (copy_from_user(a, args, nargs[call])) if (copy_from_user(a, args, len))
return -EFAULT; return -EFAULT;
audit_socketcall(nargs[call] / sizeof(unsigned long), a); audit_socketcall(nargs[call] / sizeof(unsigned long), a);

View File

@ -762,8 +762,7 @@ int __cfg80211_connect(struct cfg80211_registered_device *rdev,
wdev->conn->params.ssid = wdev->ssid; wdev->conn->params.ssid = wdev->ssid;
wdev->conn->params.ssid_len = connect->ssid_len; wdev->conn->params.ssid_len = connect->ssid_len;
/* don't care about result -- but fill bssid & channel */ /* see if we have the bss already */
if (!wdev->conn->params.bssid || !wdev->conn->params.channel)
bss = cfg80211_get_conn_bss(wdev); bss = cfg80211_get_conn_bss(wdev);
wdev->sme_state = CFG80211_SME_CONNECTING; wdev->sme_state = CFG80211_SME_CONNECTING;

View File

@ -30,6 +30,7 @@ int cfg80211_mgd_wext_connect(struct cfg80211_registered_device *rdev,
if (wdev->wext.keys) { if (wdev->wext.keys) {
wdev->wext.keys->def = wdev->wext.default_key; wdev->wext.keys->def = wdev->wext.default_key;
wdev->wext.keys->defmgmt = wdev->wext.default_mgmt_key; wdev->wext.keys->defmgmt = wdev->wext.default_mgmt_key;
if (wdev->wext.default_key != -1)
wdev->wext.connect.privacy = true; wdev->wext.connect.privacy = true;
} }
@ -229,8 +230,7 @@ int cfg80211_mgd_wext_giwessid(struct net_device *dev,
data->flags = 1; data->flags = 1;
data->length = wdev->wext.connect.ssid_len; data->length = wdev->wext.connect.ssid_len;
memcpy(ssid, wdev->wext.connect.ssid, data->length); memcpy(ssid, wdev->wext.connect.ssid, data->length);
} else }
data->flags = 0;
wdev_unlock(wdev); wdev_unlock(wdev);
return 0; return 0;
@ -306,8 +306,6 @@ int cfg80211_mgd_wext_giwap(struct net_device *dev,
wdev_lock(wdev); wdev_lock(wdev);
if (wdev->current_bss) if (wdev->current_bss)
memcpy(ap_addr->sa_data, wdev->current_bss->pub.bssid, ETH_ALEN); memcpy(ap_addr->sa_data, wdev->current_bss->pub.bssid, ETH_ALEN);
else if (wdev->wext.connect.bssid)
memcpy(ap_addr->sa_data, wdev->wext.connect.bssid, ETH_ALEN);
else else
memset(ap_addr->sa_data, 0, ETH_ALEN); memset(ap_addr->sa_data, 0, ETH_ALEN);
wdev_unlock(wdev); wdev_unlock(wdev);

View File

@ -470,7 +470,7 @@ static iw_handler get_handler(struct net_device *dev, unsigned int cmd)
/* /*
* Get statistics out of the driver * Get statistics out of the driver
*/ */
static struct iw_statistics *get_wireless_stats(struct net_device *dev) struct iw_statistics *get_wireless_stats(struct net_device *dev)
{ {
/* New location */ /* New location */
if ((dev->wireless_handlers != NULL) && if ((dev->wireless_handlers != NULL) &&
@ -773,10 +773,13 @@ static int ioctl_standard_iw_point(struct iw_point *iwp, unsigned int cmd,
essid_compat = 1; essid_compat = 1;
else if (IW_IS_SET(cmd) && (iwp->length != 0)) { else if (IW_IS_SET(cmd) && (iwp->length != 0)) {
char essid[IW_ESSID_MAX_SIZE + 1]; char essid[IW_ESSID_MAX_SIZE + 1];
unsigned int len;
len = iwp->length * descr->token_size;
err = copy_from_user(essid, iwp->pointer, if (len > IW_ESSID_MAX_SIZE)
iwp->length * return -EFAULT;
descr->token_size);
err = copy_from_user(essid, iwp->pointer, len);
if (err) if (err)
return -EFAULT; return -EFAULT;