mirror of https://gitee.com/openkylin/linux.git
ath9k_hw: add AR9580 support
Here are the AR9580 1.0 initvals checksums using the Atheros initvals-tools [1]. This is useful for when we udate the initvals again with other values. It ensures that we match the same initvals used internally. The tool is documented on the wiki [2]. $ ./initvals -f ar9580-1p0 0x00000000e912711f ar9580_1p0_modes_fast_clock 0x000000004a488fc7 ar9580_1p0_radio_postamble 0x00000000f3888b02 ar9580_1p0_baseband_core 0x0000000003f783bb ar9580_1p0_mac_postamble 0x0000000094be244a ar9580_1p0_low_ob_db_tx_gain_table 0x0000000094be244a ar9580_1p0_high_power_tx_gain_table 0x0000000090be244a ar9580_1p0_lowest_ob_db_tx_gain_table 0x00000000ed9eaac6 ar9580_1p0_baseband_core_txfir_coeff_japan_2484 0x00000000c4d66d1b ar9580_1p0_mac_core 0x00000000e8e9043a ar9580_1p0_mixed_ob_db_tx_gain_table 0x000000003521a300 ar9580_1p0_wo_xlna_rx_gain_table 0x00000000301fc841 ar9580_1p0_soc_postamble 0x00000000a9a06b3a ar9580_1p0_high_ob_db_tx_gain_table 0x00000000a15ccf1b ar9580_1p0_soc_preamble 0x0000000029495000 ar9580_1p0_rx_gain_table 0x0000000037ac0ee8 ar9580_1p0_radio_core 0x00000000603a1b80 ar9580_1p0_baseband_postamble 0x000000003d8b4396 ar9580_1p0_pcie_phy_clkreq_enable_L1 0x00000000398b4396 ar9580_1p0_pcie_phy_clkreq_disable_L1 0x00000000397b4396 ar9580_1p0_pcie_phy_pll_on_clkreq [1] git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/initvals-tool.git [2] http://wireless.kernel.org/en/users/Drivers/ath9k_hw/initvals-tool Cc: David Quan <dquan@qca.qualcomm.com> Cc: Kathy Giori <kgiori@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Tested-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Luis R. Rodriguez
John W. Linville
parent
5fa71984f3
commit
5a63ef0faf
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@ -21,6 +21,7 @@
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#include "ar9340_initvals.h"
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#include "ar9330_1p1_initvals.h"
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#include "ar9330_1p2_initvals.h"
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#include "ar9580_1p0_initvals.h"
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/* General hardware code for the AR9003 hadware family */
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@ -253,6 +254,56 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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ar9485_1_1_pcie_phy_clkreq_disable_L1,
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ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
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2);
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} else if (AR_SREV_9580(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9580_1p0_mac_core,
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ARRAY_SIZE(ar9580_1p0_mac_core), 2);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9580_1p0_mac_postamble,
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ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9580_1p0_baseband_core,
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ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9580_1p0_baseband_postamble,
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ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9580_1p0_radio_core,
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ARRAY_SIZE(ar9580_1p0_radio_core), 2);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9580_1p0_radio_postamble,
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ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9580_1p0_soc_preamble,
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ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9580_1p0_soc_postamble,
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ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9580_1p0_rx_gain_table,
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ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9580_1p0_low_ob_db_tx_gain_table,
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ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
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5);
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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ar9580_1p0_modes_fast_clock,
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ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
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3);
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} else {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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@ -348,6 +399,11 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
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ar9485_modes_lowest_ob_db_tx_gain_1_1,
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ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
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5);
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else if (AR_SREV_9580(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9580_1p0_lowest_ob_db_tx_gain_table,
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ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
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5);
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else
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
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@ -375,6 +431,11 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
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ar9485Modes_high_ob_db_tx_gain_1_1,
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ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
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5);
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else if (AR_SREV_9580(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9580_1p0_high_ob_db_tx_gain_table,
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ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
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5);
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else
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_high_ob_db_tx_gain_table_2p2,
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@ -402,6 +463,11 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
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ar9485Modes_low_ob_db_tx_gain_1_1,
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ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
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5);
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else if (AR_SREV_9580(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9580_1p0_low_ob_db_tx_gain_table,
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ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
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5);
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else
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_low_ob_db_tx_gain_table_2p2,
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@ -429,6 +495,11 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
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ar9485Modes_high_power_tx_gain_1_1,
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ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
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5);
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else if (AR_SREV_9580(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9580_1p0_high_power_tx_gain_table,
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ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
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5);
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else
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_high_power_tx_gain_table_2p2,
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@ -463,6 +534,11 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
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ar9485Common_wo_xlna_rx_gain_1_1,
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ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
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2);
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else if (AR_SREV_9580(ah))
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9580_1p0_rx_gain_table,
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ARRAY_SIZE(ar9580_1p0_rx_gain_table),
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2);
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else
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_rx_gain_table_2p2,
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@ -490,6 +566,11 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
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ar9485Common_wo_xlna_rx_gain_1_1,
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ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
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2);
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else if (AR_SREV_9580(ah))
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9580_1p0_wo_xlna_rx_gain_table,
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ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
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2);
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else
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_wo_xlna_rx_gain_table_2p2,
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File diff suppressed because it is too large
Load Diff
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@ -663,6 +663,7 @@ int ath9k_hw_init(struct ath_hw *ah)
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case AR9300_DEVID_AR9485_PCIE:
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case AR9300_DEVID_AR9330:
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case AR9300_DEVID_AR9340:
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case AR9300_DEVID_AR9580:
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break;
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default:
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if (common->bus_ops->ath_bus_type == ATH_USB)
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@ -45,6 +45,7 @@
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#define AR9300_DEVID_PCIE 0x0030
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#define AR9300_DEVID_AR9340 0x0031
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#define AR9300_DEVID_AR9485_PCIE 0x0032
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#define AR9300_DEVID_AR9580 0x0033
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#define AR9300_DEVID_AR9330 0x0035
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#define AR5416_AR9100_DEVID 0x000b
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@ -793,6 +793,8 @@
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#define AR_SREV_REVISION_9485_10 0
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#define AR_SREV_REVISION_9485_11 1
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#define AR_SREV_VERSION_9340 0x300
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#define AR_SREV_VERSION_9580 0x1C0
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#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */
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#define AR_SREV_5416(_ah) \
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(((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
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@ -893,6 +895,18 @@
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(AR_SREV_9285_12_OR_LATER(_ah) && \
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((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
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#define AR_SREV_9580(_ah) \
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(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \
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((_ah)->hw_version.macRev >= AR_SREV_REVISION_9580_10))
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#define AR_SREV_9580_10(_ah) \
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(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \
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((_ah)->hw_version.macRev == AR_SREV_REVISION_9580_10))
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/* NOTE: When adding chips newer than Peacock, add chip check here */
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#define AR_SREV_9580_10_OR_LATER(_ah) \
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(AR_SREV_9580(_ah))
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enum ath_usb_dev {
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AR9280_USB = 1, /* AR7010 + AR9280, UB94 */
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AR9287_USB = 2, /* AR7010 + AR9287, UB95 */
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