mirror of https://gitee.com/openkylin/linux.git
[TG3]: Add new hard_start_xmit
Support 5787 hardware TSO using a new flag TG3_FLG2_HW_TSO_2. Since the TSO interface is slightly different and these chips have finally fixed the 4GB DMA problem and do not have the 40-bit DMA problem, a new hard_start_xmit is used for these chips. All previous chips will use the old hard_start_xmit that is now renamed tg3_start_xmit_dma_bug(). Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
1b27777a9b
commit
5a6f3074c2
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@ -3655,7 +3655,135 @@ static void tg3_set_txd(struct tg3 *tp, int entry,
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txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
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}
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/* hard_start_xmit for devices that don't have any bugs and
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* support TG3_FLG2_HW_TSO_2 only.
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*/
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static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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struct tg3 *tp = netdev_priv(dev);
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dma_addr_t mapping;
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u32 len, entry, base_flags, mss;
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len = skb_headlen(skb);
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/* No BH disabling for tx_lock here. We are running in BH disabled
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* context and TX reclaim runs via tp->poll inside of a software
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* interrupt. Furthermore, IRQ processing runs lockless so we have
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* no IRQ context deadlocks to worry about either. Rejoice!
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*/
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if (!spin_trylock(&tp->tx_lock))
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return NETDEV_TX_LOCKED;
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if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
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if (!netif_queue_stopped(dev)) {
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netif_stop_queue(dev);
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/* This is a hard error, log it. */
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printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
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"queue awake!\n", dev->name);
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}
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spin_unlock(&tp->tx_lock);
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return NETDEV_TX_BUSY;
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}
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entry = tp->tx_prod;
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base_flags = 0;
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#if TG3_TSO_SUPPORT != 0
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mss = 0;
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if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
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(mss = skb_shinfo(skb)->tso_size) != 0) {
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int tcp_opt_len, ip_tcp_len;
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if (skb_header_cloned(skb) &&
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pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
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dev_kfree_skb(skb);
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goto out_unlock;
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}
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tcp_opt_len = ((skb->h.th->doff - 5) * 4);
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ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
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base_flags |= (TXD_FLAG_CPU_PRE_DMA |
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TXD_FLAG_CPU_POST_DMA);
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skb->nh.iph->check = 0;
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skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
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skb->h.th->check = 0;
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mss |= (ip_tcp_len + tcp_opt_len) << 9;
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}
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else if (skb->ip_summed == CHECKSUM_HW)
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base_flags |= TXD_FLAG_TCPUDP_CSUM;
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#else
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mss = 0;
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if (skb->ip_summed == CHECKSUM_HW)
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base_flags |= TXD_FLAG_TCPUDP_CSUM;
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#endif
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#if TG3_VLAN_TAG_USED
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if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
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base_flags |= (TXD_FLAG_VLAN |
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(vlan_tx_tag_get(skb) << 16));
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#endif
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/* Queue skb data, a.k.a. the main skb fragment. */
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mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
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tp->tx_buffers[entry].skb = skb;
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pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
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tg3_set_txd(tp, entry, mapping, len, base_flags,
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(skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
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entry = NEXT_TX(entry);
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/* Now loop through additional data fragments, and queue them. */
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if (skb_shinfo(skb)->nr_frags > 0) {
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unsigned int i, last;
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last = skb_shinfo(skb)->nr_frags - 1;
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for (i = 0; i <= last; i++) {
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skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
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len = frag->size;
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mapping = pci_map_page(tp->pdev,
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frag->page,
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frag->page_offset,
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len, PCI_DMA_TODEVICE);
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tp->tx_buffers[entry].skb = NULL;
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pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
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tg3_set_txd(tp, entry, mapping, len,
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base_flags, (i == last) | (mss << 1));
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entry = NEXT_TX(entry);
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}
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}
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/* Packets are ready, update Tx producer idx local and on card. */
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tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
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tp->tx_prod = entry;
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if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
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netif_stop_queue(dev);
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if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
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netif_wake_queue(tp->dev);
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}
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out_unlock:
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mmiowb();
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spin_unlock(&tp->tx_lock);
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dev->trans_start = jiffies;
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return NETDEV_TX_OK;
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}
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/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
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* support TG3_FLG2_HW_TSO_1 or firmware TSO only.
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*/
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static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
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{
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struct tg3 *tp = netdev_priv(dev);
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dma_addr_t mapping;
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@ -9811,8 +9939,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
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tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
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if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
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if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
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else
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1;
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
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@ -10163,10 +10295,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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else
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tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
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/* It seems all chips can get confused if TX buffers
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/* All chips before 5787 can get confused if TX buffers
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* straddle the 4GB address boundary in some cases.
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*/
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tp->dev->hard_start_xmit = tg3_start_xmit;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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tp->dev->hard_start_xmit = tg3_start_xmit;
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else
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tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
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tp->rx_offset = 2;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
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@ -2194,7 +2194,7 @@ struct tg3 {
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#define TG3_FLG2_PHY_SERDES 0x00002000
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#define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
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#define TG3_FLG2_FLASH 0x00008000
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#define TG3_FLG2_HW_TSO 0x00010000
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#define TG3_FLG2_HW_TSO_1 0x00010000
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#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
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#define TG3_FLG2_5705_PLUS 0x00040000
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#define TG3_FLG2_5750_PLUS 0x00080000
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@ -2207,6 +2207,8 @@ struct tg3 {
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#define TG3_FLG2_PARALLEL_DETECT 0x01000000
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#define TG3_FLG2_ICH_WORKAROUND 0x02000000
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#define TG3_FLG2_5780_CLASS 0x04000000
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#define TG3_FLG2_HW_TSO_2 0x08000000
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#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
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u32 split_mode_max_reqs;
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#define SPLIT_MODE_5704_MAX_REQ 3
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