mirror of https://gitee.com/openkylin/linux.git
drm/amd/amdgpu: gfx6 tidy up raster config
Clean up coding style in gfx_v6_0_write_harvested_raster_configs() Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1195,24 +1195,22 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
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if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
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raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
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if (!se_mask[idx]) {
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if (!se_mask[idx])
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raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
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} else {
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else
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raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
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}
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}
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pkr0_mask &= rb_mask;
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pkr1_mask &= rb_mask;
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if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
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raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
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if (!pkr0_mask) {
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if (!pkr0_mask)
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raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
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} else {
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else
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raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
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}
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}
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if (rb_per_se >= 2) {
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unsigned rb0_mask = 1 << (se * rb_per_se);
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@ -1223,14 +1221,13 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
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if (!rb0_mask || !rb1_mask) {
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raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
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if (!rb0_mask) {
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if (!rb0_mask)
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raster_config_se |=
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RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
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} else {
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else
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raster_config_se |=
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RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
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}
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}
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if (rb_per_se > 2) {
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rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
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@ -1240,16 +1237,15 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
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if (!rb0_mask || !rb1_mask) {
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raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
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if (!rb0_mask) {
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if (!rb0_mask)
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raster_config_se |=
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RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
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} else {
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else
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raster_config_se |=
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RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
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}
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}
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}
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}
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/* GRBM_GFX_INDEX has a different offset on SI */
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gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
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