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drm/amd/display: Use calculated disp_clk_khz value for dce110 

[Why]

The calculated values for actual disp_clk_khz were ignored when
notifying pplib of the new display requirements. In order to honor DFS
bypass clocks from the hardware, the calculated value should be used.

[How]

The return value for set_dispclk is now assigned back into new_clocks
and correctly carried through into dccg->clks.phyclk_khz. When notifying
pplib of new display requirements dccg->clks.phyclk_khz is used
instead of dce.dispclk_khz. The value of dce.dispclk_khz was never
explicitly set to anything before.

A 15% higher display clock value than calculated is no longer requested
for dce110 since it now makes use of the calculated value.

Since dce112 makes use of dce110's set_bandwidth but not its
update_clocks it needs to have the value correctly carried through.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas 2018-07-23 14:13:23 -04:00 committed by Alex Deucher
parent 78e4405cec
commit 5ae6fe5729
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
View File

@ -463,7 +463,7 @@ static void dce12_update_clocks(struct dccg *dccg,
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
clock_voltage_req.clocks_in_khz = new_clocks->dispclk_khz;
dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);
new_clocks->dispclk_khz = dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);
dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);
@ -661,7 +661,7 @@ static void dce_update_clocks(struct dccg *dccg,
}
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {
dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);
new_clocks->dispclk_khz = dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);
dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
}
}

4
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -2530,7 +2530,7 @@ static void pplib_apply_display_requirements(
/* TODO: dce11.2*/
pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz;
pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz;
dce110_fill_display_configs(context, pp_display_cfg);
@ -2559,7 +2559,7 @@ void dce110_set_bandwidth(
{
struct dc_clocks req_clks;
req_clks.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
req_clks.dispclk_khz = context->bw.dce.dispclk_khz;
req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context);
if (decrease_allowed)