mirror of https://gitee.com/openkylin/linux.git
[PATCH] bnx2: add 5708 support
Add 5708 copper and serdes basic support, including 2.5 Gbps support on 5708 serdes. SPEED_2500 is also added to ethtool.h Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Michael Chan
John W. Linville
parent
17ecc1e63b
commit
5b0c76ad94
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@ -41,6 +41,8 @@ typedef enum {
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NC370I,
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BCM5706S,
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NC370F,
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BCM5708,
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BCM5708S,
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} board_t;
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/* indexed by board_t, above */
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@ -52,6 +54,8 @@ static struct {
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{ "HP NC370i Multifunction Gigabit Server Adapter" },
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{ "Broadcom NetXtreme II BCM5706 1000Base-SX" },
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{ "HP NC370F Multifunction Gigabit Server Adapter" },
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{ "Broadcom NetXtreme II BCM5708 1000Base-T" },
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{ "Broadcom NetXtreme II BCM5708 1000Base-SX" },
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};
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static struct pci_device_id bnx2_pci_tbl[] = {
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@ -61,10 +65,14 @@ static struct pci_device_id bnx2_pci_tbl[] = {
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PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
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PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
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{ 0, }
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};
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@ -430,6 +438,18 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp)
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return;
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}
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if ((bp->phy_flags & PHY_SERDES_FLAG) &&
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(CHIP_NUM(bp) == CHIP_NUM_5708)) {
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u32 val;
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bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
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if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
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bp->flow_ctrl |= FLOW_CTRL_TX;
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if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
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bp->flow_ctrl |= FLOW_CTRL_RX;
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return;
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}
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bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
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bnx2_read_phy(bp, MII_LPA, &remote_adv);
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@ -476,7 +496,36 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp)
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}
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static int
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bnx2_serdes_linkup(struct bnx2 *bp)
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bnx2_5708s_linkup(struct bnx2 *bp)
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{
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u32 val;
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bp->link_up = 1;
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bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
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switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
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case BCM5708S_1000X_STAT1_SPEED_10:
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bp->line_speed = SPEED_10;
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break;
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case BCM5708S_1000X_STAT1_SPEED_100:
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bp->line_speed = SPEED_100;
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break;
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case BCM5708S_1000X_STAT1_SPEED_1G:
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bp->line_speed = SPEED_1000;
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break;
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case BCM5708S_1000X_STAT1_SPEED_2G5:
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bp->line_speed = SPEED_2500;
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break;
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}
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if (val & BCM5708S_1000X_STAT1_FD)
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bp->duplex = DUPLEX_FULL;
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else
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bp->duplex = DUPLEX_HALF;
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return 0;
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}
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static int
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bnx2_5706s_linkup(struct bnx2 *bp)
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{
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u32 bmcr, local_adv, remote_adv, common;
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@ -593,13 +642,27 @@ bnx2_set_mac_link(struct bnx2 *bp)
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val = REG_RD(bp, BNX2_EMAC_MODE);
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val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
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BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK);
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BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
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BNX2_EMAC_MODE_25G);
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if (bp->link_up) {
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if (bp->line_speed != SPEED_1000)
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val |= BNX2_EMAC_MODE_PORT_MII;
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else
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val |= BNX2_EMAC_MODE_PORT_GMII;
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switch (bp->line_speed) {
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case SPEED_10:
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if (CHIP_NUM(bp) == CHIP_NUM_5708) {
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val |= BNX2_EMAC_MODE_PORT_MII_10;
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break;
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}
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/* fall through */
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case SPEED_100:
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val |= BNX2_EMAC_MODE_PORT_MII;
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break;
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case SPEED_2500:
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val |= BNX2_EMAC_MODE_25G;
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/* fall through */
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case SPEED_1000:
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val |= BNX2_EMAC_MODE_PORT_GMII;
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break;
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}
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}
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else {
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val |= BNX2_EMAC_MODE_PORT_GMII;
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@ -662,7 +725,10 @@ bnx2_set_link(struct bnx2 *bp)
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bp->link_up = 1;
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if (bp->phy_flags & PHY_SERDES_FLAG) {
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bnx2_serdes_linkup(bp);
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if (CHIP_NUM(bp) == CHIP_NUM_5706)
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bnx2_5706s_linkup(bp);
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else if (CHIP_NUM(bp) == CHIP_NUM_5708)
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bnx2_5708s_linkup(bp);
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}
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else {
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bnx2_copper_linkup(bp);
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@ -755,39 +821,61 @@ bnx2_phy_get_pause_adv(struct bnx2 *bp)
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static int
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bnx2_setup_serdes_phy(struct bnx2 *bp)
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{
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u32 adv, bmcr;
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u32 adv, bmcr, up1;
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u32 new_adv = 0;
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if (!(bp->autoneg & AUTONEG_SPEED)) {
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u32 new_bmcr;
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int force_link_down = 0;
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if (CHIP_NUM(bp) == CHIP_NUM_5708) {
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bnx2_read_phy(bp, BCM5708S_UP1, &up1);
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if (up1 & BCM5708S_UP1_2G5) {
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up1 &= ~BCM5708S_UP1_2G5;
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bnx2_write_phy(bp, BCM5708S_UP1, up1);
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force_link_down = 1;
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}
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}
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bnx2_read_phy(bp, MII_ADVERTISE, &adv);
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adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
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bnx2_read_phy(bp, MII_BMCR, &bmcr);
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new_bmcr = bmcr & ~BMCR_ANENABLE;
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new_bmcr |= BMCR_SPEED1000;
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if (bp->req_duplex == DUPLEX_FULL) {
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adv |= ADVERTISE_1000XFULL;
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new_bmcr |= BMCR_FULLDPLX;
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}
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else {
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adv |= ADVERTISE_1000XHALF;
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new_bmcr &= ~BMCR_FULLDPLX;
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}
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if (new_bmcr != bmcr) {
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if ((new_bmcr != bmcr) || (force_link_down)) {
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/* Force a link down visible on the other side */
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if (bp->link_up) {
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bnx2_read_phy(bp, MII_ADVERTISE, &adv);
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adv &= ~(ADVERTISE_1000XFULL |
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ADVERTISE_1000XHALF);
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bnx2_write_phy(bp, MII_ADVERTISE, adv);
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bnx2_write_phy(bp, MII_ADVERTISE, adv &
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~(ADVERTISE_1000XFULL |
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ADVERTISE_1000XHALF));
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bnx2_write_phy(bp, MII_BMCR, bmcr |
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BMCR_ANRESTART | BMCR_ANENABLE);
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bp->link_up = 0;
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netif_carrier_off(bp->dev);
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bnx2_write_phy(bp, MII_BMCR, new_bmcr);
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}
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bnx2_write_phy(bp, MII_ADVERTISE, adv);
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bnx2_write_phy(bp, MII_BMCR, new_bmcr);
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}
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return 0;
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}
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if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
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bnx2_read_phy(bp, BCM5708S_UP1, &up1);
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up1 |= BCM5708S_UP1_2G5;
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bnx2_write_phy(bp, BCM5708S_UP1, up1);
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}
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if (bp->advertising & ADVERTISED_1000baseT_Full)
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new_adv |= ADVERTISE_1000XFULL;
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@ -952,7 +1040,60 @@ bnx2_setup_phy(struct bnx2 *bp)
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}
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static int
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bnx2_init_serdes_phy(struct bnx2 *bp)
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bnx2_init_5708s_phy(struct bnx2 *bp)
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{
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u32 val;
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bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
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bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
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bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
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bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
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val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
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bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
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bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
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val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
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bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
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if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
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bnx2_read_phy(bp, BCM5708S_UP1, &val);
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val |= BCM5708S_UP1_2G5;
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bnx2_write_phy(bp, BCM5708S_UP1, val);
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}
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if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
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(CHIP_ID(bp) == CHIP_ID_5708_B0)) {
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/* increase tx signal amplitude */
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bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
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BCM5708S_BLK_ADDR_TX_MISC);
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bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
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val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
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bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
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bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
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}
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val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_CONFIG) &
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BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
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if (val) {
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u32 is_backplane;
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is_backplane = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
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BNX2_SHARED_HW_CFG_CONFIG);
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if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
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bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
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BCM5708S_BLK_ADDR_TX_MISC);
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bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
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bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
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BCM5708S_BLK_ADDR_DIG);
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}
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}
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return 0;
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}
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static int
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bnx2_init_5706s_phy(struct bnx2 *bp)
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{
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bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
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@ -990,6 +1131,8 @@ bnx2_init_serdes_phy(struct bnx2 *bp)
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static int
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bnx2_init_copper_phy(struct bnx2 *bp)
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{
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u32 val;
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bp->phy_flags |= PHY_CRC_FIX_FLAG;
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if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
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@ -1004,8 +1147,6 @@ bnx2_init_copper_phy(struct bnx2 *bp)
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}
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if (bp->dev->mtu > 1500) {
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u32 val;
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/* Set extended packet length bit */
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bnx2_write_phy(bp, 0x18, 0x7);
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bnx2_read_phy(bp, 0x18, &val);
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@ -1015,8 +1156,6 @@ bnx2_init_copper_phy(struct bnx2 *bp)
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bnx2_write_phy(bp, 0x10, val | 0x1);
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}
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else {
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u32 val;
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bnx2_write_phy(bp, 0x18, 0x7);
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bnx2_read_phy(bp, 0x18, &val);
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bnx2_write_phy(bp, 0x18, val & ~0x4007);
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@ -1025,6 +1164,10 @@ bnx2_init_copper_phy(struct bnx2 *bp)
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bnx2_write_phy(bp, 0x10, val & ~0x1);
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}
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/* ethernet@wirespeed */
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bnx2_write_phy(bp, 0x18, 0x7007);
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bnx2_read_phy(bp, 0x18, &val);
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bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
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return 0;
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}
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@ -1048,7 +1191,10 @@ bnx2_init_phy(struct bnx2 *bp)
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bp->phy_id |= val & 0xffff;
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if (bp->phy_flags & PHY_SERDES_FLAG) {
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rc = bnx2_init_serdes_phy(bp);
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if (CHIP_NUM(bp) == CHIP_NUM_5706)
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rc = bnx2_init_5706s_phy(bp);
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else if (CHIP_NUM(bp) == CHIP_NUM_5708)
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rc = bnx2_init_5708s_phy(bp);
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}
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else {
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rc = bnx2_init_copper_phy(bp);
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@ -3234,7 +3380,7 @@ bnx2_test_registers(struct bnx2 *bp)
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{ 0x1408, 0, 0x01c00800, 0x00000000 },
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{ 0x149c, 0, 0x8000ffff, 0x00000000 },
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{ 0x14a8, 0, 0x00000000, 0x000001ff },
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{ 0x14ac, 0, 0x4fffffff, 0x10000000 },
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{ 0x14ac, 0, 0x0fffffff, 0x10000000 },
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{ 0x14b0, 0, 0x00000002, 0x00000001 },
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{ 0x14b8, 0, 0x00000000, 0x00000000 },
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{ 0x14c0, 0, 0x00000000, 0x00000009 },
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@ -3577,7 +3723,7 @@ bnx2_test_memory(struct bnx2 *bp)
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u32 len;
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} mem_tbl[] = {
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{ 0x60000, 0x4000 },
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{ 0xa0000, 0x4000 },
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{ 0xa0000, 0x3000 },
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{ 0xe0000, 0x4000 },
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{ 0x120000, 0x4000 },
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{ 0x1a0000, 0x4000 },
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@ -4264,7 +4410,8 @@ bnx2_get_stats(struct net_device *dev)
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(unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
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stats_blk->stat_Dot3StatsLateCollisions);
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if (CHIP_NUM(bp) == CHIP_NUM_5706)
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if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
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(CHIP_ID(bp) == CHIP_ID_5708_A0))
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net_stats->tx_carrier_errors = 0;
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else {
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net_stats->tx_carrier_errors =
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@ -4814,6 +4961,14 @@ static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
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4,4,4,4,4,
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};
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static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
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8,0,8,8,8,8,8,8,8,8,
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4,4,4,4,4,4,4,4,4,4,
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4,4,4,4,4,4,4,4,4,4,
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4,4,4,4,4,4,4,4,4,4,
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4,4,4,4,4,
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};
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#define BNX2_NUM_TESTS 6
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static struct {
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@ -4922,8 +5077,13 @@ bnx2_get_ethtool_stats(struct net_device *dev,
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return;
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}
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if (CHIP_NUM(bp) == CHIP_NUM_5706)
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if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
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(CHIP_ID(bp) == CHIP_ID_5706_A1) ||
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(CHIP_ID(bp) == CHIP_ID_5706_A2) ||
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(CHIP_ID(bp) == CHIP_ID_5708_A0))
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stats_len_arr = bnx2_5706_stats_len_arr;
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else
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stats_len_arr = bnx2_5708_stats_len_arr;
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for (i = 0; i < BNX2_NUM_STATS; i++) {
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if (stats_len_arr[i] == 0) {
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@ -5205,8 +5365,6 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
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bp->phy_addr = 1;
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/* Get bus information. */
|
||||
reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
|
||||
if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
|
||||
|
|
@ -5316,10 +5474,19 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
|
|||
bp->timer_interval = HZ;
|
||||
bp->current_interval = HZ;
|
||||
|
||||
bp->phy_addr = 1;
|
||||
|
||||
/* Disable WOL support if we are running on a SERDES chip. */
|
||||
if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
|
||||
bp->phy_flags |= PHY_SERDES_FLAG;
|
||||
bp->flags |= NO_WOL_FLAG;
|
||||
if (CHIP_NUM(bp) == CHIP_NUM_5708) {
|
||||
bp->phy_addr = 2;
|
||||
reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
|
||||
BNX2_SHARED_HW_CFG_CONFIG);
|
||||
if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
|
||||
bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
|
||||
}
|
||||
}
|
||||
|
||||
if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
|
||||
|
|
|
|||
|
|
@ -1449,8 +1449,9 @@ struct l2_fhdr {
|
|||
#define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
|
||||
#define BNX2_EMAC_MODE_PORT_MII (1L<<2)
|
||||
#define BNX2_EMAC_MODE_PORT_GMII (2L<<2)
|
||||
#define BNX2_EMAC_MODE_PORT_UNDEF (3L<<2)
|
||||
#define BNX2_EMAC_MODE_PORT_MII_10 (3L<<2)
|
||||
#define BNX2_EMAC_MODE_MAC_LOOP (1L<<4)
|
||||
#define BNX2_EMAC_MODE_25G (1L<<5)
|
||||
#define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
|
||||
#define BNX2_EMAC_MODE_TX_BURST (1L<<8)
|
||||
#define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
|
||||
|
|
@ -3724,6 +3725,53 @@ struct l2_fhdr {
|
|||
#define PHY_ID(id) ((id) & 0xfffffff0)
|
||||
#define PHY_REV_ID(id) ((id) & 0xf)
|
||||
|
||||
/* 5708 Serdes PHY registers */
|
||||
|
||||
#define BCM5708S_UP1 0xb
|
||||
|
||||
#define BCM5708S_UP1_2G5 0x1
|
||||
|
||||
#define BCM5708S_BLK_ADDR 0x1f
|
||||
|
||||
#define BCM5708S_BLK_ADDR_DIG 0x0000
|
||||
#define BCM5708S_BLK_ADDR_DIG3 0x0002
|
||||
#define BCM5708S_BLK_ADDR_TX_MISC 0x0005
|
||||
|
||||
/* Digital Block */
|
||||
#define BCM5708S_1000X_CTL1 0x10
|
||||
|
||||
#define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001
|
||||
#define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010
|
||||
|
||||
#define BCM5708S_1000X_CTL2 0x11
|
||||
|
||||
#define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001
|
||||
|
||||
#define BCM5708S_1000X_STAT1 0x14
|
||||
|
||||
#define BCM5708S_1000X_STAT1_SGMII 0x0001
|
||||
#define BCM5708S_1000X_STAT1_LINK 0x0002
|
||||
#define BCM5708S_1000X_STAT1_FD 0x0004
|
||||
#define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018
|
||||
#define BCM5708S_1000X_STAT1_SPEED_10 0x0000
|
||||
#define BCM5708S_1000X_STAT1_SPEED_100 0x0008
|
||||
#define BCM5708S_1000X_STAT1_SPEED_1G 0x0010
|
||||
#define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018
|
||||
#define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020
|
||||
#define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040
|
||||
|
||||
/* Digital3 Block */
|
||||
#define BCM5708S_DIG_3_0 0x10
|
||||
|
||||
#define BCM5708S_DIG_3_0_USE_IEEE 0x0001
|
||||
|
||||
/* Tx/Misc Block */
|
||||
#define BCM5708S_TX_ACTL1 0x15
|
||||
|
||||
#define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30
|
||||
|
||||
#define BCM5708S_TX_ACTL3 0x17
|
||||
|
||||
#define MIN_ETHERNET_PACKET_SIZE 60
|
||||
#define MAX_ETHERNET_PACKET_SIZE 1514
|
||||
#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
|
||||
|
|
@ -3893,6 +3941,7 @@ struct bnx2 {
|
|||
#define PHY_SERDES_FLAG 1
|
||||
#define PHY_CRC_FIX_FLAG 2
|
||||
#define PHY_PARALLEL_DETECT_FLAG 4
|
||||
#define PHY_2_5G_CAPABLE_FLAG 8
|
||||
#define PHY_INT_MODE_MASK_FLAG 0x300
|
||||
#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
|
||||
#define PHY_INT_MODE_LINK_READY_FLAG 0x200
|
||||
|
|
@ -3901,6 +3950,7 @@ struct bnx2 {
|
|||
/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
|
||||
#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
|
||||
#define CHIP_NUM_5706 0x57060000
|
||||
#define CHIP_NUM_5708 0x57080000
|
||||
|
||||
#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
|
||||
#define CHIP_REV_Ax 0x00000000
|
||||
|
|
@ -3913,6 +3963,9 @@ struct bnx2 {
|
|||
#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
|
||||
#define CHIP_ID_5706_A0 0x57060000
|
||||
#define CHIP_ID_5706_A1 0x57060010
|
||||
#define CHIP_ID_5706_A2 0x57060020
|
||||
#define CHIP_ID_5708_A0 0x57080000
|
||||
#define CHIP_ID_5708_B0 0x57081000
|
||||
|
||||
#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf)
|
||||
|
||||
|
|
@ -4132,12 +4185,12 @@ struct fw_info {
|
|||
#define BNX2_LINK_STATUS 0x0000000c
|
||||
|
||||
#define BNX2_DRV_PULSE_MB 0x00000010
|
||||
#define BNX2_DRV_PULSE_SEQ_MASK 0x0000ffff
|
||||
#define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff
|
||||
|
||||
/* Indicate to the firmware not to go into the
|
||||
* OS absent when it is not getting driver pulse.
|
||||
* This is used for debugging. */
|
||||
#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00010000
|
||||
#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000
|
||||
|
||||
#define BNX2_DEV_INFO_SIGNATURE 0x00000020
|
||||
#define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900
|
||||
|
|
@ -4160,6 +4213,8 @@ struct fw_info {
|
|||
#define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1
|
||||
#define BNX2_SHARED_HW_CFG_PHY_COPPER 0
|
||||
#define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2
|
||||
#define BNX2_SHARED_HW_CFG_PHY_2_5G 0x20
|
||||
#define BNX2_SHARED_HW_CFG_PHY_BACKPLANE 0x40
|
||||
#define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
|
||||
#define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300
|
||||
#define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0
|
||||
|
|
@ -4173,9 +4228,11 @@ struct fw_info {
|
|||
|
||||
#define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054
|
||||
#define BNX2_PORT_HW_CFG_CONFIG 0x00000058
|
||||
#define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff
|
||||
#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000
|
||||
#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000
|
||||
#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000
|
||||
#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000
|
||||
|
||||
#define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
|
||||
#define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
|
||||
|
|
|
|||
|
|
@ -453,10 +453,11 @@ struct ethtool_ops {
|
|||
* it was foced up into this mode or autonegotiated.
|
||||
*/
|
||||
|
||||
/* The forced speed, 10Mb, 100Mb, gigabit, 10GbE. */
|
||||
/* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */
|
||||
#define SPEED_10 10
|
||||
#define SPEED_100 100
|
||||
#define SPEED_1000 1000
|
||||
#define SPEED_2500 2500
|
||||
#define SPEED_10000 10000
|
||||
|
||||
/* Duplex, half or full. */
|
||||
|
|
|
|||
|
|
@ -1785,6 +1785,7 @@
|
|||
#define PCI_DEVICE_ID_TIGON3_5704 0x1648
|
||||
#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649
|
||||
#define PCI_DEVICE_ID_NX2_5706 0x164a
|
||||
#define PCI_DEVICE_ID_NX2_5708 0x164c
|
||||
#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d
|
||||
#define PCI_DEVICE_ID_TIGON3_5705 0x1653
|
||||
#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
|
||||
|
|
@ -1809,6 +1810,7 @@
|
|||
#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7
|
||||
#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8
|
||||
#define PCI_DEVICE_ID_NX2_5706S 0x16aa
|
||||
#define PCI_DEVICE_ID_NX2_5708S 0x16ac
|
||||
#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6
|
||||
#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7
|
||||
#define PCI_DEVICE_ID_TIGON3_5781 0x16dd
|
||||
|
|
|
|||
Loading…
Reference in New Issue