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Merge branch 'gpio/merge' of git://git.secretlab.ca/git/linux-2.6 

* 'gpio/merge' of git://git.secretlab.ca/git/linux-2.6:
  gpio/samsung: make Kconfig options def_bool
  gpio/exynos4: Fix incorrect mapping of gpio pull-up macro to register setting
  GPIO: OMAP: add locking around calls to _set_gpio_triggering
  GPIO: OMAP: fix setting IRQWAKEN bits for OMAP4
  GPIO: OMAP: fix section mismatch warnings
  gpio: Fix gpio-exynos4 build fails in mainline
This commit is contained in:
Linus Torvalds 2011-06-08 08:22:29 -07:00
parent 46671b0355 c226feb013
commit 5b28f6a25e
3 changed files with 45 additions and 35 deletions
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28
drivers/gpio/Kconfig
View File

@ -87,32 +87,20 @@ config GPIO_IT8761E
Say yes here to support GPIO functionality of IT8761E super I/O chip.
config GPIO_EXYNOS4
bool "Samsung Exynos4 GPIO library support"
default y if CPU_EXYNOS4210
depends on ARM
help
Say yes here to support Samsung Exynos4 series SoCs GPIO library
def_bool y
depends on CPU_EXYNOS4210
config GPIO_PLAT_SAMSUNG
bool "Samsung SoCs GPIO library support"
default y if SAMSUNG_GPIOLIB_4BIT
depends on ARM
help
Say yes here to support Samsung SoCs GPIO library
def_bool y
depends on SAMSUNG_GPIOLIB_4BIT
config GPIO_S5PC100
bool "Samsung S5PC100 GPIO library support"
default y if CPU_S5PC100
depends on ARM
help
Say yes here to support Samsung S5PC100 SoCs GPIO library
def_bool y
depends on CPU_S5PC100
config GPIO_S5PV210
bool "Samsung S5PV210/S5PC110 GPIO library support"
default y if CPU_S5PV210
depends on ARM
help
Say yes here to support Samsung S5PV210/S5PC110 SoCs GPIO library
def_bool y
depends on CPU_S5PV210
config GPIO_PL061
bool "PrimeCell PL061 GPIO support"

29
drivers/gpio/gpio-exynos4.c
View File

@ -21,16 +21,37 @@
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
int s3c_gpio_setpull_exynos4(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull)
{
if (pull == S3C_GPIO_PULL_UP)
pull = 3;
return s3c_gpio_setpull_updown(chip, off, pull);
}
s3c_gpio_pull_t s3c_gpio_getpull_exynos4(struct s3c_gpio_chip *chip,
unsigned int off)
{
s3c_gpio_pull_t pull;
pull = s3c_gpio_getpull_updown(chip, off);
if (pull == 3)
pull = S3C_GPIO_PULL_UP;
return pull;
}
static struct s3c_gpio_cfg gpio_cfg = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
.set_pull = s3c_gpio_setpull_exynos4,
.get_pull = s3c_gpio_getpull_exynos4,
};
static struct s3c_gpio_cfg gpio_cfg_noint = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
.set_pull = s3c_gpio_setpull_exynos4,
.get_pull = s3c_gpio_getpull_exynos4,
};
/*

23
drivers/gpio/gpio-omap.c
View File

@ -432,7 +432,6 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
{
void __iomem *base = bank->base;
u32 gpio_bit = 1 << gpio;
u32 val;
if (cpu_is_omap44xx()) {
MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
@ -455,15 +454,8 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
}
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
if (cpu_is_omap44xx()) {
if (trigger != 0)
__raw_writel(1 << gpio, bank->base+
OMAP4_GPIO_IRQWAKEN0);
else {
val = __raw_readl(bank->base +
OMAP4_GPIO_IRQWAKEN0);
__raw_writel(val & (~(1 << gpio)), bank->base +
OMAP4_GPIO_IRQWAKEN0);
}
MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
trigger != 0);
} else {
/*
* GPIO wakeup request can only be generated on edge
@ -1134,8 +1126,11 @@ static void gpio_irq_shutdown(struct irq_data *d)
{
unsigned int gpio = d->irq - IH_GPIO_BASE;
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
_reset_gpio(bank, gpio);
spin_unlock_irqrestore(&bank->lock, flags);
}
static void gpio_ack_irq(struct irq_data *d)
@ -1150,9 +1145,12 @@ static void gpio_mask_irq(struct irq_data *d)
{
unsigned int gpio = d->irq - IH_GPIO_BASE;
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
_set_gpio_irqenable(bank, gpio, 0);
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
spin_unlock_irqrestore(&bank->lock, flags);
}
static void gpio_unmask_irq(struct irq_data *d)
@ -1161,7 +1159,9 @@ static void gpio_unmask_irq(struct irq_data *d)
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
unsigned int irq_mask = 1 << get_gpio_index(gpio);
u32 trigger = irqd_get_trigger_type(d);
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
if (trigger)
_set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
@ -1173,6 +1173,7 @@ static void gpio_unmask_irq(struct irq_data *d)
}
_set_gpio_irqenable(bank, gpio, 1);
spin_unlock_irqrestore(&bank->lock, flags);
}
static struct irq_chip gpio_irq_chip = {
@ -1524,7 +1525,7 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
}
}
static void __init omap_gpio_chip_init(struct gpio_bank *bank)
static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
{
int j;
static int gpio;