openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

drm/i915/chv: remove pre-production hardware workarounds 

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Appease gcc and remove the unused variable.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jani Nikula 2015-10-07 11:17:46 +03:00 committed by Daniel Vetter
parent d39398f537
commit 5b5929cbe3
1 changed files with 22 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
drivers/gpu/drm/i915/intel_pm.c
View File

@ -5061,32 +5061,27 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
struct drm_device *dev = dev_priv->dev; struct drm_device *dev = dev_priv->dev;
u32 val, rp0; u32 val, rp0;
if (dev->pdev->revision >= 0x20) { val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
switch (INTEL_INFO(dev)->eu_total) { switch (INTEL_INFO(dev)->eu_total) {
case 8: case 8:
/* (2 * 4) config */ /* (2 * 4) config */
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
break; break;
case 12: case 12:
/* (2 * 6) config */ /* (2 * 6) config */
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
break; break;
case 16: case 16:
/* (2 * 8) config */ /* (2 * 8) config */
default: default:
/* Setting (2 * 8) Min RP0 for any other combination */ /* Setting (2 * 8) Min RP0 for any other combination */
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
break; break;
}
rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
} else {
/* For pre-production hardware */
val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
PUNIT_GPU_STATUS_MAX_FREQ_MASK;
} }
rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
return rp0; return rp0;
} }
@ -5102,18 +5097,11 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
{ {
struct drm_device *dev = dev_priv->dev;
u32 val, rp1; u32 val, rp1;
if (dev->pdev->revision >= 0x20) { val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
} else {
/* For pre-production hardware */
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
PUNIT_GPU_STATUS_MAX_FREQ_MASK);
}
return rp1; return rp1;
} }