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soc: renesas: rcar-sysc: Add R8A7742 support 

Add support for RZ/G1H (R8A7742) SoC power areas to the R-Car SYSC driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1587678050-23468-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2020-04-23 22:40:43 +01:00 committed by Geert Uytterhoeven
parent 557b7e545e
commit 5b9fa9cbe6
5 changed files with 51 additions and 0 deletions
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4
drivers/soc/renesas/Kconfig
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@ -261,6 +261,10 @@ config ARCH_R8A77995
endif # ARM64
# SoC
config SYSC_R8A7742
bool "RZ/G1H System Controller support" if COMPILE_TEST
select SYSC_RCAR
config SYSC_R8A7743
bool "RZ/G1M System Controller support" if COMPILE_TEST
select SYSC_RCAR

1
drivers/soc/renesas/Makefile
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@ -3,6 +3,7 @@
obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o
# SoC
obj-$(CONFIG_SYSC_R8A7742) += r8a7742-sysc.o
obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o

42
drivers/soc/renesas/r8a7742-sysc.c Normal file
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@ -0,0 +1,42 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas RZ/G1H System Controller
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <linux/kernel.h>
#include <dt-bindings/power/r8a7742-sysc.h>
#include "rcar-sysc.h"
static const struct rcar_sysc_area r8a7742_areas[] __initconst = {
{ "always-on", 0, 0, R8A7742_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
{ "ca15-scu", 0x180, 0, R8A7742_PD_CA15_SCU, R8A7742_PD_ALWAYS_ON,
PD_SCU },
{ "ca15-cpu0", 0x40, 0, R8A7742_PD_CA15_CPU0, R8A7742_PD_CA15_SCU,
PD_CPU_NOCR },
{ "ca15-cpu1", 0x40, 1, R8A7742_PD_CA15_CPU1, R8A7742_PD_CA15_SCU,
PD_CPU_NOCR },
{ "ca15-cpu2", 0x40, 2, R8A7742_PD_CA15_CPU2, R8A7742_PD_CA15_SCU,
PD_CPU_NOCR },
{ "ca15-cpu3", 0x40, 3, R8A7742_PD_CA15_CPU3, R8A7742_PD_CA15_SCU,
PD_CPU_NOCR },
{ "ca7-scu", 0x100, 0, R8A7742_PD_CA7_SCU, R8A7742_PD_ALWAYS_ON,
PD_SCU },
{ "ca7-cpu0", 0x1c0, 0, R8A7742_PD_CA7_CPU0, R8A7742_PD_CA7_SCU,
PD_CPU_NOCR },
{ "ca7-cpu1", 0x1c0, 1, R8A7742_PD_CA7_CPU1, R8A7742_PD_CA7_SCU,
PD_CPU_NOCR },
{ "ca7-cpu2", 0x1c0, 2, R8A7742_PD_CA7_CPU2, R8A7742_PD_CA7_SCU,
PD_CPU_NOCR },
{ "ca7-cpu3", 0x1c0, 3, R8A7742_PD_CA7_CPU3, R8A7742_PD_CA7_SCU,
PD_CPU_NOCR },
{ "rgx", 0xc0, 0, R8A7742_PD_RGX, R8A7742_PD_ALWAYS_ON },
};
const struct rcar_sysc_info r8a7742_sysc_info __initconst = {
.areas = r8a7742_areas,
.num_areas = ARRAY_SIZE(r8a7742_areas),
};

3
drivers/soc/renesas/rcar-sysc.c
View File

@ -273,6 +273,9 @@ static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
}
static const struct of_device_id rcar_sysc_matches[] __initconst = {
#ifdef CONFIG_SYSC_R8A7742
{ .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info },
#endif
#ifdef CONFIG_SYSC_R8A7743
{ .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
/* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */

1
drivers/soc/renesas/rcar-sysc.h
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@ -49,6 +49,7 @@ struct rcar_sysc_info {
u32 extmask_val; /* SYSCEXTMASK register mask value */
};
extern const struct rcar_sysc_info r8a7742_sysc_info;
extern const struct rcar_sysc_info r8a7743_sysc_info;
extern const struct rcar_sysc_info r8a7745_sysc_info;
extern const struct rcar_sysc_info r8a77470_sysc_info;