mirror of https://gitee.com/openkylin/linux.git
x86/mm/set_memory: Fix -Wmissing-prototypes warnings
Add missing includes and move prototypes into the header set_memory.h in order to fix -Wmissing-prototypes warnings. [ bp: Add ifdeffery around arch_invalidate_pmem() ] Signed-off-by: Benjamin Thiel <b.thiel@posteo.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200320145028.6013-1-b.thiel@posteo.de
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@ -46,6 +46,8 @@ int set_memory_4k(unsigned long addr, int numpages);
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int set_memory_encrypted(unsigned long addr, int numpages);
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int set_memory_decrypted(unsigned long addr, int numpages);
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int set_memory_np_noalias(unsigned long addr, int numpages);
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int set_memory_nonglobal(unsigned long addr, int numpages);
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int set_memory_global(unsigned long addr, int numpages);
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int set_pages_array_uc(struct page **pages, int addrinarray);
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int set_pages_array_wc(struct page **pages, int addrinarray);
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@ -15,6 +15,7 @@
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#include <linux/gfp.h>
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#include <linux/pci.h>
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#include <linux/vmalloc.h>
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#include <linux/libnvdimm.h>
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#include <asm/e820/api.h>
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#include <asm/processor.h>
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@ -304,11 +305,13 @@ void clflush_cache_range(void *vaddr, unsigned int size)
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}
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EXPORT_SYMBOL_GPL(clflush_cache_range);
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#ifdef CONFIG_ARCH_HAS_PMEM_API
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void arch_invalidate_pmem(void *addr, size_t size)
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{
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clflush_cache_range(addr, size);
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}
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EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
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#endif
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static void __cpa_flush_all(void *arg)
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{
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@ -39,6 +39,7 @@
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#include <asm/tlbflush.h>
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#include <asm/desc.h>
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#include <asm/sections.h>
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#include <asm/set_memory.h>
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#undef pr_fmt
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#define pr_fmt(fmt) "Kernel/User page tables isolation: " fmt
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@ -554,13 +555,6 @@ static inline bool pti_kernel_image_global_ok(void)
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return true;
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}
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/*
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* This is the only user for these and it is not arch-generic
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* like the other set_memory.h functions. Just extern them.
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*/
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extern int set_memory_nonglobal(unsigned long addr, int numpages);
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extern int set_memory_global(unsigned long addr, int numpages);
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/*
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* For some configurations, map all of kernel text into the user page
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* tables. This reduces TLB misses, especially on non-PCID systems.
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