mirror of https://gitee.com/openkylin/linux.git
x86: mce: Remove old i386 machine check code
As announced in feature-remove-schedule.txt remove CONFIG_X86_OLD_MCE This patch only removes code. The ancient machine check code for very old systems that are not supported by CONFIG_X86_NEW_MCE is still kept. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Andi Kleen
H. Peter Anvin
parent
bab9bc6583
commit
5bb38adcb5
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@ -444,13 +444,3 @@ What: CONFIG_RFKILL_INPUT
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When: 2.6.33
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Why: Should be implemented in userspace, policy daemon.
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Who: Johannes Berg <johannes@sipsolutions.net>
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----------------------------
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What: CONFIG_X86_OLD_MCE
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When: 2.6.32
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Why: Remove the old legacy 32bit machine check code. This has been
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superseded by the newer machine check code from the 64bit port,
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but the old version has been kept around for easier testing. Note this
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doesn't impact the old P5 and WinChip machine check handlers.
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Who: Andi Kleen <andi@firstfloor.org>
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@ -781,21 +781,10 @@ config X86_MCE
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The action the kernel takes depends on the severity of the problem,
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ranging from warning messages to halting the machine.
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config X86_OLD_MCE
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depends on X86_32 && X86_MCE
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bool "Use legacy machine check code (will go away)"
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default n
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select X86_ANCIENT_MCE
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---help---
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Use the old i386 machine check code. This is merely intended for
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testing in a transition period. Try this if you run into any machine
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check related software problems, but report the problem to
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linux-kernel. When in doubt say no.
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config X86_NEW_MCE
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depends on X86_MCE
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bool
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default y if (!X86_OLD_MCE && X86_32) || X86_64
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default y
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config X86_MCE_INTEL
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def_bool y
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@ -835,29 +824,9 @@ config X86_MCE_INJECT
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If you don't know what a machine check is and you don't do kernel
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QA it is safe to say n.
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config X86_MCE_NONFATAL
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tristate "Check for non-fatal errors on AMD Athlon/Duron / Intel Pentium 4"
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depends on X86_OLD_MCE
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---help---
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Enabling this feature starts a timer that triggers every 5 seconds which
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will look at the machine check registers to see if anything happened.
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Non-fatal problems automatically get corrected (but still logged).
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Disable this if you don't want to see these messages.
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Seeing the messages this option prints out may be indicative of dying
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or out-of-spec (ie, overclocked) hardware.
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This option only does something on certain CPUs.
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(AMD Athlon/Duron and Intel Pentium 4)
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config X86_MCE_P4THERMAL
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bool "check for P4 thermal throttling interrupt."
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depends on X86_OLD_MCE && X86_MCE && (X86_UP_APIC || SMP)
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---help---
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Enabling this feature will cause a message to be printed when the P4
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enters thermal throttling.
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config X86_THERMAL_VECTOR
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def_bool y
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depends on X86_MCE_P4THERMAL || X86_MCE_INTEL
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depends on X86_MCE_INTEL
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config VM86
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bool "Enable VM86 support" if EMBEDDED
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@ -115,13 +115,6 @@ void mcheck_init(struct cpuinfo_x86 *c);
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static inline void mcheck_init(struct cpuinfo_x86 *c) {}
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#endif
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#ifdef CONFIG_X86_OLD_MCE
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extern int nr_mce_banks;
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void amd_mcheck_init(struct cpuinfo_x86 *c);
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void intel_p4_mcheck_init(struct cpuinfo_x86 *c);
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void intel_p6_mcheck_init(struct cpuinfo_x86 *c);
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#endif
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#ifdef CONFIG_X86_ANCIENT_MCE
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
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void winchip_mcheck_init(struct cpuinfo_x86 *c);
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@ -208,11 +201,7 @@ extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
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void intel_init_thermal(struct cpuinfo_x86 *c);
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#ifdef CONFIG_X86_NEW_MCE
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void mce_log_therm_throt_event(__u64 status);
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#else
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static inline void mce_log_therm_throt_event(__u64 status) {}
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_MCE_H */
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@ -1,11 +1,9 @@
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obj-y = mce.o
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obj-$(CONFIG_X86_NEW_MCE) += mce-severity.o
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obj-$(CONFIG_X86_OLD_MCE) += k7.o p4.o p6.o
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obj-$(CONFIG_X86_ANCIENT_MCE) += winchip.o p5.o
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obj-$(CONFIG_X86_MCE_INTEL) += mce_intel.o
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obj-$(CONFIG_X86_MCE_AMD) += mce_amd.o
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obj-$(CONFIG_X86_MCE_NONFATAL) += non-fatal.o
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obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o
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obj-$(CONFIG_X86_MCE_INJECT) += mce-inject.o
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@ -1,116 +0,0 @@
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/*
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* Athlon specific Machine Check Exception Reporting
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* (C) Copyright 2002 Dave Jones <davej@redhat.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/mce.h>
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#include <asm/msr.h>
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/* Machine Check Handler For AMD Athlon/Duron: */
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static void k7_machine_check(struct pt_regs *regs, long error_code)
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{
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u32 alow, ahigh, high, low;
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u32 mcgstl, mcgsth;
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int recover = 1;
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int i;
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rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
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if (mcgstl & (1<<0)) /* Recoverable ? */
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recover = 0;
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printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
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smp_processor_id(), mcgsth, mcgstl);
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for (i = 1; i < nr_mce_banks; i++) {
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rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
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if (high & (1<<31)) {
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char misc[20];
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char addr[24];
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misc[0] = '\0';
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addr[0] = '\0';
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if (high & (1<<29))
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recover |= 1;
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if (high & (1<<25))
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recover |= 2;
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high &= ~(1<<31);
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if (high & (1<<27)) {
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rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
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snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
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}
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if (high & (1<<26)) {
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rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
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snprintf(addr, 24, " at %08x%08x", ahigh, alow);
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}
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printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
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smp_processor_id(), i, high, low, misc, addr);
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/* Clear it: */
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wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
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/* Serialize: */
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wmb();
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add_taint(TAINT_MACHINE_CHECK);
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}
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}
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if (recover & 2)
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panic("CPU context corrupt");
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if (recover & 1)
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panic("Unable to continue");
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printk(KERN_EMERG "Attempting to continue.\n");
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mcgstl &= ~(1<<2);
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wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
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}
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/* AMD K7 machine check is Intel like: */
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void amd_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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int i;
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if (!cpu_has(c, X86_FEATURE_MCE))
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return;
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machine_check_vector = k7_machine_check;
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/* Make sure the vector pointer is visible before we enable MCEs: */
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wmb();
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printk(KERN_INFO "Intel machine check architecture supported.\n");
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rdmsr(MSR_IA32_MCG_CAP, l, h);
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if (l & (1<<8)) /* Control register present ? */
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wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
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nr_mce_banks = l & 0xff;
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/*
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* Clear status for MC index 0 separately, we don't touch CTL,
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* as some K7 Athlons cause spurious MCEs when its enabled:
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*/
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if (boot_cpu_data.x86 == 6) {
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wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0);
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i = 1;
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} else
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i = 0;
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for (; i < nr_mce_banks; i++) {
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wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
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wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
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}
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set_in_cr4(X86_CR4_MCE);
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printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
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smp_processor_id());
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}
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@ -58,8 +58,6 @@ void (*machine_check_vector)(struct pt_regs *, long error_code) =
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int mce_disabled __read_mostly;
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#ifdef CONFIG_X86_NEW_MCE
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#define MISC_MCELOG_MINOR 227
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#define SPINUNIT 100 /* 100ns */
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@ -1993,51 +1991,6 @@ static __init int mce_init_device(void)
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device_initcall(mce_init_device);
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#else /* CONFIG_X86_OLD_MCE: */
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int nr_mce_banks;
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EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */
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/* This has to be run for each processor */
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void mcheck_init(struct cpuinfo_x86 *c)
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{
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if (mce_disabled)
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return;
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switch (c->x86_vendor) {
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case X86_VENDOR_AMD:
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amd_mcheck_init(c);
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break;
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case X86_VENDOR_INTEL:
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if (c->x86 == 5)
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intel_p5_mcheck_init(c);
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if (c->x86 == 6)
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intel_p6_mcheck_init(c);
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if (c->x86 == 15)
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intel_p4_mcheck_init(c);
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break;
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case X86_VENDOR_CENTAUR:
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if (c->x86 == 5)
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winchip_mcheck_init(c);
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break;
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default:
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break;
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}
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printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks);
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}
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static int __init mcheck_enable(char *str)
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{
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mce_p5_enabled = 1;
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return 1;
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}
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__setup("mce", mcheck_enable);
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#endif /* CONFIG_X86_OLD_MCE */
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/*
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* Old style boot options parsing. Only for compatibility.
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*/
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@ -1,94 +0,0 @@
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/*
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* Non Fatal Machine Check Exception Reporting
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*
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* (C) Copyright 2002 Dave Jones. <davej@redhat.com>
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*
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* This file contains routines to check for non-fatal MCEs every 15s
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*
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*/
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#include <linux/interrupt.h>
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#include <linux/workqueue.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/mce.h>
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#include <asm/msr.h>
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static int firstbank;
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#define MCE_RATE (15*HZ) /* timer rate is 15s */
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static void mce_checkregs(void *info)
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{
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u32 low, high;
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int i;
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for (i = firstbank; i < nr_mce_banks; i++) {
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rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
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if (!(high & (1<<31)))
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continue;
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printk(KERN_INFO "MCE: The hardware reports a non fatal, "
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"correctable incident occurred on CPU %d.\n",
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smp_processor_id());
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printk(KERN_INFO "Bank %d: %08x%08x\n", i, high, low);
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/*
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* Scrub the error so we don't pick it up in MCE_RATE
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* seconds time:
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*/
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wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
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/* Serialize: */
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wmb();
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add_taint(TAINT_MACHINE_CHECK);
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}
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}
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static void mce_work_fn(struct work_struct *work);
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static DECLARE_DELAYED_WORK(mce_work, mce_work_fn);
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static void mce_work_fn(struct work_struct *work)
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{
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on_each_cpu(mce_checkregs, NULL, 1);
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schedule_delayed_work(&mce_work, round_jiffies_relative(MCE_RATE));
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}
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static int __init init_nonfatal_mce_checker(void)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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/* Check for MCE support */
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if (!cpu_has(c, X86_FEATURE_MCE))
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return -ENODEV;
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/* Check for PPro style MCA */
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if (!cpu_has(c, X86_FEATURE_MCA))
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return -ENODEV;
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/* Some Athlons misbehave when we frob bank 0 */
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
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boot_cpu_data.x86 == 6)
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firstbank = 1;
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else
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firstbank = 0;
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/*
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* Check for non-fatal errors every MCE_RATE s
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*/
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schedule_delayed_work(&mce_work, round_jiffies_relative(MCE_RATE));
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printk(KERN_INFO "Machine check exception polling timer started.\n");
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return 0;
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}
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module_init(init_nonfatal_mce_checker);
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MODULE_LICENSE("GPL");
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@ -1,163 +0,0 @@
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/*
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* P4 specific Machine Check Exception Reporting
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include <asm/mce.h>
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#include <asm/msr.h>
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/* as supported by the P4/Xeon family */
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struct intel_mce_extended_msrs {
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u32 eax;
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u32 ebx;
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u32 ecx;
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u32 edx;
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u32 esi;
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u32 edi;
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u32 ebp;
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u32 esp;
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u32 eflags;
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u32 eip;
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/* u32 *reserved[]; */
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};
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static int mce_num_extended_msrs;
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/* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */
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static void intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
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{
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u32 h;
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rdmsr(MSR_IA32_MCG_EAX, r->eax, h);
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rdmsr(MSR_IA32_MCG_EBX, r->ebx, h);
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rdmsr(MSR_IA32_MCG_ECX, r->ecx, h);
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rdmsr(MSR_IA32_MCG_EDX, r->edx, h);
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rdmsr(MSR_IA32_MCG_ESI, r->esi, h);
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rdmsr(MSR_IA32_MCG_EDI, r->edi, h);
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rdmsr(MSR_IA32_MCG_EBP, r->ebp, h);
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rdmsr(MSR_IA32_MCG_ESP, r->esp, h);
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rdmsr(MSR_IA32_MCG_EFLAGS, r->eflags, h);
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rdmsr(MSR_IA32_MCG_EIP, r->eip, h);
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}
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static void intel_machine_check(struct pt_regs *regs, long error_code)
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{
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u32 alow, ahigh, high, low;
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u32 mcgstl, mcgsth;
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int recover = 1;
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int i;
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rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
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if (mcgstl & (1<<0)) /* Recoverable ? */
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recover = 0;
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printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
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smp_processor_id(), mcgsth, mcgstl);
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if (mce_num_extended_msrs > 0) {
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struct intel_mce_extended_msrs dbg;
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intel_get_extended_msrs(&dbg);
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printk(KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n"
|
||||
"\teax: %08x ebx: %08x ecx: %08x edx: %08x\n"
|
||||
"\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
|
||||
smp_processor_id(), dbg.eip, dbg.eflags,
|
||||
dbg.eax, dbg.ebx, dbg.ecx, dbg.edx,
|
||||
dbg.esi, dbg.edi, dbg.ebp, dbg.esp);
|
||||
}
|
||||
|
||||
for (i = 0; i < nr_mce_banks; i++) {
|
||||
rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
|
||||
if (high & (1<<31)) {
|
||||
char misc[20];
|
||||
char addr[24];
|
||||
|
||||
misc[0] = addr[0] = '\0';
|
||||
if (high & (1<<29))
|
||||
recover |= 1;
|
||||
if (high & (1<<25))
|
||||
recover |= 2;
|
||||
high &= ~(1<<31);
|
||||
if (high & (1<<27)) {
|
||||
rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
|
||||
snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
|
||||
}
|
||||
if (high & (1<<26)) {
|
||||
rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
|
||||
snprintf(addr, 24, " at %08x%08x", ahigh, alow);
|
||||
}
|
||||
printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
|
||||
smp_processor_id(), i, high, low, misc, addr);
|
||||
}
|
||||
}
|
||||
|
||||
if (recover & 2)
|
||||
panic("CPU context corrupt");
|
||||
if (recover & 1)
|
||||
panic("Unable to continue");
|
||||
|
||||
printk(KERN_EMERG "Attempting to continue.\n");
|
||||
|
||||
/*
|
||||
* Do not clear the MSR_IA32_MCi_STATUS if the error is not
|
||||
* recoverable/continuable.This will allow BIOS to look at the MSRs
|
||||
* for errors if the OS could not log the error.
|
||||
*/
|
||||
for (i = 0; i < nr_mce_banks; i++) {
|
||||
u32 msr;
|
||||
msr = MSR_IA32_MC0_STATUS+i*4;
|
||||
rdmsr(msr, low, high);
|
||||
if (high&(1<<31)) {
|
||||
/* Clear it */
|
||||
wrmsr(msr, 0UL, 0UL);
|
||||
/* Serialize */
|
||||
wmb();
|
||||
add_taint(TAINT_MACHINE_CHECK);
|
||||
}
|
||||
}
|
||||
mcgstl &= ~(1<<2);
|
||||
wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
|
||||
}
|
||||
|
||||
void intel_p4_mcheck_init(struct cpuinfo_x86 *c)
|
||||
{
|
||||
u32 l, h;
|
||||
int i;
|
||||
|
||||
machine_check_vector = intel_machine_check;
|
||||
wmb();
|
||||
|
||||
printk(KERN_INFO "Intel machine check architecture supported.\n");
|
||||
rdmsr(MSR_IA32_MCG_CAP, l, h);
|
||||
if (l & (1<<8)) /* Control register present ? */
|
||||
wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
|
||||
nr_mce_banks = l & 0xff;
|
||||
|
||||
for (i = 0; i < nr_mce_banks; i++) {
|
||||
wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
|
||||
wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
|
||||
}
|
||||
|
||||
set_in_cr4(X86_CR4_MCE);
|
||||
printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
|
||||
smp_processor_id());
|
||||
|
||||
/* Check for P4/Xeon extended MCE MSRs */
|
||||
rdmsr(MSR_IA32_MCG_CAP, l, h);
|
||||
if (l & (1<<9)) {/* MCG_EXT_P */
|
||||
mce_num_extended_msrs = (l >> 16) & 0xff;
|
||||
printk(KERN_INFO "CPU%d: Intel P4/Xeon Extended MCE MSRs (%d)"
|
||||
" available\n",
|
||||
smp_processor_id(), mce_num_extended_msrs);
|
||||
|
||||
#ifdef CONFIG_X86_MCE_P4THERMAL
|
||||
/* Check for P4/Xeon Thermal monitor */
|
||||
intel_init_thermal(c);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
@ -1,127 +0,0 @@
|
|||
/*
|
||||
* P6 specific Machine Check Exception Reporting
|
||||
* (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
|
||||
*/
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/mce.h>
|
||||
#include <asm/msr.h>
|
||||
|
||||
/* Machine Check Handler For PII/PIII */
|
||||
static void intel_machine_check(struct pt_regs *regs, long error_code)
|
||||
{
|
||||
u32 alow, ahigh, high, low;
|
||||
u32 mcgstl, mcgsth;
|
||||
int recover = 1;
|
||||
int i;
|
||||
|
||||
rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
|
||||
if (mcgstl & (1<<0)) /* Recoverable ? */
|
||||
recover = 0;
|
||||
|
||||
printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
|
||||
smp_processor_id(), mcgsth, mcgstl);
|
||||
|
||||
for (i = 0; i < nr_mce_banks; i++) {
|
||||
rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
|
||||
if (high & (1<<31)) {
|
||||
char misc[20];
|
||||
char addr[24];
|
||||
|
||||
misc[0] = '\0';
|
||||
addr[0] = '\0';
|
||||
|
||||
if (high & (1<<29))
|
||||
recover |= 1;
|
||||
if (high & (1<<25))
|
||||
recover |= 2;
|
||||
high &= ~(1<<31);
|
||||
|
||||
if (high & (1<<27)) {
|
||||
rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
|
||||
snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
|
||||
}
|
||||
if (high & (1<<26)) {
|
||||
rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
|
||||
snprintf(addr, 24, " at %08x%08x", ahigh, alow);
|
||||
}
|
||||
|
||||
printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
|
||||
smp_processor_id(), i, high, low, misc, addr);
|
||||
}
|
||||
}
|
||||
|
||||
if (recover & 2)
|
||||
panic("CPU context corrupt");
|
||||
if (recover & 1)
|
||||
panic("Unable to continue");
|
||||
|
||||
printk(KERN_EMERG "Attempting to continue.\n");
|
||||
/*
|
||||
* Do not clear the MSR_IA32_MCi_STATUS if the error is not
|
||||
* recoverable/continuable.This will allow BIOS to look at the MSRs
|
||||
* for errors if the OS could not log the error:
|
||||
*/
|
||||
for (i = 0; i < nr_mce_banks; i++) {
|
||||
unsigned int msr;
|
||||
|
||||
msr = MSR_IA32_MC0_STATUS+i*4;
|
||||
rdmsr(msr, low, high);
|
||||
if (high & (1<<31)) {
|
||||
/* Clear it: */
|
||||
wrmsr(msr, 0UL, 0UL);
|
||||
/* Serialize: */
|
||||
wmb();
|
||||
add_taint(TAINT_MACHINE_CHECK);
|
||||
}
|
||||
}
|
||||
mcgstl &= ~(1<<2);
|
||||
wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
|
||||
}
|
||||
|
||||
/* Set up machine check reporting for processors with Intel style MCE: */
|
||||
void intel_p6_mcheck_init(struct cpuinfo_x86 *c)
|
||||
{
|
||||
u32 l, h;
|
||||
int i;
|
||||
|
||||
/* Check for MCE support */
|
||||
if (!cpu_has(c, X86_FEATURE_MCE))
|
||||
return;
|
||||
|
||||
/* Check for PPro style MCA */
|
||||
if (!cpu_has(c, X86_FEATURE_MCA))
|
||||
return;
|
||||
|
||||
/* Ok machine check is available */
|
||||
machine_check_vector = intel_machine_check;
|
||||
/* Make sure the vector pointer is visible before we enable MCEs: */
|
||||
wmb();
|
||||
|
||||
printk(KERN_INFO "Intel machine check architecture supported.\n");
|
||||
rdmsr(MSR_IA32_MCG_CAP, l, h);
|
||||
if (l & (1<<8)) /* Control register present ? */
|
||||
wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
|
||||
nr_mce_banks = l & 0xff;
|
||||
|
||||
/*
|
||||
* Following the example in IA-32 SDM Vol 3:
|
||||
* - MC0_CTL should not be written
|
||||
* - Status registers on all banks should be cleared on reset
|
||||
*/
|
||||
for (i = 1; i < nr_mce_banks; i++)
|
||||
wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
|
||||
|
||||
for (i = 0; i < nr_mce_banks; i++)
|
||||
wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
|
||||
|
||||
set_in_cr4(X86_CR4_MCE);
|
||||
printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
|
||||
smp_processor_id());
|
||||
}
|
||||
Loading…
Reference in New Issue