mirror of https://gitee.com/openkylin/linux.git
Merge branch 'master' of ssh://master.kernel.org/pub/scm/linux/kernel/git/mchehab/v4l-dvb
* 'master' of ssh://master.kernel.org/pub/scm/linux/kernel/git/mchehab/v4l-dvb: V4L/DVB (5496): Pluto2: fix incorrect TSCR register setting V4L/DVB (5495): Tda10086: fix DiSEqC message length
This commit is contained in:
commit
5c0efdbc1b
|
@ -212,7 +212,7 @@ static int tda10086_send_master_cmd (struct dvb_frontend* fe,
|
|||
for(i=0; i< cmd->msg_len; i++) {
|
||||
tda10086_write_byte(state, 0x48+i, cmd->msg[i]);
|
||||
}
|
||||
tda10086_write_byte(state, 0x36, 0x08 | ((cmd->msg_len + 1) << 4));
|
||||
tda10086_write_byte(state, 0x36, 0x08 | ((cmd->msg_len - 1) << 4));
|
||||
|
||||
tda10086_diseqc_wait(state);
|
||||
|
||||
|
|
|
@ -149,6 +149,15 @@ static inline void pluto_rw(struct pluto *pluto, u32 reg, u32 mask, u32 bits)
|
|||
writel(val, &pluto->io_mem[reg]);
|
||||
}
|
||||
|
||||
static void pluto_write_tscr(struct pluto *pluto, u32 val)
|
||||
{
|
||||
/* set the number of packets */
|
||||
val &= ~TSCR_ADEF;
|
||||
val |= TS_DMA_PACKETS / 2;
|
||||
|
||||
pluto_writereg(pluto, REG_TSCR, val);
|
||||
}
|
||||
|
||||
static void pluto_setsda(void *data, int state)
|
||||
{
|
||||
struct pluto *pluto = data;
|
||||
|
@ -213,11 +222,11 @@ static void pluto_reset_ts(struct pluto *pluto, int reenable)
|
|||
|
||||
if (val & TSCR_RSTN) {
|
||||
val &= ~TSCR_RSTN;
|
||||
pluto_writereg(pluto, REG_TSCR, val);
|
||||
pluto_write_tscr(pluto, val);
|
||||
}
|
||||
if (reenable) {
|
||||
val |= TSCR_RSTN;
|
||||
pluto_writereg(pluto, REG_TSCR, val);
|
||||
pluto_write_tscr(pluto, val);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -339,7 +348,7 @@ static irqreturn_t pluto_irq(int irq, void *dev_id)
|
|||
}
|
||||
|
||||
/* ACK the interrupt */
|
||||
pluto_writereg(pluto, REG_TSCR, tscr | TSCR_IACK);
|
||||
pluto_write_tscr(pluto, tscr | TSCR_IACK);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
@ -348,9 +357,6 @@ static void __devinit pluto_enable_irqs(struct pluto *pluto)
|
|||
{
|
||||
u32 val = pluto_readreg(pluto, REG_TSCR);
|
||||
|
||||
/* set the number of packets */
|
||||
val &= ~TSCR_ADEF;
|
||||
val |= TS_DMA_PACKETS / 2;
|
||||
/* disable AFUL and LOCK interrupts */
|
||||
val |= (TSCR_MSKA | TSCR_MSKL);
|
||||
/* enable DMA and OVERFLOW interrupts */
|
||||
|
@ -358,7 +364,7 @@ static void __devinit pluto_enable_irqs(struct pluto *pluto)
|
|||
/* clear pending interrupts */
|
||||
val |= TSCR_IACK;
|
||||
|
||||
pluto_writereg(pluto, REG_TSCR, val);
|
||||
pluto_write_tscr(pluto, val);
|
||||
}
|
||||
|
||||
static void pluto_disable_irqs(struct pluto *pluto)
|
||||
|
@ -370,7 +376,7 @@ static void pluto_disable_irqs(struct pluto *pluto)
|
|||
/* clear pending interrupts */
|
||||
val |= TSCR_IACK;
|
||||
|
||||
pluto_writereg(pluto, REG_TSCR, val);
|
||||
pluto_write_tscr(pluto, val);
|
||||
}
|
||||
|
||||
static int __devinit pluto_hw_init(struct pluto *pluto)
|
||||
|
|
Loading…
Reference in New Issue