mirror of https://gitee.com/openkylin/linux.git
Merge branch 'master' of ssh://master.kernel.org/pub/scm/linux/kernel/git/mchehab/v4l-dvb
* 'master' of ssh://master.kernel.org/pub/scm/linux/kernel/git/mchehab/v4l-dvb: V4L/DVB (5496): Pluto2: fix incorrect TSCR register setting V4L/DVB (5495): Tda10086: fix DiSEqC message length
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commit
5c0efdbc1b
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@ -212,7 +212,7 @@ static int tda10086_send_master_cmd (struct dvb_frontend* fe,
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for(i=0; i< cmd->msg_len; i++) {
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for(i=0; i< cmd->msg_len; i++) {
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tda10086_write_byte(state, 0x48+i, cmd->msg[i]);
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tda10086_write_byte(state, 0x48+i, cmd->msg[i]);
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}
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}
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tda10086_write_byte(state, 0x36, 0x08 | ((cmd->msg_len + 1) << 4));
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tda10086_write_byte(state, 0x36, 0x08 | ((cmd->msg_len - 1) << 4));
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tda10086_diseqc_wait(state);
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tda10086_diseqc_wait(state);
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@ -149,6 +149,15 @@ static inline void pluto_rw(struct pluto *pluto, u32 reg, u32 mask, u32 bits)
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writel(val, &pluto->io_mem[reg]);
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writel(val, &pluto->io_mem[reg]);
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}
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}
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static void pluto_write_tscr(struct pluto *pluto, u32 val)
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{
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/* set the number of packets */
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val &= ~TSCR_ADEF;
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val |= TS_DMA_PACKETS / 2;
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pluto_writereg(pluto, REG_TSCR, val);
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}
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static void pluto_setsda(void *data, int state)
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static void pluto_setsda(void *data, int state)
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{
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{
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struct pluto *pluto = data;
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struct pluto *pluto = data;
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@ -213,11 +222,11 @@ static void pluto_reset_ts(struct pluto *pluto, int reenable)
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if (val & TSCR_RSTN) {
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if (val & TSCR_RSTN) {
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val &= ~TSCR_RSTN;
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val &= ~TSCR_RSTN;
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pluto_writereg(pluto, REG_TSCR, val);
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pluto_write_tscr(pluto, val);
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}
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}
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if (reenable) {
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if (reenable) {
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val |= TSCR_RSTN;
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val |= TSCR_RSTN;
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pluto_writereg(pluto, REG_TSCR, val);
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pluto_write_tscr(pluto, val);
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}
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}
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}
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}
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@ -339,7 +348,7 @@ static irqreturn_t pluto_irq(int irq, void *dev_id)
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}
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}
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/* ACK the interrupt */
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/* ACK the interrupt */
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pluto_writereg(pluto, REG_TSCR, tscr | TSCR_IACK);
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pluto_write_tscr(pluto, tscr | TSCR_IACK);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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@ -348,9 +357,6 @@ static void __devinit pluto_enable_irqs(struct pluto *pluto)
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{
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{
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u32 val = pluto_readreg(pluto, REG_TSCR);
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u32 val = pluto_readreg(pluto, REG_TSCR);
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/* set the number of packets */
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val &= ~TSCR_ADEF;
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val |= TS_DMA_PACKETS / 2;
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/* disable AFUL and LOCK interrupts */
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/* disable AFUL and LOCK interrupts */
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val |= (TSCR_MSKA | TSCR_MSKL);
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val |= (TSCR_MSKA | TSCR_MSKL);
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/* enable DMA and OVERFLOW interrupts */
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/* enable DMA and OVERFLOW interrupts */
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@ -358,7 +364,7 @@ static void __devinit pluto_enable_irqs(struct pluto *pluto)
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/* clear pending interrupts */
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/* clear pending interrupts */
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val |= TSCR_IACK;
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val |= TSCR_IACK;
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pluto_writereg(pluto, REG_TSCR, val);
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pluto_write_tscr(pluto, val);
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}
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}
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static void pluto_disable_irqs(struct pluto *pluto)
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static void pluto_disable_irqs(struct pluto *pluto)
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@ -370,7 +376,7 @@ static void pluto_disable_irqs(struct pluto *pluto)
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/* clear pending interrupts */
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/* clear pending interrupts */
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val |= TSCR_IACK;
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val |= TSCR_IACK;
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pluto_writereg(pluto, REG_TSCR, val);
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pluto_write_tscr(pluto, val);
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}
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}
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static int __devinit pluto_hw_init(struct pluto *pluto)
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static int __devinit pluto_hw_init(struct pluto *pluto)
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