mirror of https://gitee.com/openkylin/linux.git
staging: dgnc: cls.c: removes trailing whitespace
This patch removes trailing whitespace in the dgnc_cls.c file. Signed-off-by: Lidza Louina <lidza.louina@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Lidza Louina
Greg Kroah-Hartman
parent
53c55fa228
commit
5ca46fd4c8
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@ -6,12 +6,12 @@
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
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* implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
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* implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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@ -111,7 +111,7 @@ static inline void cls_set_cts_flow_control(struct channel_t *ch)
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn on CTS flow control, turn off IXON flow control */
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isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
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isr_fcr &= ~(UART_EXAR654_EFR_IXON);
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@ -153,7 +153,7 @@ static inline void cls_set_ixon_flow_control(struct channel_t *ch)
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn on IXON flow control, turn off CTS flow control */
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isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
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isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
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@ -199,7 +199,7 @@ static inline void cls_set_no_output_flow_control(struct channel_t *ch)
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn off IXON flow control, turn off CTS flow control */
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isr_fcr |= (UART_EXAR654_EFR_ECB);
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isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
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@ -243,7 +243,7 @@ static inline void cls_set_rts_flow_control(struct channel_t *ch)
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn on RTS flow control, turn off IXOFF flow control */
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isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
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isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
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@ -286,7 +286,7 @@ static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn on IXOFF flow control, turn off RTS flow control */
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isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
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isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
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@ -331,7 +331,7 @@ static inline void cls_set_no_input_flow_control(struct channel_t *ch)
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn off IXOFF flow control, turn off RTS flow control */
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isr_fcr |= (UART_EXAR654_EFR_ECB);
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isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
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@ -492,7 +492,7 @@ static void cls_param(struct tty_struct *tty)
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return;
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}
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ch = un->un_ch;
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ch = un->un_ch;
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if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
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return;
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}
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@ -581,7 +581,7 @@ static void cls_param(struct tty_struct *tty)
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jindex = baud;
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if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16)) {
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baud = bauds[iindex][jindex];
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baud = bauds[iindex][jindex];
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} else {
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DPR_IOCTL(("baud indices were out of range (%d)(%d)",
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iindex, jindex));
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@ -620,7 +620,7 @@ static void cls_param(struct tty_struct *tty)
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*/
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#ifdef CMSPAR
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if (ch->ch_c_cflag & CMSPAR)
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lcr |= UART_LCR_SPAR;
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lcr |= UART_LCR_SPAR;
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#endif
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if (ch->ch_c_cflag & CSTOPB)
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@ -663,7 +663,7 @@ static void cls_param(struct tty_struct *tty)
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if (ch->ch_c_cflag & CREAD) {
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ier |= (UART_IER_RDI | UART_IER_RLSI);
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}
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}
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else {
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ier &= ~(UART_IER_RDI | UART_IER_RLSI);
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}
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@ -710,7 +710,7 @@ static void cls_param(struct tty_struct *tty)
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cls_set_no_input_flow_control(ch);
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else
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cls_set_ixoff_flow_control(ch);
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}
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}
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else {
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cls_set_no_input_flow_control(ch);
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}
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@ -827,7 +827,7 @@ static irqreturn_t cls_intr(int irq, void *voidbrd)
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brd->intr_count++;
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/*
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* Check the board's global interrupt offset to see if we
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* Check the board's global interrupt offset to see if we
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* we actually do have an interrupt pending for us.
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*/
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poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
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@ -986,7 +986,7 @@ static int cls_drain(struct tty_struct *tty, uint seconds)
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return (-ENXIO);
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}
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ch = un->un_ch;
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ch = un->un_ch;
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if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
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return (-ENXIO);
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}
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@ -1006,7 +1006,7 @@ static int cls_drain(struct tty_struct *tty, uint seconds)
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return (rc);
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}
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/* Channel lock MUST be held before calling this function! */
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static void cls_flush_uart_write(struct channel_t *ch)
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@ -1032,7 +1032,7 @@ static void cls_flush_uart_read(struct channel_t *ch)
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/*
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* For complete POSIX compatibility, we should be purging the
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* read FIFO in the UART here.
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*
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*
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* However, doing the statement below also incorrectly flushes
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* write data as well as just basically trashing the FIFO.
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*
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@ -1163,7 +1163,7 @@ static void cls_parse_modem(struct channel_t *ch, uchar signals)
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msignals |= UART_MSR_DCD;
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}
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}
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/* Scrub off lower bits. They signify delta's, which I don't care about */
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signals &= 0xf0;
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@ -1192,8 +1192,8 @@ static void cls_parse_modem(struct channel_t *ch, uchar signals)
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ch->ch_portnum,
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!!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
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!!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
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!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
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!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
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!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
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!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
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!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
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!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)));
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}
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@ -1258,7 +1258,7 @@ static void cls_uart_init(struct channel_t *ch)
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
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/* Turn on Enhanced/Extended controls */
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isr_fcr |= (UART_EXAR654_EFR_ECB);
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@ -1380,7 +1380,7 @@ static void cls_send_immediate_char(struct channel_t *ch, unsigned char c)
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writeb(c, &ch->ch_cls_uart->txrx);
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}
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static void cls_vpd(struct board_t *brd)
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static void cls_vpd(struct board_t *brd)
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{
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ulong vpdbase; /* Start of io base of the card */
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uchar *re_map_vpdbase;/* Remapped memory of the card */
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