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sata_nv: enable hotplug interrupt and fix some readl/readw mismatches 

We already have code that handles hotplug interrupt indications in ADMA
mode, this turns on the control flag that actually enables these interrupts.
Also fixes some cases in the same functions where a 16-bit register was read
using a readl instead of a readw.

Signed-off-by: Robert Hancock <hancockr@shaw.ca>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Robert Hancock 2007-02-19 19:03:27 -06:00 committed by Jeff Garzik
parent 721449bf0d
commit 5ce0cf6faf
1 changed files with 10 additions and 8 deletions
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18
drivers/ata/sata_nv.c
View File

@ -1034,14 +1034,15 @@ static int nv_adma_port_start(struct ata_port *ap)
/* clear GO for register mode, enable interrupt */ /* clear GO for register mode, enable interrupt */
tmp = readw(mmio + NV_ADMA_CTL); tmp = readw(mmio + NV_ADMA_CTL);
writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN, mmio + NV_ADMA_CTL); writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
tmp = readw(mmio + NV_ADMA_CTL); tmp = readw(mmio + NV_ADMA_CTL);
writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
readl( mmio + NV_ADMA_CTL ); /* flush posted write */ readw( mmio + NV_ADMA_CTL ); /* flush posted write */
udelay(1); udelay(1);
writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
readl( mmio + NV_ADMA_CTL ); /* flush posted write */ readw( mmio + NV_ADMA_CTL ); /* flush posted write */
return 0; return 0;
} }
@ -1093,14 +1094,15 @@ static int nv_adma_port_resume(struct ata_port *ap)
/* clear GO for register mode, enable interrupt */ /* clear GO for register mode, enable interrupt */
tmp = readw(mmio + NV_ADMA_CTL); tmp = readw(mmio + NV_ADMA_CTL);
writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN, mmio + NV_ADMA_CTL); writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
tmp = readw(mmio + NV_ADMA_CTL); tmp = readw(mmio + NV_ADMA_CTL);
writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
readl( mmio + NV_ADMA_CTL ); /* flush posted write */ readw( mmio + NV_ADMA_CTL ); /* flush posted write */
udelay(1); udelay(1);
writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
readl( mmio + NV_ADMA_CTL ); /* flush posted write */ readw( mmio + NV_ADMA_CTL ); /* flush posted write */
return 0; return 0;
} }
@ -1491,10 +1493,10 @@ static void nv_adma_error_handler(struct ata_port *ap)
/* Reset channel */ /* Reset channel */
tmp = readw(mmio + NV_ADMA_CTL); tmp = readw(mmio + NV_ADMA_CTL);
writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
readl( mmio + NV_ADMA_CTL ); /* flush posted write */ readw( mmio + NV_ADMA_CTL ); /* flush posted write */
udelay(1); udelay(1);
writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
readl( mmio + NV_ADMA_CTL ); /* flush posted write */ readw( mmio + NV_ADMA_CTL ); /* flush posted write */
} }
ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,