mirror of https://gitee.com/openkylin/linux.git
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (24 commits) [POWERPC] Convert the cell IOMMU fixed mapping to 16M IOMMU pages [POWERPC] Allow for different IOMMU page sizes in cell IOMMU code [POWERPC] Cell IOMMU: n_pte_pages is in 4K page units, not IOMMU_PAGE_SIZE [POWERPC] Split setup of IOMMU stab and ptab, allocate dynamic/fixed ptabs separately [POWERPC] Move allocation of cell IOMMU pad page [POWERPC] Remove unused pte_offset variable [POWERPC] Use it_offset not pte_offset in cell IOMMU code [POWERPC] Clearup cell IOMMU fixed mapping terminology [POWERPC] enable hardware watchpoints on cell blades [POWERPC] move celleb DABRX definitions [POWERPC] OProfile: enable callgraph support for Cell [POWERPC] spufs: fix use time accounting on SPE-overcommit [POWERPC] spufs: serialize SLB invalidation against SLB loading [POWERPC] spufs: invalidate SLB translation before adding a new entry [POWERPC] spufs: synchronize IRQ when disabling [POWERPC] spufs: fix order of sputrace thread IDs [POWERPC] Xilinx: hwicap cleanup [POWERPC] 4xx: Use correct board info structure in cuboot wrappers [POWERPC] spufs: fix invalid scheduling of forgotten contexts [POWERPC] 44x: add missing define TARGET_4xx and TARGET_440GX to cuboot-taishan ...
This commit is contained in:
Linus Torvalds
commit
5ce6386b90
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@ -17,6 +17,7 @@
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#include "44x.h"
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#include "cuboot.h"
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#define TARGET_4xx
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#define TARGET_44x
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#include "ppcboot.h"
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@ -17,6 +17,7 @@
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#include "44x.h"
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#include "cuboot.h"
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#define TARGET_4xx
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#define TARGET_44x
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#include "ppcboot.h"
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@ -22,6 +22,7 @@
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#include "44x.h"
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#include "cuboot.h"
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#define TARGET_4xx
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#define TARGET_44x
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#include "ppcboot.h"
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@ -21,7 +21,9 @@
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#include "dcr.h"
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#include "4xx.h"
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#define TARGET_4xx
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#define TARGET_44x
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#define TARGET_440GX
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#include "ppcboot.h"
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static bd_t bd;
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@ -11,6 +11,7 @@
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#include "4xx.h"
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#include "cuboot.h"
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#define TARGET_4xx
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#define TARGET_44x
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#include "ppcboot.h"
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@ -235,7 +235,7 @@ PCIE0: pciex@0a0000000 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-405exr", "ibm,plb-pciex";
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compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
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primary;
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port = <0>; /* port number */
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reg = <a0000000 20000000 /* Config space access */
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@ -38,8 +38,8 @@ cpu@0 {
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timebase-frequency = <0>; /* Filled in by zImage */
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i-cache-line-size = <20>;
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d-cache-line-size = <20>;
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i-cache-size = <20000>;
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d-cache-size = <20000>;
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i-cache-size = <8000>;
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d-cache-size = <8000>;
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dcr-controller;
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dcr-access-method = "native";
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};
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@ -136,11 +136,11 @@ MAL0: mcmal {
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};
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POB0: opb {
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compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
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compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <00000000 4 e0000000 20000000>;
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clock-frequency = <0>; /* Filled in by zImage */
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ranges = <00000000 4 e0000000 20000000>;
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clock-frequency = <0>; /* Filled in by zImage */
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EBC0: ebc {
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compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
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@ -153,38 +153,38 @@ EBC0: ebc {
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};
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UART0: serial@10000200 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <10000200 8>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <10000200 8>;
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virtual-reg = <a0000200>;
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clock-frequency = <0>; /* Filled in by zImage */
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current-speed = <1c200>;
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interrupt-parent = <&UIC0>;
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interrupts = <0 4>;
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};
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clock-frequency = <0>; /* Filled in by zImage */
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current-speed = <1c200>;
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interrupt-parent = <&UIC0>;
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interrupts = <0 4>;
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};
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UART1: serial@10000300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <10000300 8>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <10000300 8>;
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virtual-reg = <a0000300>;
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clock-frequency = <0>;
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current-speed = <0>;
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interrupt-parent = <&UIC0>;
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interrupts = <1 4>;
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};
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clock-frequency = <0>;
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current-speed = <0>;
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interrupt-parent = <&UIC0>;
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interrupts = <1 4>;
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};
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UART2: serial@10000600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <10000600 8>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <10000600 8>;
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virtual-reg = <a0000600>;
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clock-frequency = <0>;
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current-speed = <0>;
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interrupt-parent = <&UIC1>;
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interrupts = <5 4>;
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};
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clock-frequency = <0>;
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current-speed = <0>;
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interrupt-parent = <&UIC1>;
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interrupts = <5 4>;
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};
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IIC0: i2c@10000400 {
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compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
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@ -1151,7 +1151,7 @@ static void cell_handle_interrupt(struct pt_regs *regs,
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for (i = 0; i < num_counters; ++i) {
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if ((interrupt_mask & CBE_PM_CTR_OVERFLOW_INTR(i))
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&& ctr[i].enabled) {
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oprofile_add_pc(pc, is_kernel, i);
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oprofile_add_ext_sample(pc, regs, i, is_kernel);
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cbe_write_ctr(cpu, i, reset_value[i]);
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}
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}
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@ -199,6 +199,7 @@ int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
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return 0;
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}
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EXPORT_SYMBOL(mpc52xx_set_psc_clkdiv);
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/**
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* mpc52xx_restart: ppc_md->restart hook for mpc5200 using the watchdog timer
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@ -113,7 +113,7 @@
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/* IOMMU sizing */
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#define IO_SEGMENT_SHIFT 28
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#define IO_PAGENO_BITS (IO_SEGMENT_SHIFT - IOMMU_PAGE_SHIFT)
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#define IO_PAGENO_BITS(shift) (IO_SEGMENT_SHIFT - (shift))
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/* The high bit needs to be set on every DMA address */
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#define SPIDER_DMA_OFFSET 0x80000000ul
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@ -123,7 +123,6 @@ struct iommu_window {
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struct cbe_iommu *iommu;
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unsigned long offset;
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unsigned long size;
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unsigned long pte_offset;
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unsigned int ioid;
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struct iommu_table table;
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};
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@ -200,7 +199,7 @@ static void tce_build_cell(struct iommu_table *tbl, long index, long npages,
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(window->ioid & IOPTE_IOID_Mask);
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#endif
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io_pte = (unsigned long *)tbl->it_base + (index - window->pte_offset);
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io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
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for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE)
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io_pte[i] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask);
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@ -232,7 +231,7 @@ static void tce_free_cell(struct iommu_table *tbl, long index, long npages)
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| (window->ioid & IOPTE_IOID_Mask);
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#endif
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io_pte = (unsigned long *)tbl->it_base + (index - window->pte_offset);
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io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
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for (i = 0; i < npages; i++)
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io_pte[i] = pte;
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@ -307,76 +306,84 @@ static int cell_iommu_find_ioc(int nid, unsigned long *base)
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return -ENODEV;
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}
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static void cell_iommu_setup_page_tables(struct cbe_iommu *iommu,
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static void cell_iommu_setup_stab(struct cbe_iommu *iommu,
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unsigned long dbase, unsigned long dsize,
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unsigned long fbase, unsigned long fsize)
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{
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struct page *page;
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int i;
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unsigned long reg, segments, pages_per_segment, ptab_size, stab_size,
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n_pte_pages, base;
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base = dbase;
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if (fsize != 0)
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base = min(fbase, dbase);
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unsigned long segments, stab_size;
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segments = max(dbase + dsize, fbase + fsize) >> IO_SEGMENT_SHIFT;
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pages_per_segment = 1ull << IO_PAGENO_BITS;
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pr_debug("%s: iommu[%d]: segments: %lu, pages per segment: %lu\n",
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__FUNCTION__, iommu->nid, segments, pages_per_segment);
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pr_debug("%s: iommu[%d]: segments: %lu\n",
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__FUNCTION__, iommu->nid, segments);
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/* set up the segment table */
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stab_size = segments * sizeof(unsigned long);
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page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(stab_size));
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BUG_ON(!page);
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iommu->stab = page_address(page);
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clear_page(iommu->stab);
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memset(iommu->stab, 0, stab_size);
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}
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static unsigned long *cell_iommu_alloc_ptab(struct cbe_iommu *iommu,
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unsigned long base, unsigned long size, unsigned long gap_base,
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unsigned long gap_size, unsigned long page_shift)
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{
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struct page *page;
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int i;
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unsigned long reg, segments, pages_per_segment, ptab_size,
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n_pte_pages, start_seg, *ptab;
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start_seg = base >> IO_SEGMENT_SHIFT;
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segments = size >> IO_SEGMENT_SHIFT;
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pages_per_segment = 1ull << IO_PAGENO_BITS(page_shift);
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/* PTEs for each segment must start on a 4K bounday */
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pages_per_segment = max(pages_per_segment,
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(1 << 12) / sizeof(unsigned long));
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/* ... and the page tables. Since these are contiguous, we can treat
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* the page tables as one array of ptes, like pSeries does.
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*/
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ptab_size = segments * pages_per_segment * sizeof(unsigned long);
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pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __FUNCTION__,
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iommu->nid, ptab_size, get_order(ptab_size));
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page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size));
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BUG_ON(!page);
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iommu->ptab = page_address(page);
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memset(iommu->ptab, 0, ptab_size);
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ptab = page_address(page);
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memset(ptab, 0, ptab_size);
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|
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/* allocate a bogus page for the end of each mapping */
|
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page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0);
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BUG_ON(!page);
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iommu->pad_page = page_address(page);
|
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clear_page(iommu->pad_page);
|
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|
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/* number of pages needed for a page table */
|
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n_pte_pages = (pages_per_segment *
|
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sizeof(unsigned long)) >> IOMMU_PAGE_SHIFT;
|
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/* number of 4K pages needed for a page table */
|
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n_pte_pages = (pages_per_segment * sizeof(unsigned long)) >> 12;
|
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|
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pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n",
|
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__FUNCTION__, iommu->nid, iommu->stab, iommu->ptab,
|
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__FUNCTION__, iommu->nid, iommu->stab, ptab,
|
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n_pte_pages);
|
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|
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/* initialise the STEs */
|
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reg = IOSTE_V | ((n_pte_pages - 1) << 5);
|
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|
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if (IOMMU_PAGE_SIZE == 0x1000)
|
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reg |= IOSTE_PS_4K;
|
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else if (IOMMU_PAGE_SIZE == 0x10000)
|
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reg |= IOSTE_PS_64K;
|
||||
else {
|
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extern void __unknown_page_size_error(void);
|
||||
__unknown_page_size_error();
|
||||
switch (page_shift) {
|
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case 12: reg |= IOSTE_PS_4K; break;
|
||||
case 16: reg |= IOSTE_PS_64K; break;
|
||||
case 20: reg |= IOSTE_PS_1M; break;
|
||||
case 24: reg |= IOSTE_PS_16M; break;
|
||||
default: BUG();
|
||||
}
|
||||
|
||||
gap_base = gap_base >> IO_SEGMENT_SHIFT;
|
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gap_size = gap_size >> IO_SEGMENT_SHIFT;
|
||||
|
||||
pr_debug("Setting up IOMMU stab:\n");
|
||||
for (i = base >> IO_SEGMENT_SHIFT; i < segments; i++) {
|
||||
iommu->stab[i] = reg |
|
||||
(__pa(iommu->ptab) + n_pte_pages * IOMMU_PAGE_SIZE * i);
|
||||
for (i = start_seg; i < (start_seg + segments); i++) {
|
||||
if (i >= gap_base && i < (gap_base + gap_size)) {
|
||||
pr_debug("\toverlap at %d, skipping\n", i);
|
||||
continue;
|
||||
}
|
||||
iommu->stab[i] = reg | (__pa(ptab) + (n_pte_pages << 12) *
|
||||
(i - start_seg));
|
||||
pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]);
|
||||
}
|
||||
|
||||
return ptab;
|
||||
}
|
||||
|
||||
static void cell_iommu_enable_hardware(struct cbe_iommu *iommu)
|
||||
|
|
@ -423,7 +430,9 @@ static void cell_iommu_enable_hardware(struct cbe_iommu *iommu)
|
|||
static void cell_iommu_setup_hardware(struct cbe_iommu *iommu,
|
||||
unsigned long base, unsigned long size)
|
||||
{
|
||||
cell_iommu_setup_page_tables(iommu, base, size, 0, 0);
|
||||
cell_iommu_setup_stab(iommu, base, size, 0, 0);
|
||||
iommu->ptab = cell_iommu_alloc_ptab(iommu, base, size, 0, 0,
|
||||
IOMMU_PAGE_SHIFT);
|
||||
cell_iommu_enable_hardware(iommu);
|
||||
}
|
||||
|
||||
|
|
@ -464,6 +473,7 @@ cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
|
|||
unsigned long pte_offset)
|
||||
{
|
||||
struct iommu_window *window;
|
||||
struct page *page;
|
||||
u32 ioid;
|
||||
|
||||
ioid = cell_iommu_get_ioid(np);
|
||||
|
|
@ -475,13 +485,11 @@ cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
|
|||
window->size = size;
|
||||
window->ioid = ioid;
|
||||
window->iommu = iommu;
|
||||
window->pte_offset = pte_offset;
|
||||
|
||||
window->table.it_blocksize = 16;
|
||||
window->table.it_base = (unsigned long)iommu->ptab;
|
||||
window->table.it_index = iommu->nid;
|
||||
window->table.it_offset = (offset >> IOMMU_PAGE_SHIFT) +
|
||||
window->pte_offset;
|
||||
window->table.it_offset = (offset >> IOMMU_PAGE_SHIFT) + pte_offset;
|
||||
window->table.it_size = size >> IOMMU_PAGE_SHIFT;
|
||||
|
||||
iommu_init_table(&window->table, iommu->nid);
|
||||
|
|
@ -504,6 +512,11 @@ cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
|
|||
* This code also assumes that we have a window that starts at 0,
|
||||
* which is the case on all spider based blades.
|
||||
*/
|
||||
page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0);
|
||||
BUG_ON(!page);
|
||||
iommu->pad_page = page_address(page);
|
||||
clear_page(iommu->pad_page);
|
||||
|
||||
__set_bit(0, window->table.it_map);
|
||||
tce_build_cell(&window->table, window->table.it_offset, 1,
|
||||
(unsigned long)iommu->pad_page, DMA_TO_DEVICE);
|
||||
|
|
@ -549,7 +562,7 @@ static void cell_dma_dev_setup_iommu(struct device *dev)
|
|||
archdata->dma_data = &window->table;
|
||||
}
|
||||
|
||||
static void cell_dma_dev_setup_static(struct device *dev);
|
||||
static void cell_dma_dev_setup_fixed(struct device *dev);
|
||||
|
||||
static void cell_dma_dev_setup(struct device *dev)
|
||||
{
|
||||
|
|
@ -557,7 +570,7 @@ static void cell_dma_dev_setup(struct device *dev)
|
|||
|
||||
/* Order is important here, these are not mutually exclusive */
|
||||
if (get_dma_ops(dev) == &dma_iommu_fixed_ops)
|
||||
cell_dma_dev_setup_static(dev);
|
||||
cell_dma_dev_setup_fixed(dev);
|
||||
else if (get_pci_dma_ops() == &dma_iommu_ops)
|
||||
cell_dma_dev_setup_iommu(dev);
|
||||
else if (get_pci_dma_ops() == &dma_direct_ops)
|
||||
|
|
@ -858,7 +871,7 @@ static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void cell_dma_dev_setup_static(struct device *dev)
|
||||
static void cell_dma_dev_setup_fixed(struct device *dev)
|
||||
{
|
||||
struct dev_archdata *archdata = &dev->archdata;
|
||||
u64 addr;
|
||||
|
|
@ -869,35 +882,45 @@ static void cell_dma_dev_setup_static(struct device *dev)
|
|||
dev_dbg(dev, "iommu: fixed addr = %lx\n", addr);
|
||||
}
|
||||
|
||||
static void insert_16M_pte(unsigned long addr, unsigned long *ptab,
|
||||
unsigned long base_pte)
|
||||
{
|
||||
unsigned long segment, offset;
|
||||
|
||||
segment = addr >> IO_SEGMENT_SHIFT;
|
||||
offset = (addr >> 24) - (segment << IO_PAGENO_BITS(24));
|
||||
ptab = ptab + (segment * (1 << 12) / sizeof(unsigned long));
|
||||
|
||||
pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n",
|
||||
addr, ptab, segment, offset);
|
||||
|
||||
ptab[offset] = base_pte | (__pa(addr) & IOPTE_RPN_Mask);
|
||||
}
|
||||
|
||||
static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu,
|
||||
struct device_node *np, unsigned long dbase, unsigned long dsize,
|
||||
unsigned long fbase, unsigned long fsize)
|
||||
{
|
||||
unsigned long base_pte, uaddr, *io_pte;
|
||||
int i;
|
||||
unsigned long base_pte, uaddr, ioaddr, *ptab;
|
||||
|
||||
ptab = cell_iommu_alloc_ptab(iommu, fbase, fsize, dbase, dsize, 24);
|
||||
|
||||
dma_iommu_fixed_base = fbase;
|
||||
|
||||
/* convert from bytes into page table indices */
|
||||
dbase = dbase >> IOMMU_PAGE_SHIFT;
|
||||
dsize = dsize >> IOMMU_PAGE_SHIFT;
|
||||
fbase = fbase >> IOMMU_PAGE_SHIFT;
|
||||
fsize = fsize >> IOMMU_PAGE_SHIFT;
|
||||
|
||||
pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase);
|
||||
|
||||
io_pte = iommu->ptab;
|
||||
base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW
|
||||
| (cell_iommu_get_ioid(np) & IOPTE_IOID_Mask);
|
||||
|
||||
uaddr = 0;
|
||||
for (i = fbase; i < fbase + fsize; i++, uaddr += IOMMU_PAGE_SIZE) {
|
||||
for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) {
|
||||
/* Don't touch the dynamic region */
|
||||
if (i >= dbase && i < (dbase + dsize)) {
|
||||
pr_debug("iommu: static/dynamic overlap, skipping\n");
|
||||
ioaddr = uaddr + fbase;
|
||||
if (ioaddr >= dbase && ioaddr < (dbase + dsize)) {
|
||||
pr_debug("iommu: fixed/dynamic overlap, skipping\n");
|
||||
continue;
|
||||
}
|
||||
io_pte[i] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask);
|
||||
|
||||
insert_16M_pte(uaddr, ptab, base_pte);
|
||||
}
|
||||
|
||||
mb();
|
||||
|
|
@ -995,7 +1018,9 @@ static int __init cell_iommu_fixed_mapping_init(void)
|
|||
"fixed window 0x%lx-0x%lx\n", iommu->nid, dbase,
|
||||
dbase + dsize, fbase, fbase + fsize);
|
||||
|
||||
cell_iommu_setup_page_tables(iommu, dbase, dsize, fbase, fsize);
|
||||
cell_iommu_setup_stab(iommu, dbase, dsize, fbase, fsize);
|
||||
iommu->ptab = cell_iommu_alloc_ptab(iommu, dbase, dsize, 0, 0,
|
||||
IOMMU_PAGE_SHIFT);
|
||||
cell_iommu_setup_fixed_ptab(iommu, np, dbase, dsize,
|
||||
fbase, fsize);
|
||||
cell_iommu_enable_hardware(iommu);
|
||||
|
|
|
|||
|
|
@ -149,6 +149,11 @@ static void __init cell_init_irq(void)
|
|||
mpic_init_IRQ();
|
||||
}
|
||||
|
||||
static void __init cell_set_dabrx(void)
|
||||
{
|
||||
mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
|
||||
}
|
||||
|
||||
static void __init cell_setup_arch(void)
|
||||
{
|
||||
#ifdef CONFIG_SPU_BASE
|
||||
|
|
@ -158,6 +163,8 @@ static void __init cell_setup_arch(void)
|
|||
|
||||
cbe_regs_init();
|
||||
|
||||
cell_set_dabrx();
|
||||
|
||||
#ifdef CONFIG_CBE_RAS
|
||||
cbe_ras_init();
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -81,9 +81,12 @@ struct spu_slb {
|
|||
void spu_invalidate_slbs(struct spu *spu)
|
||||
{
|
||||
struct spu_priv2 __iomem *priv2 = spu->priv2;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&spu->register_lock, flags);
|
||||
if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK)
|
||||
out_be64(&priv2->slb_invalidate_all_W, 0UL);
|
||||
spin_unlock_irqrestore(&spu->register_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(spu_invalidate_slbs);
|
||||
|
||||
|
|
@ -148,7 +151,11 @@ static inline void spu_load_slb(struct spu *spu, int slbe, struct spu_slb *slb)
|
|||
__func__, slbe, slb->vsid, slb->esid);
|
||||
|
||||
out_be64(&priv2->slb_index_W, slbe);
|
||||
/* set invalid before writing vsid */
|
||||
out_be64(&priv2->slb_esid_RW, 0);
|
||||
/* now it's safe to write the vsid */
|
||||
out_be64(&priv2->slb_vsid_RW, slb->vsid);
|
||||
/* setting the new esid makes the entry valid again */
|
||||
out_be64(&priv2->slb_esid_RW, slb->esid);
|
||||
}
|
||||
|
||||
|
|
@ -290,9 +297,11 @@ void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
|
|||
nr_slbs++;
|
||||
}
|
||||
|
||||
spin_lock_irq(&spu->register_lock);
|
||||
/* Add the set of SLBs */
|
||||
for (i = 0; i < nr_slbs; i++)
|
||||
spu_load_slb(spu, i, &slbs[i]);
|
||||
spin_unlock_irq(&spu->register_lock);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(spu_setup_kernel_slbs);
|
||||
|
||||
|
|
@ -337,13 +346,14 @@ spu_irq_class_1(int irq, void *data)
|
|||
if (stat & CLASS1_STORAGE_FAULT_INTR)
|
||||
spu_mfc_dsisr_set(spu, 0ul);
|
||||
spu_int_stat_clear(spu, 1, stat);
|
||||
spin_unlock(&spu->register_lock);
|
||||
pr_debug("%s: %lx %lx %lx %lx\n", __FUNCTION__, mask, stat,
|
||||
dar, dsisr);
|
||||
|
||||
if (stat & CLASS1_SEGMENT_FAULT_INTR)
|
||||
__spu_trap_data_seg(spu, dar);
|
||||
|
||||
spin_unlock(&spu->register_lock);
|
||||
pr_debug("%s: %lx %lx %lx %lx\n", __FUNCTION__, mask, stat,
|
||||
dar, dsisr);
|
||||
|
||||
if (stat & CLASS1_STORAGE_FAULT_INTR)
|
||||
__spu_trap_data_map(spu, dar, dsisr);
|
||||
|
||||
|
|
|
|||
|
|
@ -109,13 +109,12 @@ void spu_forget(struct spu_context *ctx)
|
|||
|
||||
/*
|
||||
* This is basically an open-coded spu_acquire_saved, except that
|
||||
* we don't acquire the state mutex interruptible.
|
||||
* we don't acquire the state mutex interruptible, and we don't
|
||||
* want this context to be rescheduled on release.
|
||||
*/
|
||||
mutex_lock(&ctx->state_mutex);
|
||||
if (ctx->state != SPU_STATE_SAVED) {
|
||||
set_bit(SPU_SCHED_WAS_ACTIVE, &ctx->sched_flags);
|
||||
if (ctx->state != SPU_STATE_SAVED)
|
||||
spu_deactivate(ctx);
|
||||
}
|
||||
|
||||
mm = ctx->owner;
|
||||
ctx->owner = NULL;
|
||||
|
|
|
|||
|
|
@ -366,6 +366,13 @@ static unsigned long spufs_ps_nopfn(struct vm_area_struct *vma,
|
|||
if (offset >= ps_size)
|
||||
return NOPFN_SIGBUS;
|
||||
|
||||
/*
|
||||
* Because we release the mmap_sem, the context may be destroyed while
|
||||
* we're in spu_wait. Grab an extra reference so it isn't destroyed
|
||||
* in the meantime.
|
||||
*/
|
||||
get_spu_context(ctx);
|
||||
|
||||
/*
|
||||
* We have to wait for context to be loaded before we have
|
||||
* pages to hand out to the user, but we don't want to wait
|
||||
|
|
@ -375,7 +382,7 @@ static unsigned long spufs_ps_nopfn(struct vm_area_struct *vma,
|
|||
* hanged.
|
||||
*/
|
||||
if (spu_acquire(ctx))
|
||||
return NOPFN_REFAULT;
|
||||
goto refault;
|
||||
|
||||
if (ctx->state == SPU_STATE_SAVED) {
|
||||
up_read(¤t->mm->mmap_sem);
|
||||
|
|
@ -391,6 +398,9 @@ static unsigned long spufs_ps_nopfn(struct vm_area_struct *vma,
|
|||
|
||||
if (!ret)
|
||||
spu_release(ctx);
|
||||
|
||||
refault:
|
||||
put_spu_context(ctx);
|
||||
return NOPFN_REFAULT;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -246,7 +246,7 @@ static void spu_bind_context(struct spu *spu, struct spu_context *ctx)
|
|||
spu_switch_notify(spu, ctx);
|
||||
ctx->state = SPU_STATE_RUNNABLE;
|
||||
|
||||
spuctx_switch_state(ctx, SPU_UTIL_IDLE_LOADED);
|
||||
spuctx_switch_state(ctx, SPU_UTIL_USER);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -58,12 +58,12 @@ static int sputrace_sprint(char *tbuf, int n)
|
|||
ktime_to_timespec(ktime_sub(t->tstamp, sputrace_start));
|
||||
|
||||
return snprintf(tbuf, n,
|
||||
"[%lu.%09lu] %d: %s (thread = %d, spu = %d)\n",
|
||||
"[%lu.%09lu] %d: %s (ctxthread = %d, spu = %d)\n",
|
||||
(unsigned long) tv.tv_sec,
|
||||
(unsigned long) tv.tv_nsec,
|
||||
t->owner_tid,
|
||||
t->name,
|
||||
t->curr_tid,
|
||||
t->name,
|
||||
t->owner_tid,
|
||||
t->number);
|
||||
}
|
||||
|
||||
|
|
@ -188,6 +188,7 @@ struct spu_probe spu_probes[] = {
|
|||
{ "spufs_ps_nopfn__insert", "%p %p", spu_context_event },
|
||||
{ "spu_acquire_saved__enter", "%p", spu_context_nospu_event },
|
||||
{ "destroy_spu_context__enter", "%p", spu_context_nospu_event },
|
||||
{ "spufs_stop_callback__enter", "%p %p", spu_context_event },
|
||||
};
|
||||
|
||||
static int __init sputrace_init(void)
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@
|
|||
|
||||
#include <linux/module.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/hardirq.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
|
|
@ -117,6 +118,8 @@ static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
|
|||
* Write INT_MASK_class1 with value of 0.
|
||||
* Save INT_Mask_class2 in CSA.
|
||||
* Write INT_MASK_class2 with value of 0.
|
||||
* Synchronize all three interrupts to be sure
|
||||
* we no longer execute a handler on another CPU.
|
||||
*/
|
||||
spin_lock_irq(&spu->register_lock);
|
||||
if (csa) {
|
||||
|
|
@ -129,6 +132,9 @@ static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
|
|||
spu_int_mask_set(spu, 2, 0ul);
|
||||
eieio();
|
||||
spin_unlock_irq(&spu->register_lock);
|
||||
synchronize_irq(spu->irqs[0]);
|
||||
synchronize_irq(spu->irqs[1]);
|
||||
synchronize_irq(spu->irqs[2]);
|
||||
}
|
||||
|
||||
static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
|
||||
|
|
|
|||
|
|
@ -21,9 +21,6 @@
|
|||
#ifndef _CELLEB_BEAT_H
|
||||
#define _CELLEB_BEAT_H
|
||||
|
||||
#define DABRX_KERNEL (1UL<<1)
|
||||
#define DABRX_USER (1UL<<0)
|
||||
|
||||
int64_t beat_get_term_char(uint64_t,uint64_t*,uint64_t*,uint64_t*);
|
||||
int64_t beat_put_term_char(uint64_t,uint64_t,uint64_t,uint64_t);
|
||||
int64_t beat_repository_encode(int, const char *, uint64_t[4]);
|
||||
|
|
|
|||
|
|
@ -73,8 +73,8 @@
|
|||
#define XHI_BUFFER_START 0
|
||||
|
||||
/**
|
||||
* buffer_icap_get_status: Get the contents of the status register.
|
||||
* @parameter base_address: is the base address of the device
|
||||
* buffer_icap_get_status - Get the contents of the status register.
|
||||
* @base_address: is the base address of the device
|
||||
*
|
||||
* The status register contains the ICAP status and the done bit.
|
||||
*
|
||||
|
|
@ -94,9 +94,9 @@ static inline u32 buffer_icap_get_status(void __iomem *base_address)
|
|||
}
|
||||
|
||||
/**
|
||||
* buffer_icap_get_bram: Reads data from the storage buffer bram.
|
||||
* @parameter base_address: contains the base address of the component.
|
||||
* @parameter offset: The word offset from which the data should be read.
|
||||
* buffer_icap_get_bram - Reads data from the storage buffer bram.
|
||||
* @base_address: contains the base address of the component.
|
||||
* @offset: The word offset from which the data should be read.
|
||||
*
|
||||
* A bram is used as a configuration memory cache. One frame of data can
|
||||
* be stored in this "storage buffer".
|
||||
|
|
@ -108,8 +108,8 @@ static inline u32 buffer_icap_get_bram(void __iomem *base_address,
|
|||
}
|
||||
|
||||
/**
|
||||
* buffer_icap_busy: Return true if the icap device is busy
|
||||
* @parameter base_address: is the base address of the device
|
||||
* buffer_icap_busy - Return true if the icap device is busy
|
||||
* @base_address: is the base address of the device
|
||||
*
|
||||
* The queries the low order bit of the status register, which
|
||||
* indicates whether the current configuration or readback operation
|
||||
|
|
@ -121,8 +121,8 @@ static inline bool buffer_icap_busy(void __iomem *base_address)
|
|||
}
|
||||
|
||||
/**
|
||||
* buffer_icap_busy: Return true if the icap device is not busy
|
||||
* @parameter base_address: is the base address of the device
|
||||
* buffer_icap_busy - Return true if the icap device is not busy
|
||||
* @base_address: is the base address of the device
|
||||
*
|
||||
* The queries the low order bit of the status register, which
|
||||
* indicates whether the current configuration or readback operation
|
||||
|
|
@ -134,9 +134,9 @@ static inline bool buffer_icap_done(void __iomem *base_address)
|
|||
}
|
||||
|
||||
/**
|
||||
* buffer_icap_set_size: Set the size register.
|
||||
* @parameter base_address: is the base address of the device
|
||||
* @parameter data: The size in bytes.
|
||||
* buffer_icap_set_size - Set the size register.
|
||||
* @base_address: is the base address of the device
|
||||
* @data: The size in bytes.
|
||||
*
|
||||
* The size register holds the number of 8 bit bytes to transfer between
|
||||
* bram and the icap (or icap to bram).
|
||||
|
|
@ -148,9 +148,9 @@ static inline void buffer_icap_set_size(void __iomem *base_address,
|
|||
}
|
||||
|
||||
/**
|
||||
* buffer_icap_mSetoffsetReg: Set the bram offset register.
|
||||
* @parameter base_address: contains the base address of the device.
|
||||
* @parameter data: is the value to be written to the data register.
|
||||
* buffer_icap_set_offset - Set the bram offset register.
|
||||
* @base_address: contains the base address of the device.
|
||||
* @data: is the value to be written to the data register.
|
||||
*
|
||||
* The bram offset register holds the starting bram address to transfer
|
||||
* data from during configuration or write data to during readback.
|
||||
|
|
@ -162,9 +162,9 @@ static inline void buffer_icap_set_offset(void __iomem *base_address,
|
|||
}
|
||||
|
||||
/**
|
||||
* buffer_icap_set_rnc: Set the RNC (Readback not Configure) register.
|
||||
* @parameter base_address: contains the base address of the device.
|
||||
* @parameter data: is the value to be written to the data register.
|
||||
* buffer_icap_set_rnc - Set the RNC (Readback not Configure) register.
|
||||
* @base_address: contains the base address of the device.
|
||||
* @data: is the value to be written to the data register.
|
||||
*
|
||||
* The RNC register determines the direction of the data transfer. It
|
||||
* controls whether a configuration or readback take place. Writing to
|
||||
|
|
@ -178,10 +178,10 @@ static inline void buffer_icap_set_rnc(void __iomem *base_address,
|
|||
}
|
||||
|
||||
/**
|
||||
* buffer_icap_set_bram: Write data to the storage buffer bram.
|
||||
* @parameter base_address: contains the base address of the component.
|
||||
* @parameter offset: The word offset at which the data should be written.
|
||||
* @parameter data: The value to be written to the bram offset.
|
||||
* buffer_icap_set_bram - Write data to the storage buffer bram.
|
||||
* @base_address: contains the base address of the component.
|
||||
* @offset: The word offset at which the data should be written.
|
||||
* @data: The value to be written to the bram offset.
|
||||
*
|
||||
* A bram is used as a configuration memory cache. One frame of data can
|
||||
* be stored in this "storage buffer".
|
||||
|
|
@ -193,10 +193,10 @@ static inline void buffer_icap_set_bram(void __iomem *base_address,
|
|||
}
|
||||
|
||||
/**
|
||||
* buffer_icap_device_read: Transfer bytes from ICAP to the storage buffer.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* @parameter offset: The storage buffer start address.
|
||||
* @parameter count: The number of words (32 bit) to read from the
|
||||
* buffer_icap_device_read - Transfer bytes from ICAP to the storage buffer.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
* @offset: The storage buffer start address.
|
||||
* @count: The number of words (32 bit) to read from the
|
||||
* device (ICAP).
|
||||
**/
|
||||
static int buffer_icap_device_read(struct hwicap_drvdata *drvdata,
|
||||
|
|
@ -227,10 +227,10 @@ static int buffer_icap_device_read(struct hwicap_drvdata *drvdata,
|
|||
};
|
||||
|
||||
/**
|
||||
* buffer_icap_device_write: Transfer bytes from ICAP to the storage buffer.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* @parameter offset: The storage buffer start address.
|
||||
* @parameter count: The number of words (32 bit) to read from the
|
||||
* buffer_icap_device_write - Transfer bytes from ICAP to the storage buffer.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
* @offset: The storage buffer start address.
|
||||
* @count: The number of words (32 bit) to read from the
|
||||
* device (ICAP).
|
||||
**/
|
||||
static int buffer_icap_device_write(struct hwicap_drvdata *drvdata,
|
||||
|
|
@ -261,8 +261,8 @@ static int buffer_icap_device_write(struct hwicap_drvdata *drvdata,
|
|||
};
|
||||
|
||||
/**
|
||||
* buffer_icap_reset: Reset the logic of the icap device.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* buffer_icap_reset - Reset the logic of the icap device.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
*
|
||||
* Writing to the status register resets the ICAP logic in an internal
|
||||
* version of the core. For the version of the core published in EDK,
|
||||
|
|
@ -274,10 +274,10 @@ void buffer_icap_reset(struct hwicap_drvdata *drvdata)
|
|||
}
|
||||
|
||||
/**
|
||||
* buffer_icap_set_configuration: Load a partial bitstream from system memory.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* @parameter data: Kernel address of the partial bitstream.
|
||||
* @parameter size: the size of the partial bitstream in 32 bit words.
|
||||
* buffer_icap_set_configuration - Load a partial bitstream from system memory.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
* @data: Kernel address of the partial bitstream.
|
||||
* @size: the size of the partial bitstream in 32 bit words.
|
||||
**/
|
||||
int buffer_icap_set_configuration(struct hwicap_drvdata *drvdata, u32 *data,
|
||||
u32 size)
|
||||
|
|
@ -333,10 +333,10 @@ int buffer_icap_set_configuration(struct hwicap_drvdata *drvdata, u32 *data,
|
|||
};
|
||||
|
||||
/**
|
||||
* buffer_icap_get_configuration: Read configuration data from the device.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* @parameter data: Address of the data representing the partial bitstream
|
||||
* @parameter size: the size of the partial bitstream in 32 bit words.
|
||||
* buffer_icap_get_configuration - Read configuration data from the device.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
* @data: Address of the data representing the partial bitstream
|
||||
* @size: the size of the partial bitstream in 32 bit words.
|
||||
**/
|
||||
int buffer_icap_get_configuration(struct hwicap_drvdata *drvdata, u32 *data,
|
||||
u32 size)
|
||||
|
|
|
|||
|
|
@ -94,9 +94,9 @@
|
|||
|
||||
|
||||
/**
|
||||
* fifo_icap_fifo_write: Write data to the write FIFO.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* @parameter data: the 32-bit value to be written to the FIFO.
|
||||
* fifo_icap_fifo_write - Write data to the write FIFO.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
* @data: the 32-bit value to be written to the FIFO.
|
||||
*
|
||||
* This function will silently fail if the fifo is full.
|
||||
**/
|
||||
|
|
@ -108,8 +108,8 @@ static inline void fifo_icap_fifo_write(struct hwicap_drvdata *drvdata,
|
|||
}
|
||||
|
||||
/**
|
||||
* fifo_icap_fifo_read: Read data from the Read FIFO.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* fifo_icap_fifo_read - Read data from the Read FIFO.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
*
|
||||
* This function will silently fail if the fifo is empty.
|
||||
**/
|
||||
|
|
@ -121,9 +121,9 @@ static inline u32 fifo_icap_fifo_read(struct hwicap_drvdata *drvdata)
|
|||
}
|
||||
|
||||
/**
|
||||
* fifo_icap_set_read_size: Set the the size register.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* @parameter data: the size of the following read transaction, in words.
|
||||
* fifo_icap_set_read_size - Set the the size register.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
* @data: the size of the following read transaction, in words.
|
||||
**/
|
||||
static inline void fifo_icap_set_read_size(struct hwicap_drvdata *drvdata,
|
||||
u32 data)
|
||||
|
|
@ -132,8 +132,8 @@ static inline void fifo_icap_set_read_size(struct hwicap_drvdata *drvdata,
|
|||
}
|
||||
|
||||
/**
|
||||
* fifo_icap_start_config: Initiate a configuration (write) to the device.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* fifo_icap_start_config - Initiate a configuration (write) to the device.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
**/
|
||||
static inline void fifo_icap_start_config(struct hwicap_drvdata *drvdata)
|
||||
{
|
||||
|
|
@ -142,8 +142,8 @@ static inline void fifo_icap_start_config(struct hwicap_drvdata *drvdata)
|
|||
}
|
||||
|
||||
/**
|
||||
* fifo_icap_start_readback: Initiate a readback from the device.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* fifo_icap_start_readback - Initiate a readback from the device.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
**/
|
||||
static inline void fifo_icap_start_readback(struct hwicap_drvdata *drvdata)
|
||||
{
|
||||
|
|
@ -152,8 +152,8 @@ static inline void fifo_icap_start_readback(struct hwicap_drvdata *drvdata)
|
|||
}
|
||||
|
||||
/**
|
||||
* fifo_icap_busy: Return true if the ICAP is still processing a transaction.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* fifo_icap_busy - Return true if the ICAP is still processing a transaction.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
**/
|
||||
static inline u32 fifo_icap_busy(struct hwicap_drvdata *drvdata)
|
||||
{
|
||||
|
|
@ -163,8 +163,8 @@ static inline u32 fifo_icap_busy(struct hwicap_drvdata *drvdata)
|
|||
}
|
||||
|
||||
/**
|
||||
* fifo_icap_write_fifo_vacancy: Query the write fifo available space.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* fifo_icap_write_fifo_vacancy - Query the write fifo available space.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
*
|
||||
* Return the number of words that can be safely pushed into the write fifo.
|
||||
**/
|
||||
|
|
@ -175,8 +175,8 @@ static inline u32 fifo_icap_write_fifo_vacancy(
|
|||
}
|
||||
|
||||
/**
|
||||
* fifo_icap_read_fifo_occupancy: Query the read fifo available data.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* fifo_icap_read_fifo_occupancy - Query the read fifo available data.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
*
|
||||
* Return the number of words that can be safely read from the read fifo.
|
||||
**/
|
||||
|
|
@ -187,11 +187,11 @@ static inline u32 fifo_icap_read_fifo_occupancy(
|
|||
}
|
||||
|
||||
/**
|
||||
* fifo_icap_set_configuration: Send configuration data to the ICAP.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* @parameter frame_buffer: a pointer to the data to be written to the
|
||||
* fifo_icap_set_configuration - Send configuration data to the ICAP.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
* @frame_buffer: a pointer to the data to be written to the
|
||||
* ICAP device.
|
||||
* @parameter num_words: the number of words (32 bit) to write to the ICAP
|
||||
* @num_words: the number of words (32 bit) to write to the ICAP
|
||||
* device.
|
||||
|
||||
* This function writes the given user data to the Write FIFO in
|
||||
|
|
@ -266,10 +266,10 @@ int fifo_icap_set_configuration(struct hwicap_drvdata *drvdata,
|
|||
}
|
||||
|
||||
/**
|
||||
* fifo_icap_get_configuration: Read configuration data from the device.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* @parameter data: Address of the data representing the partial bitstream
|
||||
* @parameter size: the size of the partial bitstream in 32 bit words.
|
||||
* fifo_icap_get_configuration - Read configuration data from the device.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
* @data: Address of the data representing the partial bitstream
|
||||
* @size: the size of the partial bitstream in 32 bit words.
|
||||
*
|
||||
* This function reads the specified number of words from the ICAP device in
|
||||
* the polled mode.
|
||||
|
|
@ -335,8 +335,8 @@ int fifo_icap_get_configuration(struct hwicap_drvdata *drvdata,
|
|||
}
|
||||
|
||||
/**
|
||||
* buffer_icap_reset: Reset the logic of the icap device.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* buffer_icap_reset - Reset the logic of the icap device.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
*
|
||||
* This function forces the software reset of the complete HWICAP device.
|
||||
* All the registers will return to the default value and the FIFO is also
|
||||
|
|
@ -360,8 +360,8 @@ void fifo_icap_reset(struct hwicap_drvdata *drvdata)
|
|||
}
|
||||
|
||||
/**
|
||||
* fifo_icap_flush_fifo: This function flushes the FIFOs in the device.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* fifo_icap_flush_fifo - This function flushes the FIFOs in the device.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
*/
|
||||
void fifo_icap_flush_fifo(struct hwicap_drvdata *drvdata)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/poll.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <asm/semaphore.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/sysctl.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/fs.h>
|
||||
|
|
@ -119,6 +119,7 @@ module_param(xhwicap_minor, int, S_IRUGO);
|
|||
|
||||
/* An array, which is set to true when the device is registered. */
|
||||
static bool probed_devices[HWICAP_DEVICES];
|
||||
static struct mutex icap_sem;
|
||||
|
||||
static struct class *icap_class;
|
||||
|
||||
|
|
@ -199,14 +200,14 @@ static const struct config_registers v5_config_registers = {
|
|||
};
|
||||
|
||||
/**
|
||||
* hwicap_command_desync: Send a DESYNC command to the ICAP port.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* hwicap_command_desync - Send a DESYNC command to the ICAP port.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
*
|
||||
* This command desynchronizes the ICAP After this command, a
|
||||
* bitstream containing a NULL packet, followed by a SYNCH packet is
|
||||
* required before the ICAP will recognize commands.
|
||||
*/
|
||||
int hwicap_command_desync(struct hwicap_drvdata *drvdata)
|
||||
static int hwicap_command_desync(struct hwicap_drvdata *drvdata)
|
||||
{
|
||||
u32 buffer[4];
|
||||
u32 index = 0;
|
||||
|
|
@ -228,51 +229,18 @@ int hwicap_command_desync(struct hwicap_drvdata *drvdata)
|
|||
}
|
||||
|
||||
/**
|
||||
* hwicap_command_capture: Send a CAPTURE command to the ICAP port.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
*
|
||||
* This command captures all of the flip flop states so they will be
|
||||
* available during readback. One can use this command instead of
|
||||
* enabling the CAPTURE block in the design.
|
||||
*/
|
||||
int hwicap_command_capture(struct hwicap_drvdata *drvdata)
|
||||
{
|
||||
u32 buffer[7];
|
||||
u32 index = 0;
|
||||
|
||||
/*
|
||||
* Create the data to be written to the ICAP.
|
||||
*/
|
||||
buffer[index++] = XHI_DUMMY_PACKET;
|
||||
buffer[index++] = XHI_SYNC_PACKET;
|
||||
buffer[index++] = XHI_NOOP_PACKET;
|
||||
buffer[index++] = hwicap_type_1_write(drvdata->config_regs->CMD) | 1;
|
||||
buffer[index++] = XHI_CMD_GCAPTURE;
|
||||
buffer[index++] = XHI_DUMMY_PACKET;
|
||||
buffer[index++] = XHI_DUMMY_PACKET;
|
||||
|
||||
/*
|
||||
* Write the data to the FIFO and intiate the transfer of data
|
||||
* present in the FIFO to the ICAP device.
|
||||
*/
|
||||
return drvdata->config->set_configuration(drvdata,
|
||||
&buffer[0], index);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* hwicap_get_configuration_register: Query a configuration register.
|
||||
* @parameter drvdata: a pointer to the drvdata.
|
||||
* @parameter reg: a constant which represents the configuration
|
||||
* hwicap_get_configuration_register - Query a configuration register.
|
||||
* @drvdata: a pointer to the drvdata.
|
||||
* @reg: a constant which represents the configuration
|
||||
* register value to be returned.
|
||||
* Examples: XHI_IDCODE, XHI_FLR.
|
||||
* @parameter RegData: returns the value of the register.
|
||||
* @reg_data: returns the value of the register.
|
||||
*
|
||||
* Sends a query packet to the ICAP and then receives the response.
|
||||
* The icap is left in Synched state.
|
||||
*/
|
||||
int hwicap_get_configuration_register(struct hwicap_drvdata *drvdata,
|
||||
u32 reg, u32 *RegData)
|
||||
static int hwicap_get_configuration_register(struct hwicap_drvdata *drvdata,
|
||||
u32 reg, u32 *reg_data)
|
||||
{
|
||||
int status;
|
||||
u32 buffer[6];
|
||||
|
|
@ -300,14 +268,14 @@ int hwicap_get_configuration_register(struct hwicap_drvdata *drvdata,
|
|||
/*
|
||||
* Read the configuration register
|
||||
*/
|
||||
status = drvdata->config->get_configuration(drvdata, RegData, 1);
|
||||
status = drvdata->config->get_configuration(drvdata, reg_data, 1);
|
||||
if (status)
|
||||
return status;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hwicap_initialize_hwicap(struct hwicap_drvdata *drvdata)
|
||||
static int hwicap_initialize_hwicap(struct hwicap_drvdata *drvdata)
|
||||
{
|
||||
int status;
|
||||
u32 idcode;
|
||||
|
|
@ -344,7 +312,7 @@ int hwicap_initialize_hwicap(struct hwicap_drvdata *drvdata)
|
|||
}
|
||||
|
||||
static ssize_t
|
||||
hwicap_read(struct file *file, char *buf, size_t count, loff_t *ppos)
|
||||
hwicap_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
|
||||
{
|
||||
struct hwicap_drvdata *drvdata = file->private_data;
|
||||
ssize_t bytes_to_read = 0;
|
||||
|
|
@ -353,8 +321,9 @@ hwicap_read(struct file *file, char *buf, size_t count, loff_t *ppos)
|
|||
u32 bytes_remaining;
|
||||
int status;
|
||||
|
||||
if (down_interruptible(&drvdata->sem))
|
||||
return -ERESTARTSYS;
|
||||
status = mutex_lock_interruptible(&drvdata->sem);
|
||||
if (status)
|
||||
return status;
|
||||
|
||||
if (drvdata->read_buffer_in_use) {
|
||||
/* If there are leftover bytes in the buffer, just */
|
||||
|
|
@ -370,8 +339,9 @@ hwicap_read(struct file *file, char *buf, size_t count, loff_t *ppos)
|
|||
goto error;
|
||||
}
|
||||
drvdata->read_buffer_in_use -= bytes_to_read;
|
||||
memcpy(drvdata->read_buffer + bytes_to_read,
|
||||
drvdata->read_buffer, 4 - bytes_to_read);
|
||||
memmove(drvdata->read_buffer,
|
||||
drvdata->read_buffer + bytes_to_read,
|
||||
4 - bytes_to_read);
|
||||
} else {
|
||||
/* Get new data from the ICAP, and return was was requested. */
|
||||
kbuf = (u32 *) get_zeroed_page(GFP_KERNEL);
|
||||
|
|
@ -414,18 +384,20 @@ hwicap_read(struct file *file, char *buf, size_t count, loff_t *ppos)
|
|||
status = -EFAULT;
|
||||
goto error;
|
||||
}
|
||||
memcpy(kbuf, drvdata->read_buffer, bytes_remaining);
|
||||
memcpy(drvdata->read_buffer,
|
||||
kbuf,
|
||||
bytes_remaining);
|
||||
drvdata->read_buffer_in_use = bytes_remaining;
|
||||
free_page((unsigned long)kbuf);
|
||||
}
|
||||
status = bytes_to_read;
|
||||
error:
|
||||
up(&drvdata->sem);
|
||||
mutex_unlock(&drvdata->sem);
|
||||
return status;
|
||||
}
|
||||
|
||||
static ssize_t
|
||||
hwicap_write(struct file *file, const char *buf,
|
||||
hwicap_write(struct file *file, const char __user *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct hwicap_drvdata *drvdata = file->private_data;
|
||||
|
|
@ -435,8 +407,9 @@ hwicap_write(struct file *file, const char *buf,
|
|||
ssize_t len;
|
||||
ssize_t status;
|
||||
|
||||
if (down_interruptible(&drvdata->sem))
|
||||
return -ERESTARTSYS;
|
||||
status = mutex_lock_interruptible(&drvdata->sem);
|
||||
if (status)
|
||||
return status;
|
||||
|
||||
left += drvdata->write_buffer_in_use;
|
||||
|
||||
|
|
@ -465,7 +438,7 @@ hwicap_write(struct file *file, const char *buf,
|
|||
memcpy(kbuf, drvdata->write_buffer,
|
||||
drvdata->write_buffer_in_use);
|
||||
if (copy_from_user(
|
||||
(((char *)kbuf) + (drvdata->write_buffer_in_use)),
|
||||
(((char *)kbuf) + drvdata->write_buffer_in_use),
|
||||
buf + written,
|
||||
len - (drvdata->write_buffer_in_use))) {
|
||||
free_page((unsigned long)kbuf);
|
||||
|
|
@ -508,7 +481,7 @@ hwicap_write(struct file *file, const char *buf,
|
|||
free_page((unsigned long)kbuf);
|
||||
status = written;
|
||||
error:
|
||||
up(&drvdata->sem);
|
||||
mutex_unlock(&drvdata->sem);
|
||||
return status;
|
||||
}
|
||||
|
||||
|
|
@ -519,8 +492,9 @@ static int hwicap_open(struct inode *inode, struct file *file)
|
|||
|
||||
drvdata = container_of(inode->i_cdev, struct hwicap_drvdata, cdev);
|
||||
|
||||
if (down_interruptible(&drvdata->sem))
|
||||
return -ERESTARTSYS;
|
||||
status = mutex_lock_interruptible(&drvdata->sem);
|
||||
if (status)
|
||||
return status;
|
||||
|
||||
if (drvdata->is_open) {
|
||||
status = -EBUSY;
|
||||
|
|
@ -539,7 +513,7 @@ static int hwicap_open(struct inode *inode, struct file *file)
|
|||
drvdata->is_open = 1;
|
||||
|
||||
error:
|
||||
up(&drvdata->sem);
|
||||
mutex_unlock(&drvdata->sem);
|
||||
return status;
|
||||
}
|
||||
|
||||
|
|
@ -549,8 +523,7 @@ static int hwicap_release(struct inode *inode, struct file *file)
|
|||
int i;
|
||||
int status = 0;
|
||||
|
||||
if (down_interruptible(&drvdata->sem))
|
||||
return -ERESTARTSYS;
|
||||
mutex_lock(&drvdata->sem);
|
||||
|
||||
if (drvdata->write_buffer_in_use) {
|
||||
/* Flush write buffer. */
|
||||
|
|
@ -569,7 +542,7 @@ static int hwicap_release(struct inode *inode, struct file *file)
|
|||
|
||||
error:
|
||||
drvdata->is_open = 0;
|
||||
up(&drvdata->sem);
|
||||
mutex_unlock(&drvdata->sem);
|
||||
return status;
|
||||
}
|
||||
|
||||
|
|
@ -592,31 +565,36 @@ static int __devinit hwicap_setup(struct device *dev, int id,
|
|||
|
||||
dev_info(dev, "Xilinx icap port driver\n");
|
||||
|
||||
mutex_lock(&icap_sem);
|
||||
|
||||
if (id < 0) {
|
||||
for (id = 0; id < HWICAP_DEVICES; id++)
|
||||
if (!probed_devices[id])
|
||||
break;
|
||||
}
|
||||
if (id < 0 || id >= HWICAP_DEVICES) {
|
||||
mutex_unlock(&icap_sem);
|
||||
dev_err(dev, "%s%i too large\n", DRIVER_NAME, id);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (probed_devices[id]) {
|
||||
mutex_unlock(&icap_sem);
|
||||
dev_err(dev, "cannot assign to %s%i; it is already in use\n",
|
||||
DRIVER_NAME, id);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
probed_devices[id] = 1;
|
||||
mutex_unlock(&icap_sem);
|
||||
|
||||
devt = MKDEV(xhwicap_major, xhwicap_minor + id);
|
||||
|
||||
drvdata = kmalloc(sizeof(struct hwicap_drvdata), GFP_KERNEL);
|
||||
drvdata = kzalloc(sizeof(struct hwicap_drvdata), GFP_KERNEL);
|
||||
if (!drvdata) {
|
||||
dev_err(dev, "Couldn't allocate device private record\n");
|
||||
return -ENOMEM;
|
||||
retval = -ENOMEM;
|
||||
goto failed0;
|
||||
}
|
||||
memset((void *)drvdata, 0, sizeof(struct hwicap_drvdata));
|
||||
dev_set_drvdata(dev, (void *)drvdata);
|
||||
|
||||
if (!regs_res) {
|
||||
|
|
@ -648,7 +626,7 @@ static int __devinit hwicap_setup(struct device *dev, int id,
|
|||
drvdata->config = config;
|
||||
drvdata->config_regs = config_regs;
|
||||
|
||||
init_MUTEX(&drvdata->sem);
|
||||
mutex_init(&drvdata->sem);
|
||||
drvdata->is_open = 0;
|
||||
|
||||
dev_info(dev, "ioremap %lx to %p with size %x\n",
|
||||
|
|
@ -663,7 +641,7 @@ static int __devinit hwicap_setup(struct device *dev, int id,
|
|||
goto failed3;
|
||||
}
|
||||
/* devfs_mk_cdev(devt, S_IFCHR|S_IRUGO|S_IWUGO, DRIVER_NAME); */
|
||||
class_device_create(icap_class, NULL, devt, NULL, DRIVER_NAME);
|
||||
device_create(icap_class, dev, devt, "%s%d", DRIVER_NAME, id);
|
||||
return 0; /* success */
|
||||
|
||||
failed3:
|
||||
|
|
@ -675,6 +653,11 @@ static int __devinit hwicap_setup(struct device *dev, int id,
|
|||
failed1:
|
||||
kfree(drvdata);
|
||||
|
||||
failed0:
|
||||
mutex_lock(&icap_sem);
|
||||
probed_devices[id] = 0;
|
||||
mutex_unlock(&icap_sem);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
|
@ -699,14 +682,16 @@ static int __devexit hwicap_remove(struct device *dev)
|
|||
if (!drvdata)
|
||||
return 0;
|
||||
|
||||
class_device_destroy(icap_class, drvdata->devt);
|
||||
device_destroy(icap_class, drvdata->devt);
|
||||
cdev_del(&drvdata->cdev);
|
||||
iounmap(drvdata->base_address);
|
||||
release_mem_region(drvdata->mem_start, drvdata->mem_size);
|
||||
kfree(drvdata);
|
||||
dev_set_drvdata(dev, NULL);
|
||||
probed_devices[MINOR(dev->devt)-xhwicap_minor] = 0;
|
||||
|
||||
mutex_lock(&icap_sem);
|
||||
probed_devices[MINOR(dev->devt)-xhwicap_minor] = 0;
|
||||
mutex_unlock(&icap_sem);
|
||||
return 0; /* success */
|
||||
}
|
||||
|
||||
|
|
@ -821,28 +806,29 @@ static struct of_platform_driver hwicap_of_driver = {
|
|||
};
|
||||
|
||||
/* Registration helpers to keep the number of #ifdefs to a minimum */
|
||||
static inline int __devinit hwicap_of_register(void)
|
||||
static inline int __init hwicap_of_register(void)
|
||||
{
|
||||
pr_debug("hwicap: calling of_register_platform_driver()\n");
|
||||
return of_register_platform_driver(&hwicap_of_driver);
|
||||
}
|
||||
|
||||
static inline void __devexit hwicap_of_unregister(void)
|
||||
static inline void __exit hwicap_of_unregister(void)
|
||||
{
|
||||
of_unregister_platform_driver(&hwicap_of_driver);
|
||||
}
|
||||
#else /* CONFIG_OF */
|
||||
/* CONFIG_OF not enabled; do nothing helpers */
|
||||
static inline int __devinit hwicap_of_register(void) { return 0; }
|
||||
static inline void __devexit hwicap_of_unregister(void) { }
|
||||
static inline int __init hwicap_of_register(void) { return 0; }
|
||||
static inline void __exit hwicap_of_unregister(void) { }
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
static int __devinit hwicap_module_init(void)
|
||||
static int __init hwicap_module_init(void)
|
||||
{
|
||||
dev_t devt;
|
||||
int retval;
|
||||
|
||||
icap_class = class_create(THIS_MODULE, "xilinx_config");
|
||||
mutex_init(&icap_sem);
|
||||
|
||||
if (xhwicap_major) {
|
||||
devt = MKDEV(xhwicap_major, xhwicap_minor);
|
||||
|
|
@ -883,7 +869,7 @@ static int __devinit hwicap_module_init(void)
|
|||
return retval;
|
||||
}
|
||||
|
||||
static void __devexit hwicap_module_cleanup(void)
|
||||
static void __exit hwicap_module_cleanup(void)
|
||||
{
|
||||
dev_t devt = MKDEV(xhwicap_major, xhwicap_minor);
|
||||
|
||||
|
|
|
|||
|
|
@ -48,9 +48,9 @@ struct hwicap_drvdata {
|
|||
u8 write_buffer[4];
|
||||
u32 read_buffer_in_use; /* Always in [0,3] */
|
||||
u8 read_buffer[4];
|
||||
u32 mem_start; /* phys. address of the control registers */
|
||||
u32 mem_end; /* phys. address of the control registers */
|
||||
u32 mem_size;
|
||||
resource_size_t mem_start;/* phys. address of the control registers */
|
||||
resource_size_t mem_end; /* phys. address of the control registers */
|
||||
resource_size_t mem_size;
|
||||
void __iomem *base_address;/* virt. address of the control registers */
|
||||
|
||||
struct device *dev;
|
||||
|
|
@ -61,7 +61,7 @@ struct hwicap_drvdata {
|
|||
const struct config_registers *config_regs;
|
||||
void *private_data;
|
||||
bool is_open;
|
||||
struct semaphore sem;
|
||||
struct mutex sem;
|
||||
};
|
||||
|
||||
struct hwicap_driver_config {
|
||||
|
|
@ -164,29 +164,29 @@ struct config_registers {
|
|||
#define XHI_DISABLED_AUTO_CRC 0x0000DEFCUL
|
||||
|
||||
/**
|
||||
* hwicap_type_1_read: Generates a Type 1 read packet header.
|
||||
* @parameter: Register is the address of the register to be read back.
|
||||
* hwicap_type_1_read - Generates a Type 1 read packet header.
|
||||
* @reg: is the address of the register to be read back.
|
||||
*
|
||||
* Generates a Type 1 read packet header, which is used to indirectly
|
||||
* read registers in the configuration logic. This packet must then
|
||||
* be sent through the icap device, and a return packet received with
|
||||
* the information.
|
||||
**/
|
||||
static inline u32 hwicap_type_1_read(u32 Register)
|
||||
static inline u32 hwicap_type_1_read(u32 reg)
|
||||
{
|
||||
return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
|
||||
(Register << XHI_REGISTER_SHIFT) |
|
||||
(reg << XHI_REGISTER_SHIFT) |
|
||||
(XHI_OP_READ << XHI_OP_SHIFT);
|
||||
}
|
||||
|
||||
/**
|
||||
* hwicap_type_1_write: Generates a Type 1 write packet header
|
||||
* @parameter: Register is the address of the register to be read back.
|
||||
* hwicap_type_1_write - Generates a Type 1 write packet header
|
||||
* @reg: is the address of the register to be read back.
|
||||
**/
|
||||
static inline u32 hwicap_type_1_write(u32 Register)
|
||||
static inline u32 hwicap_type_1_write(u32 reg)
|
||||
{
|
||||
return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
|
||||
(Register << XHI_REGISTER_SHIFT) |
|
||||
(reg << XHI_REGISTER_SHIFT) |
|
||||
(XHI_OP_WRITE << XHI_OP_SHIFT);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -153,6 +153,9 @@
|
|||
#define CTRL_RUNLATCH 0x1
|
||||
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
|
||||
#define DABR_TRANSLATION (1UL << 2)
|
||||
#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
|
||||
#define DABRX_USER (1UL << 0)
|
||||
#define DABRX_KERNEL (1UL << 1)
|
||||
#define SPRN_DAR 0x013 /* Data Address Register */
|
||||
#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
|
||||
#define DSISR_NOHPTE 0x40000000 /* no translation found */
|
||||
|
|
|
|||
Loading…
Reference in New Issue