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RISC-V: recognize S/U mode bits in print_isa 

Removes the warning about an unsupported ISA when reading /proc/cpuinfo
on QEMU. The "S" extension is not being returned as it is not accessible
from userspace.

Signed-off-by: Patrick Stählin <me@packi.ch>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Patrick Stählin 2018-11-09 22:42:16 +01:00 committed by Palmer Dabbelt
parent 27f8899d60
commit 5d8f81ba1d
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GPG Key ID: EF4CA1502CCBAB41
1 changed files with 6 additions and 3 deletions
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7
arch/riscv/kernel/cpu.c
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@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node)
static void print_isa(struct seq_file *f, const char *orig_isa) static void print_isa(struct seq_file *f, const char *orig_isa)
{ {
static const char *ext = "mafdc"; static const char *ext = "mafdcsu";
const char *isa = orig_isa; const char *isa = orig_isa;
const char *e; const char *e;
@ -88,11 +88,14 @@ static void print_isa(struct seq_file *f, const char *orig_isa)
/* /*
* Check the rest of the ISA string for valid extensions, printing those * Check the rest of the ISA string for valid extensions, printing those
* we find. RISC-V ISA strings define an order, so we only print the * we find. RISC-V ISA strings define an order, so we only print the
* extension bits when they're in order. * extension bits when they're in order. Hide the supervisor (S)
* extension from userspace as it's not accessible from there.
*/ */
for (e = ext; *e != '\0'; ++e) { for (e = ext; *e != '\0'; ++e) {
if (isa[0] == e[0]) { if (isa[0] == e[0]) {
if (isa[0] != 's')
seq_write(f, isa, 1); seq_write(f, isa, 1);
isa++; isa++;
} }
} }