mirror of https://gitee.com/openkylin/linux.git
drm/i915: add proper CPU/PCH checks to crtc_mode_set functions
On ironlake_crtc_mode_set, WARN if not using IBX or CPT. On haswell_crtc_mode_set, only run IBX/CPT code on IBX/CPT. I am still not sure whether IBX/CPT will be possible with a Haswell CPU, so leave the code there for now and put a WARN in case we spot it. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Paulo Zanoni
Daniel Vetter
parent
09b4ddf95d
commit
5dc5298bb3
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@ -5002,6 +5002,9 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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num_connectors++;
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}
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WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
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"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
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ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
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&has_reduced_clock, &reduced_clock);
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if (!ok) {
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@ -5027,12 +5030,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
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drm_mode_debug_printmodeline(mode);
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/* CPU eDP is the only output that doesn't need a PCH PLL of its own on
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* pre-Haswell/LPT generation */
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if (HAS_PCH_LPT(dev)) {
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DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
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pipe);
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} else if (!is_cpu_edp) {
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/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
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if (!is_cpu_edp) {
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struct intel_pch_pll *pll;
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pll = intel_get_pch_pll(intel_crtc, dpll, fp);
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@ -5155,7 +5154,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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int plane = intel_crtc->plane;
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int num_connectors = 0;
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intel_clock_t clock, reduced_clock;
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u32 dpll, fp = 0, fp2 = 0;
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u32 dpll = 0, fp = 0, fp2 = 0;
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bool ok, has_reduced_clock = false;
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bool is_lvds = false, is_dp = false, is_cpu_edp = false;
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struct intel_encoder *encoder;
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@ -5181,11 +5180,21 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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num_connectors++;
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}
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ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
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&has_reduced_clock, &reduced_clock);
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if (!ok) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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/* We are not sure yet this won't happen. */
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WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
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INTEL_PCH_TYPE(dev));
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WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
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num_connectors, pipe_name(pipe));
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
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ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
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&has_reduced_clock,
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&reduced_clock);
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if (!ok) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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}
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}
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/* Ensure that the cursor is valid for the new mode before changing... */
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@ -5196,104 +5205,112 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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if (is_lvds && dev_priv->lvds_dither)
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dither = true;
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fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
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if (has_reduced_clock)
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fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
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reduced_clock.m2;
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dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
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DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
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drm_mode_debug_printmodeline(mode);
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/* CPU eDP is the only output that doesn't need a PCH PLL of its own on
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* pre-Haswell/LPT generation */
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if (HAS_PCH_LPT(dev)) {
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DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
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pipe);
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} else if (!is_cpu_edp) {
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struct intel_pch_pll *pll;
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
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fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
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if (has_reduced_clock)
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fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
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reduced_clock.m2;
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pll = intel_get_pch_pll(intel_crtc, dpll, fp);
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if (pll == NULL) {
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DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
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pipe);
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return -EINVAL;
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}
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} else
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intel_put_pch_pll(intel_crtc);
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dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
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fp);
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/* The LVDS pin pair needs to be on before the DPLLs are enabled.
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* This is an exception to the general rule that mode_set doesn't turn
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* things on.
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*/
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if (is_lvds) {
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temp = I915_READ(PCH_LVDS);
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temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
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if (HAS_PCH_CPT(dev)) {
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temp &= ~PORT_TRANS_SEL_MASK;
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temp |= PORT_TRANS_SEL_CPT(pipe);
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} else {
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if (pipe == 1)
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temp |= LVDS_PIPEB_SELECT;
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/* CPU eDP is the only output that doesn't need a PCH PLL of its
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* own on pre-Haswell/LPT generation */
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if (!is_cpu_edp) {
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struct intel_pch_pll *pll;
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pll = intel_get_pch_pll(intel_crtc, dpll, fp);
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if (pll == NULL) {
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DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
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pipe);
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return -EINVAL;
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}
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} else
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intel_put_pch_pll(intel_crtc);
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/* The LVDS pin pair needs to be on before the DPLLs are
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* enabled. This is an exception to the general rule that
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* mode_set doesn't turn things on.
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*/
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if (is_lvds) {
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temp = I915_READ(PCH_LVDS);
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temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
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if (HAS_PCH_CPT(dev)) {
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temp &= ~PORT_TRANS_SEL_MASK;
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temp |= PORT_TRANS_SEL_CPT(pipe);
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} else {
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if (pipe == 1)
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temp |= LVDS_PIPEB_SELECT;
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else
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temp &= ~LVDS_PIPEB_SELECT;
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}
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/* set the corresponsding LVDS_BORDER bit */
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temp |= dev_priv->lvds_border_bits;
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/* Set the B0-B3 data pairs corresponding to whether
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* we're going to set the DPLLs for dual-channel mode or
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* not.
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*/
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if (clock.p2 == 7)
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temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
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else
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temp &= ~LVDS_PIPEB_SELECT;
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temp &= ~(LVDS_B0B3_POWER_UP |
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LVDS_CLKB_POWER_UP);
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/* It would be nice to set 24 vs 18-bit mode
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* (LVDS_A3_POWER_UP) appropriately here, but we need to
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* look more thoroughly into how panels behave in the
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* two modes.
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*/
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temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
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if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
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temp |= LVDS_HSYNC_POLARITY;
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if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
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temp |= LVDS_VSYNC_POLARITY;
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I915_WRITE(PCH_LVDS, temp);
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}
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/* set the corresponsding LVDS_BORDER bit */
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temp |= dev_priv->lvds_border_bits;
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/* Set the B0-B3 data pairs corresponding to whether we're going to
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* set the DPLLs for dual-channel mode or not.
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*/
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if (clock.p2 == 7)
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temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
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else
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temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
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/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
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* appropriately here, but we need to look more thoroughly into how
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* panels behave in the two modes.
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*/
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temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
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if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
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temp |= LVDS_HSYNC_POLARITY;
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if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
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temp |= LVDS_VSYNC_POLARITY;
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I915_WRITE(PCH_LVDS, temp);
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}
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if (is_dp && !is_cpu_edp) {
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intel_dp_set_m_n(crtc, mode, adjusted_mode);
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} else {
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/* For non-DP output, clear any trans DP clock recovery setting.*/
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I915_WRITE(TRANSDATA_M1(pipe), 0);
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I915_WRITE(TRANSDATA_N1(pipe), 0);
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I915_WRITE(TRANSDPLINK_M1(pipe), 0);
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I915_WRITE(TRANSDPLINK_N1(pipe), 0);
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}
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if (intel_crtc->pch_pll) {
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I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
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/* Wait for the clocks to stabilize. */
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POSTING_READ(intel_crtc->pch_pll->pll_reg);
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udelay(150);
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/* The pixel multiplier can only be updated once the
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* DPLL is enabled and the clocks are stable.
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*
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* So write it again.
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*/
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I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
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/* For non-DP output, clear any trans DP clock recovery
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* setting.*/
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I915_WRITE(TRANSDATA_M1(pipe), 0);
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I915_WRITE(TRANSDATA_N1(pipe), 0);
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I915_WRITE(TRANSDPLINK_M1(pipe), 0);
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I915_WRITE(TRANSDPLINK_N1(pipe), 0);
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}
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}
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intel_crtc->lowfreq_avail = false;
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if (intel_crtc->pch_pll) {
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if (is_lvds && has_reduced_clock && i915_powersave) {
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I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
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intel_crtc->lowfreq_avail = true;
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} else {
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I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
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if (intel_crtc->pch_pll) {
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I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
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/* Wait for the clocks to stabilize. */
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POSTING_READ(intel_crtc->pch_pll->pll_reg);
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udelay(150);
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/* The pixel multiplier can only be updated once the
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* DPLL is enabled and the clocks are stable.
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*
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* So write it again.
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*/
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I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
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}
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if (intel_crtc->pch_pll) {
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if (is_lvds && has_reduced_clock && i915_powersave) {
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I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
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intel_crtc->lowfreq_avail = true;
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} else {
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I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
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}
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}
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}
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@ -5301,8 +5318,9 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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ironlake_set_m_n(crtc, mode, adjusted_mode);
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if (is_cpu_edp)
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ironlake_set_pll_edp(crtc, adjusted_mode->clock);
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
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if (is_cpu_edp)
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ironlake_set_pll_edp(crtc, adjusted_mode->clock);
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ironlake_set_pipeconf(crtc, adjusted_mode, dither);
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