mirror of https://gitee.com/openkylin/linux.git
PCI update for v3.18:
NVIDIA Tegra - Use physical range for I/O mapping (Thierry Reding) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUf1W0AAoJEFmIoMA60/r8wIUP/iFJKucfHJUDo3i/R96vXYhv /PEosMwQu2FnfLC13vOnUnx9m2uv2gpthhI255guxm3DUIsurOcdBGR7ZoaQcMkD 0NMf/UeGlKPFkXk5ltJiO4SHsAv8ITMV7pYcUl4DX0E288kBjM4LV69+aprKw7GY ULZDDqIE5x6SkmBv5PopTr7M+Z6omQ+nxZ6txMAM3ks2+rku6SzqPaWZFhpTinqn AJlx9gqjN8OLuPNXqHia+hBzPk9xvisCOZ0kOXpS3ipeXvyLVPThqhO1fG9RFY0a BXK+l8E7z3zcwIZIQMsVl3zuxYVpjQhgNlPqFyYE+TCW/kG6V3STWzmYW/kCT0ax ipVeSKXZnmcf7iKZ78UdW8bXZGHi6WNouaN0/NAtXh9Gln8P2qOuSBwv1H3374in NnIFPr8bFNXgSr8OPZWIqhwQEdPZgydxq28DxIEZCdYo4idP3Q+yElQPpmZzBeeC 8rnFyHsBFdazr7W44jsPnn45Fdy2LEEo07v80buj/RwdwMV2zj2OFLUMT9Nlyu6k p7HLM40FZlyeu+OHjzc0zu/GjQ5CAt4SV0DSQ/Gi80Bq1X+qHPVc7u6MoKmS0wYr wZ2/DCXHloMRsITZ6fyPVNsUHB9S9M01V4VCnzCSeJ65ArvNeP5+7yzQKUIEKLQ9 FclPrRsT+jaJUWVpNLjE =KWwE -----END PGP SIGNATURE----- Merge tag 'pci-v3.18-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fix from Bjorn Helgaas: "This fixes a Tegra20 regression that we introduced during the v3.18 merge window" * tag 'pci-v3.18-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: tegra: Use physical range for I/O mapping
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commit
5dc626358f
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@ -276,6 +276,7 @@ struct tegra_pcie {
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struct resource all;
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struct resource io;
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struct resource pio;
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struct resource mem;
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struct resource prefetch;
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struct resource busn;
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@ -658,7 +659,6 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
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{
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struct tegra_pcie *pcie = sys_to_pcie(sys);
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int err;
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phys_addr_t io_start;
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err = devm_request_resource(pcie->dev, &pcie->all, &pcie->mem);
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if (err < 0)
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@ -668,14 +668,12 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
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if (err)
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return err;
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io_start = pci_pio_to_address(pcie->io.start);
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pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
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pci_add_resource_offset(&sys->resources, &pcie->prefetch,
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sys->mem_offset);
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pci_add_resource(&sys->resources, &pcie->busn);
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pci_ioremap_io(nr * SZ_64K, io_start);
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pci_ioremap_io(pcie->pio.start, pcie->io.start);
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return 1;
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}
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@ -786,7 +784,6 @@ static irqreturn_t tegra_pcie_isr(int irq, void *arg)
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static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
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{
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u32 fpci_bar, size, axi_address;
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phys_addr_t io_start = pci_pio_to_address(pcie->io.start);
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/* Bar 0: type 1 extended configuration space */
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fpci_bar = 0xfe100000;
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@ -799,7 +796,7 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
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/* Bar 1: downstream IO bar */
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fpci_bar = 0xfdfc0000;
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size = resource_size(&pcie->io);
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axi_address = io_start;
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axi_address = pcie->io.start;
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afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
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afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
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afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
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@ -1690,8 +1687,23 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
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switch (res.flags & IORESOURCE_TYPE_BITS) {
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case IORESOURCE_IO:
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memcpy(&pcie->io, &res, sizeof(res));
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pcie->io.name = np->full_name;
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memcpy(&pcie->pio, &res, sizeof(res));
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pcie->pio.name = np->full_name;
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/*
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* The Tegra PCIe host bridge uses this to program the
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* mapping of the I/O space to the physical address,
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* so we override the .start and .end fields here that
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* of_pci_range_to_resource() converted to I/O space.
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* We also set the IORESOURCE_MEM type to clarify that
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* the resource is in the physical memory space.
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*/
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pcie->io.start = range.cpu_addr;
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pcie->io.end = range.cpu_addr + range.size - 1;
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pcie->io.flags = IORESOURCE_MEM;
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pcie->io.name = "I/O";
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memcpy(&res, &pcie->io, sizeof(res));
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break;
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case IORESOURCE_MEM:
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