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RISC-V: probes: Treat the instruction stream as host-endian 

Neither of these are actually correct: the instruction stream is defined
(for versions of the ISA manual newer than 2.2) as a stream of 16-bit
little-endian parcels, which is different than just being little-endian.
In theory we should represent this as a type, but we don't have any
concrete plans for the big endian stuff so it doesn't seem worth the
time -- we've got variants of this all over the place.

Instead I'm just dropping the unnecessary type conversion, which is a
NOP on LE systems but causes an sparse error as the types are all mixed
up.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Palmer Dabbelt 2021-01-22 19:34:29 -08:00
parent d4c34d09ab
commit 5dd6713331
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GPG Key ID: 2E1319F35FBB1889
2 changed files with 2 additions and 2 deletions
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2
arch/riscv/kernel/probes/decode-insn.c
View File

@ -16,7 +16,7 @@
enum probe_insn __kprobes
riscv_probe_decode_insn(probe_opcode_t *addr, struct arch_probe_insn *api)
{
probe_opcode_t insn = le32_to_cpu(*addr);
probe_opcode_t insn = *addr;
/*
* Reject instructions list:

2
arch/riscv/kernel/probes/kprobes.c
View File

@ -57,7 +57,7 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
}
/* copy instruction */
p->opcode = le32_to_cpu(*p->addr);
p->opcode = *p->addr;
/* decode instruction */
switch (riscv_probe_decode_insn(p->addr, &p->ainsn.api)) {