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brcmfmac: always perform cores checks 

Instead of checking the cores in the chip only if CONFIG_BRCMDBG
is selected perform the check always and extend it with more sanity
checking.

Reviewed-by: Hante Meuleman <meuleman@broadcom.com>
Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com>
Signed-off-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Arend van Spriel 2015-03-11 16:11:28 +01:00 committed by Kalle Valo
parent 55b59fba0f
commit 5ded1c251f
1 changed files with 11 additions and 7 deletions
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18
drivers/net/wireless/brcm80211/brcmfmac/chip.c
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@ -419,13 +419,13 @@ static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
return &core->pub; return &core->pub;
} }
#ifdef DEBUG
/* safety check for chipinfo */ /* safety check for chipinfo */
static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci) static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
{ {
struct brcmf_core_priv *core; struct brcmf_core_priv *core;
bool need_socram = false; bool need_socram = false;
bool has_socram = false; bool has_socram = false;
bool cpu_found = false;
int idx = 1; int idx = 1;
list_for_each_entry(core, &ci->cores, list) { list_for_each_entry(core, &ci->cores, list) {
@ -435,12 +435,14 @@ static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
switch (core->pub.id) { switch (core->pub.id) {
case BCMA_CORE_ARM_CM3: case BCMA_CORE_ARM_CM3:
cpu_found = true;
need_socram = true; need_socram = true;
break; break;
case BCMA_CORE_INTERNAL_MEM: case BCMA_CORE_INTERNAL_MEM:
has_socram = true; has_socram = true;
break; break;
case BCMA_CORE_ARM_CR4: case BCMA_CORE_ARM_CR4:
cpu_found = true;
if (ci->pub.rambase == 0) { if (ci->pub.rambase == 0) {
brcmf_err("RAM base not provided with ARM CR4 core\n"); brcmf_err("RAM base not provided with ARM CR4 core\n");
return -ENOMEM; return -ENOMEM;
@ -451,19 +453,21 @@ static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
} }
} }
if (!cpu_found) {
brcmf_err("CPU core not detected\n");
return -ENXIO;
}
/* check RAM core presence for ARM CM3 core */ /* check RAM core presence for ARM CM3 core */
if (need_socram && !has_socram) { if (need_socram && !has_socram) {
brcmf_err("RAM core not provided with ARM CM3 core\n"); brcmf_err("RAM core not provided with ARM CM3 core\n");
return -ENODEV; return -ENODEV;
} }
if (!ci->pub.ramsize) {
brcmf_err("RAM size is undetermined\n");
return -ENOMEM;
}
return 0; return 0;
} }
#else /* DEBUG */
static inline int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
{
return 0;
}
#endif
static void brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci) static void brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
{ {