mirror of https://gitee.com/openkylin/linux.git
V4L/DVB: gspca_tv8532: remove a whole bunch of unnecessary register writes
There is a problem with certain tv8532 cams, where sometimes there hsync/vsync locks one pixel of where it normally locks. While trying to fix this (which I failed to do). I noticed there are lots if duplicate register writes and unnecessary register reads in the tv8532 driver. This patch cleanes these ups (which has no negative effects, but unfortunately also does not help). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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d6b6d7aef4
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5e027610ea
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@ -129,18 +129,6 @@ static const u8 eeprom_data[][3] = {
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{0x05, 0x09, 0xf1},
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};
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static int reg_r(struct gspca_dev *gspca_dev,
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__u16 index)
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{
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usb_control_msg(gspca_dev->dev,
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usb_rcvctrlpipe(gspca_dev->dev, 0),
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0x03,
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USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
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0, /* value */
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index, gspca_dev->usb_buf, 1,
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500);
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return gspca_dev->usb_buf[0];
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}
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/* write 1 byte */
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static void reg_w1(struct gspca_dev *gspca_dev,
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@ -183,7 +171,6 @@ static void tv_8532WriteEEprom(struct gspca_dev *gspca_dev)
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}
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reg_w1(gspca_dev, R07_TABLE_LEN, i);
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reg_w1(gspca_dev, R01_TIMING_CONTROL_LOW, CMD_EEprom_Close);
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msleep(10);
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}
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/* this function is called at probe time */
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@ -201,49 +188,8 @@ static int sd_config(struct gspca_dev *gspca_dev,
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return 0;
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}
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static void tv_8532ReadRegisters(struct gspca_dev *gspca_dev)
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{
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int i;
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static u8 reg_tb[] = {
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R0C_AD_WIDTHL,
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R0D_AD_WIDTHH,
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R28_QUANT,
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R29_LINE,
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R2C_POLARITY,
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R2D_POINT,
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R2E_POINTH,
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R2F_POINTB,
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R30_POINTBH,
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R2A_HIGH_BUDGET,
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R2B_LOW_BUDGET,
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R34_VID,
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R35_VIDH,
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R36_PID,
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R37_PIDH,
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R83_AD_IDH,
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R10_AD_COL_BEGINL,
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R11_AD_COL_BEGINH,
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R14_AD_ROW_BEGINL,
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R15_AD_ROWBEGINH,
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0
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};
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i = 0;
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do {
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reg_r(gspca_dev, reg_tb[i]);
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i++;
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} while (reg_tb[i] != 0);
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}
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static void tv_8532_setReg(struct gspca_dev *gspca_dev)
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{
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reg_w1(gspca_dev, R10_AD_COL_BEGINL, 0x44);
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/* begin active line */
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reg_w1(gspca_dev, R11_AD_COL_BEGINH, 0x00);
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/* mirror and digital gain */
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reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE);
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/* = 0x84 */
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reg_w1(gspca_dev, R3B_Test3, 0x0a); /* Test0Sel = 10 */
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/******************************************************/
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reg_w1(gspca_dev, R0E_AD_HEIGHTL, 0x90);
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@ -255,75 +201,17 @@ static void tv_8532_setReg(struct gspca_dev *gspca_dev)
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/* mirror and digital gain */
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reg_w1(gspca_dev, R14_AD_ROW_BEGINL, 0x0a);
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reg_w1(gspca_dev, R91_AD_SLOPEREG, 0x00);
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reg_w1(gspca_dev, R94_AD_BITCONTROL, 0x02);
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reg_w1(gspca_dev, R01_TIMING_CONTROL_LOW, CMD_EEprom_Close);
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reg_w1(gspca_dev, R91_AD_SLOPEREG, 0x00);
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reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE);
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/* = 0x84 */
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}
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static void tv_8532_PollReg(struct gspca_dev *gspca_dev)
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{
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int i;
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/* strange polling from tgc */
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for (i = 0; i < 10; i++) {
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reg_w1(gspca_dev, R2C_POLARITY, 0x10);
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reg_w1(gspca_dev, R00_PART_CONTROL,
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LATENT_CHANGE | EXPO_CHANGE);
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reg_w1(gspca_dev, R31_UPD, 0x01);
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}
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}
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/* this function is called at probe and resume time */
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static int sd_init(struct gspca_dev *gspca_dev)
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{
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tv_8532WriteEEprom(gspca_dev);
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reg_w1(gspca_dev, R91_AD_SLOPEREG, 0x32); /* slope begin 1,7V,
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* slope rate 2 */
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reg_w1(gspca_dev, R94_AD_BITCONTROL, 0x00);
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tv_8532ReadRegisters(gspca_dev);
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reg_w1(gspca_dev, R3B_Test3, 0x0b);
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reg_w2(gspca_dev, R0E_AD_HEIGHTL, 0x0190);
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reg_w2(gspca_dev, R1C_AD_EXPOSE_TIMEL, 0x018f);
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reg_w1(gspca_dev, R0C_AD_WIDTHL, 0xe8);
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reg_w1(gspca_dev, R0D_AD_WIDTHH, 0x03);
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/*******************************************************************/
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reg_w1(gspca_dev, R28_QUANT, 0x90);
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/* no compress - fixed Q - quant 0 */
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reg_w1(gspca_dev, R29_LINE, 0x81);
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/* 0x84; // CIF | 4 packet 0x29 */
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/************************************************/
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reg_w1(gspca_dev, R2C_POLARITY, 0x10);
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/* 0x48; //0x08; 0x2c */
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reg_w1(gspca_dev, R2D_POINT, 0x14);
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/* 0x38; 0x2d */
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reg_w1(gspca_dev, R2E_POINTH, 0x01);
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/* 0x04; 0x2e */
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reg_w1(gspca_dev, R2F_POINTB, 0x12);
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/* 0x04; 0x2f */
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reg_w1(gspca_dev, R30_POINTBH, 0x01);
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/* 0x04; 0x30 */
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reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE);
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/* 0x00<-0x84 */
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/*************************************************/
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reg_w1(gspca_dev, R31_UPD, 0x01); /* update registers */
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msleep(200);
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reg_w1(gspca_dev, R31_UPD, 0x00); /* end update */
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/*************************************************/
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tv_8532_setReg(gspca_dev);
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/*************************************************/
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reg_w1(gspca_dev, R3B_Test3, 0x0b); /* Test0Sel = 11 = GPIO */
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/*************************************************/
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tv_8532_setReg(gspca_dev);
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/*************************************************/
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tv_8532_PollReg(gspca_dev);
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return 0;
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}
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@ -341,15 +229,6 @@ static int sd_start(struct gspca_dev *gspca_dev)
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{
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struct sd *sd = (struct sd *) gspca_dev;
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reg_w1(gspca_dev, R91_AD_SLOPEREG, 0x32); /* slope begin 1,7V,
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* slope rate 2 */
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reg_w1(gspca_dev, R94_AD_BITCONTROL, 0x00);
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tv_8532ReadRegisters(gspca_dev);
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reg_w1(gspca_dev, R3B_Test3, 0x0b);
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reg_w2(gspca_dev, R0E_AD_HEIGHTL, 0x0190);
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setbrightness(gspca_dev);
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reg_w1(gspca_dev, R0C_AD_WIDTHL, 0xe8); /* 0x20; 0x0c */
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reg_w1(gspca_dev, R0D_AD_WIDTHH, 0x03);
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@ -371,20 +250,15 @@ static int sd_start(struct gspca_dev *gspca_dev)
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reg_w1(gspca_dev, R2E_POINTH, 0x01);
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reg_w1(gspca_dev, R2F_POINTB, 0x12);
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reg_w1(gspca_dev, R30_POINTBH, 0x01);
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reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE);
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tv_8532_setReg(gspca_dev);
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setbrightness(gspca_dev);
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/************************************************/
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reg_w1(gspca_dev, R31_UPD, 0x01); /* update registers */
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msleep(200);
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reg_w1(gspca_dev, R31_UPD, 0x00); /* end update */
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/************************************************/
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tv_8532_setReg(gspca_dev);
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/************************************************/
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reg_w1(gspca_dev, R3B_Test3, 0x0b); /* Test0Sel = 11 = GPIO */
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/************************************************/
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tv_8532_setReg(gspca_dev);
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/************************************************/
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tv_8532_PollReg(gspca_dev);
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reg_w1(gspca_dev, R31_UPD, 0x00); /* end update */
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gspca_dev->empty_packet = 0; /* check the empty packets */
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sd->packet = 0; /* ignore the first packets */
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