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Merge tag 'drm-fixes-5.2-2019-07-02' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

drm-fixes-5.2-2019-07-02:

Fixes for stable

amdgpu:
- stability fix for gfx9
- regression fix for HG on some polaris boards
- crash fix for some new OEM boards

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190703015705.3162-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie 2019-07-04 11:17:23 +10:00
parent c84c9029d7 25f09f8588
commit 5ee5d30a81
5 changed files with 9 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@ -1959,25 +1959,6 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
mutex_unlock(&adev->srbm_mutex); mutex_unlock(&adev->srbm_mutex);
gfx_v9_0_init_compute_vmid(adev); gfx_v9_0_init_compute_vmid(adev);
mutex_lock(&adev->grbm_idx_mutex);
/*
* making sure that the following register writes will be broadcasted
* to all the shaders
*/
gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
(adev->gfx.config.sc_prim_fifo_size_frontend <<
PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
(adev->gfx.config.sc_prim_fifo_size_backend <<
PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
(adev->gfx.config.sc_hiz_tile_fifo_size <<
PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
(adev->gfx.config.sc_earlyz_tile_fifo_size <<
PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
mutex_unlock(&adev->grbm_idx_mutex);
} }
static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)

2
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
View File

@ -326,7 +326,7 @@ int hwmgr_resume(struct pp_hwmgr *hwmgr)
if (ret) if (ret)
return ret; return ret;
ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL); ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
return ret; return ret;
} }

4
drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
View File

@ -916,8 +916,10 @@ static int init_thermal_controller(
PHM_PlatformCaps_ThermalController PHM_PlatformCaps_ThermalController
); );
if (0 == powerplay_table->usFanTableOffset) if (0 == powerplay_table->usFanTableOffset) {
hwmgr->thermal_controller.use_hw_fan_control = 1;
return 0; return 0;
}
fan_table = (const PPTable_Generic_SubTable_Header *) fan_table = (const PPTable_Generic_SubTable_Header *)
(((unsigned long)powerplay_table) + (((unsigned long)powerplay_table) +

1
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
View File

@ -694,6 +694,7 @@ struct pp_thermal_controller_info {
uint8_t ucType; uint8_t ucType;
uint8_t ucI2cLine; uint8_t ucI2cLine;
uint8_t ucI2cAddress; uint8_t ucI2cAddress;
uint8_t use_hw_fan_control;
struct pp_fan_info fanInfo; struct pp_fan_info fanInfo;
struct pp_advance_fan_control_parameters advanceFanControlParameters; struct pp_advance_fan_control_parameters advanceFanControlParameters;
}; };

4
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
View File

@ -2092,6 +2092,10 @@ static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
return 0; return 0;
} }
/* use hardware fan control */
if (hwmgr->thermal_controller.use_hw_fan_control)
return 0;
tmp64 = hwmgr->thermal_controller.advanceFanControlParameters. tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
usPWMMin * duty100; usPWMMin * duty100;
do_div(tmp64, 10000); do_div(tmp64, 10000);