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ARM: dts: sam9x60: add rtt 

Add RTT. Allong with it enable GBPR as it is requested by RTT.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1591779936-18577-4-git-send-email-claudiu.beznea@microchip.com
This commit is contained in:
Claudiu Beznea 2020-06-10 12:05:36 +03:00 committed by Alexandre Belloni
parent 73554069de
commit 5f6b33f463
2 changed files with 16 additions and 0 deletions
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9
arch/arm/boot/dts/at91-sam9x60ek.dts
View File

@ -309,6 +309,10 @@ gpio_exp: mcp23008@20 {
};
};
&gpbr {
status = "okay";
};
&i2s {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s_default>;
@ -636,6 +640,11 @@ kernel@200000 {
};
};
&rtt {
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
status = "okay";
};
&shutdown_controller {
atmel,shdwc-debouncer = <976>;
status = "okay";

7
arch/arm/boot/dts/sam9x60.dtsi
View File

@ -661,6 +661,13 @@ shutdown_controller: shdwc@fffffe10 {
status = "disabled";
};
rtt: rtt@fffffe20 {
compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
reg = <0xfffffe20 0x20>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k 0>;
};
pit: timer@fffffe40 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe40 0x10>;