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drm/amdgpu: correct ip for mmHDP_READ_CACHE_INVALIDATE register access 

Use the proper IP index for HDP registers.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Le Ma 2019-05-20 17:04:05 +08:00 committed by Alex Deucher
parent 7d0670f441
commit 5fb7c66508
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/amdgpu/soc15.c
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@ -703,7 +703,7 @@ static void soc15_invalidate_hdp(struct amdgpu_device *adev,
struct amdgpu_ring *ring) struct amdgpu_ring *ring)
{ {
if (!ring || !ring->funcs->emit_wreg) if (!ring || !ring->funcs->emit_wreg)
WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
else else
amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);