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net: hns3: refactor interrupt coalescing init function 

In the hardware, the coalesce configurable registers include GL0, GL1,
GL2. In the driver, the TX queues use the register GL1 and the RX queues
use the register GL0. This function initializes the configuration of the
interrupt coalescing, but does not distinguish between the TX direction
and the RX direction. It will cause some confusion.

This patch refactors the function to initialize the TX GL and the RX GL
separately. And the initialization of related variables also is added to
this patch.

Signed-off-by: Fuyun Liang <liangfuyun1@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Fuyun Liang 2018-01-12 16:23:11 +08:00 committed by David S. Miller
parent 434776a5fa
commit 5fd4789a98
1 changed files with 20 additions and 9 deletions
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29
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
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@ -206,21 +206,32 @@ void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
} }
static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector) static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
struct hns3_nic_priv *priv)
{ {
struct hnae3_handle *h = priv->ae_handle;
/* initialize the configuration for interrupt coalescing. /* initialize the configuration for interrupt coalescing.
* 1. GL (Interrupt Gap Limiter) * 1. GL (Interrupt Gap Limiter)
* 2. RL (Interrupt Rate Limiter) * 2. RL (Interrupt Rate Limiter)
*/ */
/* Default :enable interrupt coalesce */ /* Default: enable interrupt coalescing self-adaptive and GL */
tqp_vector->rx_group.int_gl = HNS3_INT_GL_50K; tqp_vector->tx_group.gl_adapt_enable = 1;
tqp_vector->rx_group.gl_adapt_enable = 1;
tqp_vector->tx_group.int_gl = HNS3_INT_GL_50K; tqp_vector->tx_group.int_gl = HNS3_INT_GL_50K;
hns3_set_vector_coalesc_gl(tqp_vector, HNS3_INT_GL_50K); tqp_vector->rx_group.int_gl = HNS3_INT_GL_50K;
/* for now we are disabling Interrupt RL - we
* will re-enable later hns3_set_vector_coalesce_tx_gl(tqp_vector,
*/ tqp_vector->tx_group.int_gl);
hns3_set_vector_coalesce_rl(tqp_vector, 0); hns3_set_vector_coalesce_rx_gl(tqp_vector,
tqp_vector->rx_group.int_gl);
/* Default: disable RL */
h->kinfo.int_rl_setting = 0;
hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
tqp_vector->rx_group.flow_level = HNS3_FLOW_LOW; tqp_vector->rx_group.flow_level = HNS3_FLOW_LOW;
tqp_vector->tx_group.flow_level = HNS3_FLOW_LOW; tqp_vector->tx_group.flow_level = HNS3_FLOW_LOW;
} }
@ -2654,7 +2665,7 @@ static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
tqp_vector->rx_group.total_packets = 0; tqp_vector->rx_group.total_packets = 0;
tqp_vector->tx_group.total_bytes = 0; tqp_vector->tx_group.total_bytes = 0;
tqp_vector->tx_group.total_packets = 0; tqp_vector->tx_group.total_packets = 0;
hns3_vector_gl_rl_init(tqp_vector); hns3_vector_gl_rl_init(tqp_vector, priv);
tqp_vector->handle = h; tqp_vector->handle = h;
ret = hns3_get_vector_ring_chain(tqp_vector, ret = hns3_get_vector_ring_chain(tqp_vector,