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ARM: dts: sun9i: Add i2c controller nodes to a80 dtsi 

The A80 has 5 i2c controllers in the main processor block.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai 2014-10-31 11:05:46 +08:00 committed by Maxime Ripard
parent b8d2fef270
commit 6023ebca9c
1 changed files with 55 additions and 0 deletions
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55
arch/arm/boot/dts/sun9i-a80.dtsi
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@ -426,6 +426,61 @@ uart5: serial@07001400 {
status = "disabled"; status = "disabled";
}; };
i2c0: i2c@07002800 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07002800 0x400>;
interrupts = <0 6 4>;
clocks = <&apb1_gates 0>;
resets = <&apb1_resets 0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@07002c00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07002c00 0x400>;
interrupts = <0 7 4>;
clocks = <&apb1_gates 1>;
resets = <&apb1_resets 1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@07003000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003000 0x400>;
interrupts = <0 8 4>;
clocks = <&apb1_gates 2>;
resets = <&apb1_resets 2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c3: i2c@07003400 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003400 0x400>;
interrupts = <0 9 4>;
clocks = <&apb1_gates 3>;
resets = <&apb1_resets 3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c4: i2c@07003800 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003800 0x400>;
interrupts = <0 10 4>;
clocks = <&apb1_gates 4>;
resets = <&apb1_resets 4>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
r_wdt: watchdog@08001000 { r_wdt: watchdog@08001000 {
compatible = "allwinner,sun6i-a31-wdt"; compatible = "allwinner,sun6i-a31-wdt";
reg = <0x08001000 0x20>; reg = <0x08001000 0x20>;