mirror of https://gitee.com/openkylin/linux.git
pinctrl: SPEAr: Add plgpio driver
Most of SPEAr SoCs, which support pinctrl, can configure & use pads as gpio. This patch adds plgpio driver for configuring these pads as gpio. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Viresh Kumar
Linus Walleij
parent
f23f1516b6
commit
604bb7da77
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@ -41,4 +41,11 @@ config PINCTRL_SPEAR1340
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depends on MACH_SPEAR1340
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select PINCTRL_SPEAR
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config PINCTRL_SPEAR_PLGPIO
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bool "SPEAr SoC PLGPIO Controller"
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depends on GPIOLIB && PINCTRL_SPEAR
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help
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Say yes here to support PLGPIO controller on ST Microelectronics SPEAr
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SoCs.
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endif
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@ -1,5 +1,6 @@
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# SPEAr pinmux support
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obj-$(CONFIG_PINCTRL_SPEAR_PLGPIO) += pinctrl-plgpio.o
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obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o
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obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o
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obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o
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@ -0,0 +1,746 @@
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/*
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* SPEAr platform PLGPIO driver
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*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <viresh.kumar@linaro.org>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/spinlock.h>
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#include <asm/mach/irq.h>
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#define MAX_GPIO_PER_REG 32
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#define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
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#define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \
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* sizeof(int *))
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/*
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* plgpio pins in all machines are not one to one mapped, bitwise with registers
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* bits. These set of macros define register masks for which below functions
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* (pin_to_offset and offset_to_pin) are required to be called.
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*/
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#define PTO_ENB_REG 0x001
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#define PTO_WDATA_REG 0x002
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#define PTO_DIR_REG 0x004
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#define PTO_IE_REG 0x008
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#define PTO_RDATA_REG 0x010
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#define PTO_MIS_REG 0x020
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struct plgpio_regs {
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u32 enb; /* enable register */
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u32 wdata; /* write data register */
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u32 dir; /* direction set register */
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u32 rdata; /* read data register */
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u32 ie; /* interrupt enable register */
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u32 mis; /* mask interrupt status register */
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u32 eit; /* edge interrupt type */
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};
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/*
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* struct plgpio: plgpio driver specific structure
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*
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* lock: lock for guarding gpio registers
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* base: base address of plgpio block
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* irq_base: irq number of plgpio0
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* chip: gpio framework specific chip information structure
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* p2o: function ptr for pin to offset conversion. This is required only for
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* machines where mapping b/w pin and offset is not 1-to-1.
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* o2p: function ptr for offset to pin conversion. This is required only for
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* machines where mapping b/w pin and offset is not 1-to-1.
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* p2o_regs: mask of registers for which p2o and o2p are applicable
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* regs: register offsets
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* csave_regs: context save registers for standby/sleep/hibernate cases
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*/
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struct plgpio {
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spinlock_t lock;
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void __iomem *base;
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struct clk *clk;
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unsigned irq_base;
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struct irq_domain *irq_domain;
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struct gpio_chip chip;
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int (*p2o)(int pin); /* pin_to_offset */
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int (*o2p)(int offset); /* offset_to_pin */
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u32 p2o_regs;
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struct plgpio_regs regs;
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#ifdef CONFIG_PM
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struct plgpio_regs *csave_regs;
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#endif
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};
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/* register manipulation inline functions */
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static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg)
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{
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u32 offset = PIN_OFFSET(pin);
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void __iomem *reg_off = REG_OFFSET(base, reg, pin);
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u32 val = readl_relaxed(reg_off);
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return !!(val & (1 << offset));
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}
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static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg)
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{
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u32 offset = PIN_OFFSET(pin);
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void __iomem *reg_off = REG_OFFSET(base, reg, pin);
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u32 val = readl_relaxed(reg_off);
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writel_relaxed(val | (1 << offset), reg_off);
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}
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static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg)
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{
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u32 offset = PIN_OFFSET(pin);
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void __iomem *reg_off = REG_OFFSET(base, reg, pin);
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u32 val = readl_relaxed(reg_off);
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writel_relaxed(val & ~(1 << offset), reg_off);
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}
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/* gpio framework specific routines */
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static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
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unsigned long flags;
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/* get correct offset for "offset" pin */
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) {
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offset = plgpio->p2o(offset);
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if (offset == -1)
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return -EINVAL;
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}
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spin_lock_irqsave(&plgpio->lock, flags);
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plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir);
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spin_unlock_irqrestore(&plgpio->lock, flags);
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return 0;
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}
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static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
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unsigned long flags;
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unsigned dir_offset = offset, wdata_offset = offset, tmp;
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/* get correct offset for "offset" pin */
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if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) {
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tmp = plgpio->p2o(offset);
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if (tmp == -1)
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return -EINVAL;
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if (plgpio->p2o_regs & PTO_DIR_REG)
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dir_offset = tmp;
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if (plgpio->p2o_regs & PTO_WDATA_REG)
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wdata_offset = tmp;
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}
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spin_lock_irqsave(&plgpio->lock, flags);
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if (value)
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plgpio_reg_set(plgpio->base, wdata_offset,
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plgpio->regs.wdata);
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else
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plgpio_reg_reset(plgpio->base, wdata_offset,
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plgpio->regs.wdata);
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plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir);
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spin_unlock_irqrestore(&plgpio->lock, flags);
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return 0;
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}
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static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
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{
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struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
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if (offset >= chip->ngpio)
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return -EINVAL;
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/* get correct offset for "offset" pin */
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) {
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offset = plgpio->p2o(offset);
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if (offset == -1)
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return -EINVAL;
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}
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return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata);
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}
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static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
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if (offset >= chip->ngpio)
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return;
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/* get correct offset for "offset" pin */
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) {
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offset = plgpio->p2o(offset);
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if (offset == -1)
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return;
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}
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if (value)
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plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata);
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else
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plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata);
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}
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static int plgpio_request(struct gpio_chip *chip, unsigned offset)
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{
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struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
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int gpio = chip->base + offset;
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unsigned long flags;
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int ret = 0;
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if (offset >= chip->ngpio)
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return -EINVAL;
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ret = pinctrl_request_gpio(gpio);
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if (ret)
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return ret;
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if (!IS_ERR(plgpio->clk)) {
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ret = clk_prepare_enable(plgpio->clk);
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if (ret)
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goto err0;
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}
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if (plgpio->regs.enb == -1)
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return 0;
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/*
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* put gpio in IN mode before enabling it. This make enabling gpio safe
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*/
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ret = plgpio_direction_input(chip, offset);
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if (ret)
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goto err1;
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/* get correct offset for "offset" pin */
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
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offset = plgpio->p2o(offset);
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if (offset == -1) {
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ret = -EINVAL;
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goto err1;
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}
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}
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spin_lock_irqsave(&plgpio->lock, flags);
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plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb);
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spin_unlock_irqrestore(&plgpio->lock, flags);
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return 0;
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err1:
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clk_disable_unprepare(plgpio->clk);
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err0:
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pinctrl_free_gpio(gpio);
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return ret;
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}
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static void plgpio_free(struct gpio_chip *chip, unsigned offset)
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{
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struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
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int gpio = chip->base + offset;
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unsigned long flags;
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if (offset >= chip->ngpio)
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return;
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if (plgpio->regs.enb == -1)
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goto disable_clk;
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/* get correct offset for "offset" pin */
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
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offset = plgpio->p2o(offset);
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if (offset == -1)
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return;
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}
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spin_lock_irqsave(&plgpio->lock, flags);
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plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb);
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spin_unlock_irqrestore(&plgpio->lock, flags);
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disable_clk:
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if (!IS_ERR(plgpio->clk))
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clk_disable_unprepare(plgpio->clk);
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pinctrl_free_gpio(gpio);
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}
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static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
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if (plgpio->irq_base < 0)
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return -EINVAL;
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return irq_find_mapping(plgpio->irq_domain, offset);
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}
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/* PLGPIO IRQ */
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static void plgpio_irq_disable(struct irq_data *d)
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{
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struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
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int offset = d->irq - plgpio->irq_base;
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unsigned long flags;
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/* get correct offset for "offset" pin */
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
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offset = plgpio->p2o(offset);
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if (offset == -1)
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return;
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}
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spin_lock_irqsave(&plgpio->lock, flags);
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plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie);
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spin_unlock_irqrestore(&plgpio->lock, flags);
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}
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static void plgpio_irq_enable(struct irq_data *d)
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{
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struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
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int offset = d->irq - plgpio->irq_base;
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unsigned long flags;
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/* get correct offset for "offset" pin */
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
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offset = plgpio->p2o(offset);
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if (offset == -1)
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return;
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}
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spin_lock_irqsave(&plgpio->lock, flags);
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plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie);
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spin_unlock_irqrestore(&plgpio->lock, flags);
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}
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static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
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{
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struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
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int offset = d->irq - plgpio->irq_base;
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void __iomem *reg_off;
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unsigned int supported_type = 0, val;
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if (offset >= plgpio->chip.ngpio)
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return -EINVAL;
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if (plgpio->regs.eit == -1)
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supported_type = IRQ_TYPE_LEVEL_HIGH;
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else
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supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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if (!(trigger & supported_type))
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return -EINVAL;
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if (plgpio->regs.eit == -1)
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return 0;
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reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset);
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val = readl_relaxed(reg_off);
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offset = PIN_OFFSET(offset);
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if (trigger & IRQ_TYPE_EDGE_RISING)
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writel_relaxed(val | (1 << offset), reg_off);
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else
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writel_relaxed(val & ~(1 << offset), reg_off);
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return 0;
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}
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static struct irq_chip plgpio_irqchip = {
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.name = "PLGPIO",
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.irq_enable = plgpio_irq_enable,
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.irq_disable = plgpio_irq_disable,
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.irq_set_type = plgpio_irq_set_type,
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};
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static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct plgpio *plgpio = irq_get_handler_data(irq);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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int regs_count, count, pin, offset, i = 0;
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unsigned long pending;
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count = plgpio->chip.ngpio;
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regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG);
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chained_irq_enter(irqchip, desc);
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/* check all plgpio MIS registers for a possible interrupt */
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for (; i < regs_count; i++) {
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pending = readl_relaxed(plgpio->base + plgpio->regs.mis +
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i * sizeof(int *));
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if (!pending)
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continue;
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/* clear interrupts */
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writel_relaxed(~pending, plgpio->base + plgpio->regs.mis +
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i * sizeof(int *));
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/*
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* clear extra bits in last register having gpios < MAX/REG
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* ex: Suppose there are max 102 plgpios. then last register
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* must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits
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* so, we must not take other 28 bits into consideration for
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* checking interrupt. so clear those bits.
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*/
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count = count - i * MAX_GPIO_PER_REG;
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if (count < MAX_GPIO_PER_REG)
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pending &= (1 << count) - 1;
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for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) {
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/* get correct pin for "offset" */
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if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) {
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pin = plgpio->o2p(offset);
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if (pin == -1)
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continue;
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} else
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pin = offset;
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/* get correct irq line number */
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pin = i * MAX_GPIO_PER_REG + pin;
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generic_handle_irq(plgpio_to_irq(&plgpio->chip, pin));
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}
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}
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chained_irq_exit(irqchip, desc);
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}
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/*
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* pin to offset and offset to pin converter functions
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*
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* In spear310 there is inconsistency among bit positions in plgpio regiseters,
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* for different plgpio pins. For example: for pin 27, bit offset is 23, pin
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* 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1
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*/
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static int spear310_p2o(int pin)
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{
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int offset = pin;
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if (pin <= 27)
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offset += 4;
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else if (pin <= 33)
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offset = -1;
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else if (pin <= 97)
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offset -= 2;
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else if (pin <= 101)
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offset = 101 - pin;
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else
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offset = -1;
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return offset;
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}
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int spear310_o2p(int offset)
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{
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if (offset <= 3)
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return 101 - offset;
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else if (offset <= 31)
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return offset - 4;
|
||||
else
|
||||
return offset + 2;
|
||||
}
|
||||
|
||||
static int __devinit plgpio_probe_dt(struct platform_device *pdev,
|
||||
struct plgpio *plgpio)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
int ret = -EINVAL;
|
||||
u32 val;
|
||||
|
||||
if (of_machine_is_compatible("st,spear310")) {
|
||||
plgpio->p2o = spear310_p2o;
|
||||
plgpio->o2p = spear310_o2p;
|
||||
plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG |
|
||||
PTO_RDATA_REG | PTO_MIS_REG;
|
||||
}
|
||||
|
||||
if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) {
|
||||
plgpio->chip.ngpio = val;
|
||||
} else {
|
||||
dev_err(&pdev->dev, "DT: Invalid ngpio field\n");
|
||||
goto end;
|
||||
}
|
||||
|
||||
if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val))
|
||||
plgpio->regs.enb = val;
|
||||
else
|
||||
plgpio->regs.enb = -1;
|
||||
|
||||
if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) {
|
||||
plgpio->regs.wdata = val;
|
||||
} else {
|
||||
dev_err(&pdev->dev, "DT: Invalid wdata reg\n");
|
||||
goto end;
|
||||
}
|
||||
|
||||
if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) {
|
||||
plgpio->regs.dir = val;
|
||||
} else {
|
||||
dev_err(&pdev->dev, "DT: Invalid dir reg\n");
|
||||
goto end;
|
||||
}
|
||||
|
||||
if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) {
|
||||
plgpio->regs.ie = val;
|
||||
} else {
|
||||
dev_err(&pdev->dev, "DT: Invalid ie reg\n");
|
||||
goto end;
|
||||
}
|
||||
|
||||
if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) {
|
||||
plgpio->regs.rdata = val;
|
||||
} else {
|
||||
dev_err(&pdev->dev, "DT: Invalid rdata reg\n");
|
||||
goto end;
|
||||
}
|
||||
|
||||
if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) {
|
||||
plgpio->regs.mis = val;
|
||||
} else {
|
||||
dev_err(&pdev->dev, "DT: Invalid mis reg\n");
|
||||
goto end;
|
||||
}
|
||||
|
||||
if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val))
|
||||
plgpio->regs.eit = val;
|
||||
else
|
||||
plgpio->regs.eit = -1;
|
||||
|
||||
return 0;
|
||||
|
||||
end:
|
||||
return ret;
|
||||
}
|
||||
static int __devinit plgpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct plgpio *plgpio;
|
||||
struct resource *res;
|
||||
int ret, irq, i;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "invalid IORESOURCE_MEM\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
|
||||
if (!plgpio) {
|
||||
dev_err(&pdev->dev, "memory allocation fail\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
plgpio->base = devm_request_and_ioremap(&pdev->dev, res);
|
||||
if (!plgpio->base) {
|
||||
dev_err(&pdev->dev, "request and ioremap fail\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = plgpio_probe_dt(pdev, plgpio);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "DT probe failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
plgpio->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(plgpio->clk))
|
||||
dev_warn(&pdev->dev, "clk_get() failed, work without it\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
plgpio->csave_regs = devm_kzalloc(&pdev->dev,
|
||||
sizeof(*plgpio->csave_regs) *
|
||||
DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG),
|
||||
GFP_KERNEL);
|
||||
if (!plgpio->csave_regs) {
|
||||
dev_err(&pdev->dev, "csave registers memory allocation fail\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
#endif
|
||||
|
||||
platform_set_drvdata(pdev, plgpio);
|
||||
spin_lock_init(&plgpio->lock);
|
||||
|
||||
plgpio->irq_base = -1;
|
||||
plgpio->chip.base = -1;
|
||||
plgpio->chip.request = plgpio_request;
|
||||
plgpio->chip.free = plgpio_free;
|
||||
plgpio->chip.direction_input = plgpio_direction_input;
|
||||
plgpio->chip.direction_output = plgpio_direction_output;
|
||||
plgpio->chip.get = plgpio_get_value;
|
||||
plgpio->chip.set = plgpio_set_value;
|
||||
plgpio->chip.to_irq = plgpio_to_irq;
|
||||
plgpio->chip.label = dev_name(&pdev->dev);
|
||||
plgpio->chip.dev = &pdev->dev;
|
||||
plgpio->chip.owner = THIS_MODULE;
|
||||
|
||||
ret = gpiochip_add(&plgpio->chip);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "unable to add gpio chip\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_info(&pdev->dev, "irqs not supported\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
plgpio->irq_base = irq_alloc_descs(-1, 0, plgpio->chip.ngpio, 0);
|
||||
if (IS_ERR_VALUE(plgpio->irq_base)) {
|
||||
/* we would not support irq for gpio */
|
||||
dev_warn(&pdev->dev, "couldn't allocate irq base\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
plgpio->irq_domain = irq_domain_add_legacy(np, plgpio->chip.ngpio,
|
||||
plgpio->irq_base, 0, &irq_domain_simple_ops, NULL);
|
||||
if (WARN_ON(!plgpio->irq_domain)) {
|
||||
dev_err(&pdev->dev, "irq domain init failed\n");
|
||||
irq_free_descs(plgpio->irq_base, plgpio->chip.ngpio);
|
||||
ret = -ENXIO;
|
||||
goto remove_gpiochip;
|
||||
}
|
||||
|
||||
irq_set_chained_handler(irq, plgpio_irq_handler);
|
||||
for (i = 0; i < plgpio->chip.ngpio; i++) {
|
||||
irq_set_chip_and_handler(i + plgpio->irq_base, &plgpio_irqchip,
|
||||
handle_simple_irq);
|
||||
set_irq_flags(i + plgpio->irq_base, IRQF_VALID);
|
||||
irq_set_chip_data(i + plgpio->irq_base, plgpio);
|
||||
}
|
||||
|
||||
irq_set_handler_data(irq, plgpio);
|
||||
dev_info(&pdev->dev, "PLGPIO registered with IRQs\n");
|
||||
|
||||
return 0;
|
||||
|
||||
remove_gpiochip:
|
||||
dev_info(&pdev->dev, "Remove gpiochip\n");
|
||||
if (gpiochip_remove(&plgpio->chip))
|
||||
dev_err(&pdev->dev, "unable to remove gpiochip\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int plgpio_suspend(struct device *dev)
|
||||
{
|
||||
struct plgpio *plgpio = dev_get_drvdata(dev);
|
||||
int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
|
||||
void __iomem *off;
|
||||
|
||||
for (i = 0; i < reg_count; i++) {
|
||||
off = plgpio->base + i * sizeof(int *);
|
||||
|
||||
if (plgpio->regs.enb != -1)
|
||||
plgpio->csave_regs[i].enb =
|
||||
readl_relaxed(plgpio->regs.enb + off);
|
||||
if (plgpio->regs.eit != -1)
|
||||
plgpio->csave_regs[i].eit =
|
||||
readl_relaxed(plgpio->regs.eit + off);
|
||||
plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata +
|
||||
off);
|
||||
plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir +
|
||||
off);
|
||||
plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This is used to correct the values in end registers. End registers contain
|
||||
* extra bits that might be used for other purpose in platform. So, we shouldn't
|
||||
* overwrite these bits. This macro, reads given register again, preserves other
|
||||
* bit values (non-plgpio bits), and retain captured value (plgpio bits).
|
||||
*/
|
||||
#define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \
|
||||
{ \
|
||||
_tmp = readl_relaxed(plgpio->regs.__reg + _off); \
|
||||
_tmp &= ~_mask; \
|
||||
plgpio->csave_regs[i].__reg = \
|
||||
_tmp | (plgpio->csave_regs[i].__reg & _mask); \
|
||||
}
|
||||
|
||||
static int plgpio_resume(struct device *dev)
|
||||
{
|
||||
struct plgpio *plgpio = dev_get_drvdata(dev);
|
||||
int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
|
||||
void __iomem *off;
|
||||
u32 mask, tmp;
|
||||
|
||||
for (i = 0; i < reg_count; i++) {
|
||||
off = plgpio->base + i * sizeof(int *);
|
||||
|
||||
if (i == reg_count - 1) {
|
||||
mask = (1 << (plgpio->chip.ngpio - i *
|
||||
MAX_GPIO_PER_REG)) - 1;
|
||||
|
||||
if (plgpio->regs.enb != -1)
|
||||
plgpio_prepare_reg(enb, off, mask, tmp);
|
||||
|
||||
if (plgpio->regs.eit != -1)
|
||||
plgpio_prepare_reg(eit, off, mask, tmp);
|
||||
|
||||
plgpio_prepare_reg(wdata, off, mask, tmp);
|
||||
plgpio_prepare_reg(dir, off, mask, tmp);
|
||||
plgpio_prepare_reg(ie, off, mask, tmp);
|
||||
}
|
||||
|
||||
writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata +
|
||||
off);
|
||||
writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir +
|
||||
off);
|
||||
|
||||
if (plgpio->regs.eit != -1)
|
||||
writel_relaxed(plgpio->csave_regs[i].eit,
|
||||
plgpio->regs.eit + off);
|
||||
|
||||
writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off);
|
||||
|
||||
if (plgpio->regs.enb != -1)
|
||||
writel_relaxed(plgpio->csave_regs[i].enb,
|
||||
plgpio->regs.enb + off);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume);
|
||||
|
||||
static const struct of_device_id plgpio_of_match[] = {
|
||||
{ .compatible = "st,spear-plgpio" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, plgpio_of_match);
|
||||
|
||||
static struct platform_driver plgpio_driver = {
|
||||
.probe = plgpio_probe,
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "spear-plgpio",
|
||||
.pm = &plgpio_dev_pm_ops,
|
||||
.of_match_table = of_match_ptr(plgpio_of_match),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plgpio_init(void)
|
||||
{
|
||||
return platform_driver_register(&plgpio_driver);
|
||||
}
|
||||
subsys_initcall(plgpio_init);
|
||||
|
||||
MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
|
||||
MODULE_DESCRIPTION("ST Microlectronics SPEAr PLGPIO driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue