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gpio: cadence: Pass irqchip when adding gpiochip 

We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Jan Kotas <jank@cadence.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Jan Kotas <jank@cadence.com>
Link: https://lore.kernel.org/r/20190809131804.20352-1-linus.walleij@linaro.org
This commit is contained in:
Linus Walleij 2019-08-09 15:18:04 +02:00
parent a7fc89f9d5
commit 607a0dcddb
1 changed files with 23 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
drivers/gpio/gpio-cadence.c
View File

@ -214,29 +214,35 @@ static int cdns_gpio_probe(struct platform_device *pdev)
goto err_revert_dir;
}
/*
* Optional irq_chip support
*/
irq = platform_get_irq(pdev, 0);
if (irq >= 0) {
struct gpio_irq_chip *girq;
girq = &cgpio->gc.irq;
girq->chip = &cdns_gpio_irqchip;
girq->parent_handler = cdns_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(&pdev->dev, 1,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents) {
ret = -ENOMEM;
goto err_disable_clk;
}
girq->parents[0] = irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
}
ret = devm_gpiochip_add_data(&pdev->dev, &cgpio->gc, cgpio);
if (ret < 0) {
dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
goto err_disable_clk;
}
/*
* irq_chip support
*/
irq = platform_get_irq(pdev, 0);
if (irq >= 0) {
ret = gpiochip_irqchip_add(&cgpio->gc, &cdns_gpio_irqchip,
0, handle_level_irq,
IRQ_TYPE_NONE);
if (ret) {
dev_err(&pdev->dev, "Could not add irqchip, %d\n",
ret);
goto err_disable_clk;
}
gpiochip_set_chained_irqchip(&cgpio->gc, &cdns_gpio_irqchip,
irq, cdns_gpio_irq_handler);
}
cgpio->bypass_orig = ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE);
/*