mirror of https://gitee.com/openkylin/linux.git
ASoC: tegra: add ac97 host driver
This adds the driver for the Tegra 2x AC97 host controller. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Lucas Stach
Mark Brown
parent
15fab58507
commit
609dad9bdf
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@ -0,0 +1,22 @@
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NVIDIA Tegra 20 AC97 controller
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Required properties:
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- compatible : "nvidia,tegra20-ac97"
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- reg : Should contain AC97 controller registers location and length
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- interrupts : Should contain AC97 interrupt
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- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
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request selector for the AC97 controller
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- nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
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of the GPIO used to reset the external AC97 codec
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- nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number
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of the GPIO corresponding with the AC97 DAP _FS line
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Example:
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ac97@70002000 {
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compatible = "nvidia,tegra20-ac97";
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reg = <0x70002000 0x200>;
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interrupts = <0 81 0x04>;
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nvidia,dma-request-selector = <&apbdma 12>;
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nvidia,codec-reset-gpio = <&gpio 170 0>;
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nvidia,codec-sync-gpio = <&gpio 120 0>;
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};
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@ -6,6 +6,16 @@ config SND_SOC_TEGRA
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help
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Say Y or M here if you want support for SoC audio on Tegra.
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config SND_SOC_TEGRA20_AC97
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tristate
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depends on SND_SOC_TEGRA && ARCH_TEGRA_2x_SOC
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select SND_SOC_AC97_BUS
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select SND_SOC_TEGRA20_DAS
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help
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Say Y or M if you want to add support for codecs attached to the
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Tegra20 AC97 interface. You will also need to select the individual
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machine drivers to support below.
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config SND_SOC_TEGRA20_DAS
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tristate
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depends on SND_SOC_TEGRA && ARCH_TEGRA_2x_SOC
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@ -1,6 +1,7 @@
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# Tegra platform Support
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snd-soc-tegra-pcm-objs := tegra_pcm.o
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snd-soc-tegra-utils-objs += tegra_asoc_utils.o
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snd-soc-tegra20-ac97-objs := tegra20_ac97.o
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snd-soc-tegra20-das-objs := tegra20_das.o
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snd-soc-tegra20-i2s-objs := tegra20_i2s.o
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snd-soc-tegra20-spdif-objs := tegra20_spdif.o
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@ -9,6 +10,7 @@ snd-soc-tegra30-i2s-objs := tegra30_i2s.o
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obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-pcm.o
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obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-utils.o
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obj-$(CONFIG_SND_SOC_TEGRA20_AC97) += snd-soc-tegra20-ac97.o
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obj-$(CONFIG_SND_SOC_TEGRA20_DAS) += snd-soc-tegra20-das.o
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obj-$(CONFIG_SND_SOC_TEGRA20_I2S) += snd-soc-tegra20-i2s.o
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obj-$(CONFIG_SND_SOC_TEGRA20_SPDIF) += snd-soc-tegra20-spdif.o
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@ -0,0 +1,480 @@
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/*
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* tegra20_ac97.c - Tegra20 AC97 platform driver
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*
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* Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
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*
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* Partly based on code copyright/by:
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*
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* Copyright (c) 2011,2012 Toradex Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "tegra_asoc_utils.h"
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#include "tegra20_ac97.h"
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#define DRV_NAME "tegra20-ac97"
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static struct tegra20_ac97 *workdata;
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static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
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{
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u32 readback;
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unsigned long timeout;
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/* reset line is not driven by DAC pad group, have to toggle GPIO */
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gpio_set_value(workdata->reset_gpio, 0);
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udelay(2);
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gpio_set_value(workdata->reset_gpio, 1);
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udelay(2);
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timeout = jiffies + msecs_to_jiffies(100);
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do {
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regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
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if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
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break;
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usleep_range(1000, 2000);
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} while (!time_after(jiffies, timeout));
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}
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static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97)
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{
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u32 readback;
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unsigned long timeout;
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/*
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* although sync line is driven by the DAC pad group warm reset using
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* the controller cmd is not working, have to toggle sync line
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* manually.
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*/
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gpio_request(workdata->sync_gpio, "codec-sync");
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gpio_direction_output(workdata->sync_gpio, 1);
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udelay(2);
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gpio_set_value(workdata->sync_gpio, 0);
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udelay(2);
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gpio_free(workdata->sync_gpio);
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timeout = jiffies + msecs_to_jiffies(100);
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do {
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regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
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if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
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break;
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usleep_range(1000, 2000);
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} while (!time_after(jiffies, timeout));
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}
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static unsigned short tegra20_ac97_codec_read(struct snd_ac97 *ac97_snd,
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unsigned short reg)
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{
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u32 readback;
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unsigned long timeout;
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regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
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(((reg | 0x80) << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
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TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
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TEGRA20_AC97_CMD_BUSY);
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timeout = jiffies + msecs_to_jiffies(100);
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do {
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regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
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if (readback & TEGRA20_AC97_STATUS1_STA_VALID1)
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break;
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usleep_range(1000, 2000);
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} while (!time_after(jiffies, timeout));
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return ((readback & TEGRA20_AC97_STATUS1_STA_DATA1_MASK) >>
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TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT);
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}
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static void tegra20_ac97_codec_write(struct snd_ac97 *ac97_snd,
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unsigned short reg, unsigned short val)
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{
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u32 readback;
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unsigned long timeout;
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regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
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((reg << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
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TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
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((val << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) &
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TEGRA20_AC97_CMD_CMD_DATA_MASK) |
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TEGRA20_AC97_CMD_BUSY);
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timeout = jiffies + msecs_to_jiffies(100);
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do {
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regmap_read(workdata->regmap, TEGRA20_AC97_CMD, &readback);
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if (!(readback & TEGRA20_AC97_CMD_BUSY))
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break;
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usleep_range(1000, 2000);
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} while (!time_after(jiffies, timeout));
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}
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struct snd_ac97_bus_ops soc_ac97_ops = {
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.read = tegra20_ac97_codec_read,
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.write = tegra20_ac97_codec_write,
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.reset = tegra20_ac97_codec_reset,
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.warm_reset = tegra20_ac97_codec_warm_reset,
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};
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EXPORT_SYMBOL_GPL(soc_ac97_ops);
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static inline void tegra20_ac97_start_playback(struct tegra20_ac97 *ac97)
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{
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regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
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TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN,
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TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN);
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regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
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TEGRA20_AC97_CTRL_PCM_DAC_EN |
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TEGRA20_AC97_CTRL_STM_EN,
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TEGRA20_AC97_CTRL_PCM_DAC_EN |
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TEGRA20_AC97_CTRL_STM_EN);
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}
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static inline void tegra20_ac97_stop_playback(struct tegra20_ac97 *ac97)
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{
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regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
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TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN, 0);
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regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
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TEGRA20_AC97_CTRL_PCM_DAC_EN, 0);
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}
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static inline void tegra20_ac97_start_capture(struct tegra20_ac97 *ac97)
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{
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regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
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TEGRA20_AC97_FIFO_SCR_REC_FULL_EN,
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TEGRA20_AC97_FIFO_SCR_REC_FULL_EN);
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}
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static inline void tegra20_ac97_stop_capture(struct tegra20_ac97 *ac97)
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{
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regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
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TEGRA20_AC97_FIFO_SCR_REC_FULL_EN, 0);
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}
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static int tegra20_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_RESUME:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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tegra20_ac97_start_playback(ac97);
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else
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tegra20_ac97_start_capture(ac97);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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tegra20_ac97_stop_playback(ac97);
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else
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tegra20_ac97_stop_capture(ac97);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct snd_soc_dai_ops tegra20_ac97_dai_ops = {
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.trigger = tegra20_ac97_trigger,
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};
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static int tegra20_ac97_probe(struct snd_soc_dai *dai)
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{
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struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
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dai->capture_dma_data = &ac97->capture_dma_data;
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dai->playback_dma_data = &ac97->playback_dma_data;
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return 0;
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}
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static struct snd_soc_dai_driver tegra20_ac97_dai = {
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.name = "tegra-ac97-pcm",
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.ac97_control = 1,
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.probe = tegra20_ac97_probe,
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.playback = {
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.stream_name = "PCM Playback",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.capture = {
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.stream_name = "PCM Capture",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.ops = &tegra20_ac97_dai_ops,
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};
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static bool tegra20_ac97_wr_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA20_AC97_CTRL:
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case TEGRA20_AC97_CMD:
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case TEGRA20_AC97_STATUS1:
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case TEGRA20_AC97_FIFO1_SCR:
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case TEGRA20_AC97_FIFO_TX1:
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case TEGRA20_AC97_FIFO_RX1:
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return true;
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default:
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break;
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}
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return false;
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}
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static bool tegra20_ac97_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA20_AC97_STATUS1:
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case TEGRA20_AC97_FIFO1_SCR:
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case TEGRA20_AC97_FIFO_TX1:
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case TEGRA20_AC97_FIFO_RX1:
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return true;
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default:
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break;
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}
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return false;
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}
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static bool tegra20_ac97_precious_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA20_AC97_FIFO_TX1:
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case TEGRA20_AC97_FIFO_RX1:
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return true;
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default:
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break;
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}
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return false;
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}
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static const struct regmap_config tegra20_ac97_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = TEGRA20_AC97_FIFO_RX1,
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.writeable_reg = tegra20_ac97_wr_rd_reg,
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.readable_reg = tegra20_ac97_wr_rd_reg,
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.volatile_reg = tegra20_ac97_volatile_reg,
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.precious_reg = tegra20_ac97_precious_reg,
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.cache_type = REGCACHE_RBTREE,
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};
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static int tegra20_ac97_platform_probe(struct platform_device *pdev)
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{
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struct tegra20_ac97 *ac97;
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struct resource *mem, *memregion;
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u32 of_dma[2];
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void __iomem *regs;
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int ret = 0;
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ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97),
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GFP_KERNEL);
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if (!ac97) {
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dev_err(&pdev->dev, "Can't allocate tegra20_ac97\n");
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ret = -ENOMEM;
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goto err;
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}
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dev_set_drvdata(&pdev->dev, ac97);
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ac97->clk_ac97 = clk_get(&pdev->dev, NULL);
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if (IS_ERR(ac97->clk_ac97)) {
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dev_err(&pdev->dev, "Can't retrieve ac97 clock\n");
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ret = PTR_ERR(ac97->clk_ac97);
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goto err;
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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dev_err(&pdev->dev, "No memory resource\n");
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ret = -ENODEV;
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goto err_clk_put;
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}
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memregion = devm_request_mem_region(&pdev->dev, mem->start,
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resource_size(mem), DRV_NAME);
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if (!memregion) {
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dev_err(&pdev->dev, "Memory region already claimed\n");
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ret = -EBUSY;
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goto err_clk_put;
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}
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regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
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if (!regs) {
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dev_err(&pdev->dev, "ioremap failed\n");
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ret = -ENOMEM;
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goto err_clk_put;
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}
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ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
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&tegra20_ac97_regmap_config);
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if (IS_ERR(ac97->regmap)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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ret = PTR_ERR(ac97->regmap);
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goto err_clk_put;
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}
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if (of_property_read_u32_array(pdev->dev.of_node,
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"nvidia,dma-request-selector",
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of_dma, 2) < 0) {
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dev_err(&pdev->dev, "No DMA resource\n");
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ret = -ENODEV;
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goto err_clk_put;
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}
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ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
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"nvidia,codec-reset-gpio", 0);
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if (gpio_is_valid(ac97->reset_gpio)) {
|
||||
ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio,
|
||||
GPIOF_OUT_INIT_HIGH, "codec-reset");
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "could not get codec-reset GPIO\n");
|
||||
goto err_clk_put;
|
||||
}
|
||||
} else {
|
||||
dev_err(&pdev->dev, "no codec-reset GPIO supplied\n");
|
||||
goto err_clk_put;
|
||||
}
|
||||
|
||||
ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
|
||||
"nvidia,codec-sync-gpio", 0);
|
||||
if (!gpio_is_valid(ac97->sync_gpio)) {
|
||||
dev_err(&pdev->dev, "no codec-sync GPIO supplied\n");
|
||||
goto err_clk_put;
|
||||
}
|
||||
|
||||
ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
|
||||
ac97->capture_dma_data.wrap = 4;
|
||||
ac97->capture_dma_data.width = 32;
|
||||
ac97->capture_dma_data.req_sel = of_dma[1];
|
||||
|
||||
ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
|
||||
ac97->playback_dma_data.wrap = 4;
|
||||
ac97->playback_dma_data.width = 32;
|
||||
ac97->playback_dma_data.req_sel = of_dma[1];
|
||||
|
||||
ret = snd_soc_register_dais(&pdev->dev, &tegra20_ac97_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
|
||||
ret = -ENOMEM;
|
||||
goto err_clk_put;
|
||||
}
|
||||
|
||||
ret = tegra_pcm_platform_register(&pdev->dev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
|
||||
goto err_unregister_dai;
|
||||
}
|
||||
|
||||
ret = tegra_asoc_utils_init(&ac97->util_data, &pdev->dev);
|
||||
if (ret)
|
||||
goto err_unregister_pcm;
|
||||
|
||||
ret = tegra_asoc_utils_set_ac97_rate(&ac97->util_data);
|
||||
if (ret)
|
||||
goto err_asoc_utils_fini;
|
||||
|
||||
ret = clk_prepare_enable(ac97->clk_ac97);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "clk_enable failed: %d\n", ret);
|
||||
goto err_asoc_utils_fini;
|
||||
}
|
||||
|
||||
/* XXX: crufty ASoC AC97 API - only one AC97 codec allowed */
|
||||
workdata = ac97;
|
||||
|
||||
return 0;
|
||||
|
||||
err_asoc_utils_fini:
|
||||
tegra_asoc_utils_fini(&ac97->util_data);
|
||||
err_unregister_pcm:
|
||||
tegra_pcm_platform_unregister(&pdev->dev);
|
||||
err_unregister_dai:
|
||||
snd_soc_unregister_dai(&pdev->dev);
|
||||
err_clk_put:
|
||||
clk_put(ac97->clk_ac97);
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tegra20_ac97_platform_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
tegra_pcm_platform_unregister(&pdev->dev);
|
||||
snd_soc_unregister_dai(&pdev->dev);
|
||||
|
||||
tegra_asoc_utils_fini(&ac97->util_data);
|
||||
|
||||
clk_disable_unprepare(ac97->clk_ac97);
|
||||
clk_put(ac97->clk_ac97);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra20_ac97_of_match[] __devinitconst = {
|
||||
{ .compatible = "nvidia,tegra20-ac97", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver tegra20_ac97_driver = {
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra20_ac97_of_match,
|
||||
},
|
||||
.probe = tegra20_ac97_platform_probe,
|
||||
.remove = tegra20_ac97_platform_remove,
|
||||
};
|
||||
module_platform_driver(tegra20_ac97_driver);
|
||||
|
||||
MODULE_AUTHOR("Lucas Stach");
|
||||
MODULE_DESCRIPTION("Tegra20 AC97 ASoC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
MODULE_DEVICE_TABLE(of, tegra20_ac97_of_match);
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* tegra20_ac97.h - Definitions for the Tegra20 AC97 controller driver
|
||||
*
|
||||
* Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
|
||||
*
|
||||
* Partly based on code copyright/by:
|
||||
*
|
||||
* Copyright (c) 2011,2012 Toradex Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __TEGRA20_AC97_H__
|
||||
#define __TEGRA20_AC97_H__
|
||||
|
||||
#include "tegra_pcm.h"
|
||||
|
||||
#define TEGRA20_AC97_CTRL 0x00
|
||||
#define TEGRA20_AC97_CMD 0x04
|
||||
#define TEGRA20_AC97_STATUS1 0x08
|
||||
/* ... */
|
||||
#define TEGRA20_AC97_FIFO1_SCR 0x1c
|
||||
/* ... */
|
||||
#define TEGRA20_AC97_FIFO_TX1 0x40
|
||||
#define TEGRA20_AC97_FIFO_RX1 0x80
|
||||
|
||||
/* TEGRA20_AC97_CTRL */
|
||||
#define TEGRA20_AC97_CTRL_STM2_EN (1 << 16)
|
||||
#define TEGRA20_AC97_CTRL_DOUBLE_SAMPLING_EN (1 << 11)
|
||||
#define TEGRA20_AC97_CTRL_IO_CNTRL_EN (1 << 10)
|
||||
#define TEGRA20_AC97_CTRL_HSET_DAC_EN (1 << 9)
|
||||
#define TEGRA20_AC97_CTRL_LINE2_DAC_EN (1 << 8)
|
||||
#define TEGRA20_AC97_CTRL_PCM_LFE_EN (1 << 7)
|
||||
#define TEGRA20_AC97_CTRL_PCM_SUR_EN (1 << 6)
|
||||
#define TEGRA20_AC97_CTRL_PCM_CEN_DAC_EN (1 << 5)
|
||||
#define TEGRA20_AC97_CTRL_LINE1_DAC_EN (1 << 4)
|
||||
#define TEGRA20_AC97_CTRL_PCM_DAC_EN (1 << 3)
|
||||
#define TEGRA20_AC97_CTRL_COLD_RESET (1 << 2)
|
||||
#define TEGRA20_AC97_CTRL_WARM_RESET (1 << 1)
|
||||
#define TEGRA20_AC97_CTRL_STM_EN (1 << 0)
|
||||
|
||||
/* TEGRA20_AC97_CMD */
|
||||
#define TEGRA20_AC97_CMD_CMD_ADDR_SHIFT 24
|
||||
#define TEGRA20_AC97_CMD_CMD_ADDR_MASK (0xff << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT)
|
||||
#define TEGRA20_AC97_CMD_CMD_DATA_SHIFT 8
|
||||
#define TEGRA20_AC97_CMD_CMD_DATA_MASK (0xffff << TEGRA20_AC97_CMD_CMD_DATA_SHIFT)
|
||||
#define TEGRA20_AC97_CMD_CMD_ID_SHIFT 2
|
||||
#define TEGRA20_AC97_CMD_CMD_ID_MASK (0x3 << TEGRA20_AC97_CMD_CMD_ID_SHIFT)
|
||||
#define TEGRA20_AC97_CMD_BUSY (1 << 0)
|
||||
|
||||
/* TEGRA20_AC97_STATUS1 */
|
||||
#define TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT 24
|
||||
#define TEGRA20_AC97_STATUS1_STA_ADDR1_MASK (0xff << TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT)
|
||||
#define TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT 8
|
||||
#define TEGRA20_AC97_STATUS1_STA_DATA1_MASK (0xffff << TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT)
|
||||
#define TEGRA20_AC97_STATUS1_STA_VALID1 (1 << 2)
|
||||
#define TEGRA20_AC97_STATUS1_STANDBY1 (1 << 1)
|
||||
#define TEGRA20_AC97_STATUS1_CODEC1_RDY (1 << 0)
|
||||
|
||||
/* TEGRA20_AC97_FIFO1_SCR */
|
||||
#define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT 27
|
||||
#define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT)
|
||||
#define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT 22
|
||||
#define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT)
|
||||
#define TEGRA20_AC97_FIFO_SCR_REC_OVERRUN_INT_STA (1 << 19)
|
||||
#define TEGRA20_AC97_FIFO_SCR_PB_UNDERRUN_INT_STA (1 << 18)
|
||||
#define TEGRA20_AC97_FIFO_SCR_REC_FORCE_MT (1 << 17)
|
||||
#define TEGRA20_AC97_FIFO_SCR_PB_FORCE_MT (1 << 16)
|
||||
#define TEGRA20_AC97_FIFO_SCR_REC_FULL_EN (1 << 15)
|
||||
#define TEGRA20_AC97_FIFO_SCR_REC_3QRT_FULL_EN (1 << 14)
|
||||
#define TEGRA20_AC97_FIFO_SCR_REC_QRT_FULL_EN (1 << 13)
|
||||
#define TEGRA20_AC97_FIFO_SCR_REC_EMPTY_EN (1 << 12)
|
||||
#define TEGRA20_AC97_FIFO_SCR_PB_NOT_FULL_EN (1 << 11)
|
||||
#define TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN (1 << 10)
|
||||
#define TEGRA20_AC97_FIFO_SCR_PB_3QRT_MT_EN (1 << 9)
|
||||
#define TEGRA20_AC97_FIFO_SCR_PB_EMPTY_MT_EN (1 << 8)
|
||||
|
||||
struct tegra20_ac97 {
|
||||
struct clk *clk_ac97;
|
||||
struct tegra_pcm_dma_params capture_dma_data;
|
||||
struct tegra_pcm_dma_params playback_dma_data;
|
||||
struct regmap *regmap;
|
||||
int reset_gpio;
|
||||
int sync_gpio;
|
||||
struct tegra_asoc_utils_data util_data;
|
||||
};
|
||||
#endif /* __TEGRA20_AC97_H__ */
|
||||
Loading…
Reference in New Issue