mirror of https://gitee.com/openkylin/linux.git
[media] cx25821: fix sparse warnings
drivers/media/pci/cx25821/cx25821-cards.c:49:20: warning: symbol 'cx25821_bcount' was not declared. Should it be static? drivers/media/pci/cx25821/cx25821-video-upstream.c:162:33: warning: incorrect type in assignment (different base types) drivers/media/pci/cx25821/cx25821-video-upstream.c:163:33: warning: incorrect type in assignment (different base types) drivers/media/pci/cx25821/cx25821-video-upstream.c:164:33: warning: incorrect type in assignment (different base types) drivers/media/pci/cx25821/cx25821-video-upstream.c:165:33: warning: incorrect type in assignment (different base types) drivers/media/pci/cx25821/cx25821-medusa-video.h:43:16: warning: symbol '_num_decoders' was not declared. Should it be static? drivers/media/pci/cx25821/cx25821-medusa-video.h:44:16: warning: symbol '_num_cameras' was not declared. Should it be static? drivers/media/pci/cx25821/cx25821-medusa-video.h:46:14: warning: symbol '_video_standard' was not declared. Should it be static? drivers/media/pci/cx25821/cx25821-medusa-video.h:47:5: warning: symbol '_display_field_cnt' was not declared. Should it be static? After analyzing the last four warnings carefully it became clear that these variables were really completely unused. As a result of that the call to medusa_set_decoderduration() is now dubious since the duration is always 0. Without documentation, however, I can't tell what the right value is. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
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@ -45,5 +45,3 @@ struct cx25821_board cx25821_boards[] = {
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},
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};
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const unsigned int cx25821_bcount = ARRAY_SIZE(cx25821_boards);
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@ -438,7 +438,7 @@ void medusa_set_resolution(struct cx25821_dev *dev, int width,
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decoder_count = decoder_select + 1;
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} else {
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decoder = 0;
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decoder_count = _num_decoders;
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decoder_count = dev->_max_num_decoders;
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}
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switch (width) {
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@ -506,8 +506,6 @@ static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
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break;
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}
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_display_field_cnt[decoder] = duration;
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/* update hardware */
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fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp);
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@ -667,8 +665,6 @@ int medusa_video_init(struct cx25821_dev *dev)
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int ret_val = 0;
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int i = 0;
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_num_decoders = dev->_max_num_decoders;
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/* disable Auto source selection on all video decoders */
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value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
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value &= 0xFFFFF0FF;
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@ -685,8 +681,14 @@ int medusa_video_init(struct cx25821_dev *dev)
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if (ret_val < 0)
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goto error;
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for (i = 0; i < _num_decoders; i++)
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medusa_set_decoderduration(dev, i, _display_field_cnt[i]);
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/*
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* FIXME: due to a coding bug the duration was always 0. It's
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* likely that it really should be something else, but due to the
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* lack of documentation I have no idea what it should be. For
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* now just fill in 0 as the duration.
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*/
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for (i = 0; i < dev->_max_num_decoders; i++)
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medusa_set_decoderduration(dev, i, 0);
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/* Select monitor as DENC A input, power up the DAC */
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value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp);
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@ -717,7 +719,7 @@ int medusa_video_init(struct cx25821_dev *dev)
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/* Turn on all of the data out and control output pins. */
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value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp);
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value &= 0xFEF0FE00;
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if (_num_decoders == MAX_DECODERS) {
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if (dev->_max_num_decoders == MAX_DECODERS) {
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/*
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* Note: The octal board does not support control pins(bit16-19)
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* These bits are ignored in the octal board.
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@ -40,10 +40,4 @@
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#define CONTRAST_DEFAULT 5000
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#define HUE_DEFAULT 5000
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unsigned short _num_decoders;
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unsigned short _num_cameras;
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unsigned int _video_standard;
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int _display_field_cnt[MAX_DECODERS];
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#endif
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@ -159,10 +159,10 @@ static __le32 *cx25821_risc_field_upstream(struct cx25821_channel *chan, __le32
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* For the upstream video channel, the risc engine will enable
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* the FIFO. */
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if (fifo_enable && line == 3) {
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*(rp++) = RISC_WRITECR;
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*(rp++) = sram_ch->dma_ctl;
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*(rp++) = FLD_VID_FIFO_EN;
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*(rp++) = 0x00000001;
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*(rp++) = cpu_to_le32(RISC_WRITECR);
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*(rp++) = cpu_to_le32(sram_ch->dma_ctl);
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*(rp++) = cpu_to_le32(FLD_VID_FIFO_EN);
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*(rp++) = cpu_to_le32(0x00000001);
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}
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}
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